mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-06-04 13:29:29 +00:00
18 lines
381 B
Plaintext
18 lines
381 B
Plaintext
|
[ActiveSupport TRCE]
|
||
|
; Setup Analysis
|
||
|
Fmax_0 = 47.556 MHz (2.900 MHz);
|
||
|
Fmax_1 = 150.150 MHz (2.900 MHz);
|
||
|
Fmax_2 = 150.150 MHz (2.900 MHz);
|
||
|
Fmax_3 = 102.312 MHz (62.500 MHz);
|
||
|
Failed = 0 (Total 4);
|
||
|
Clock_ports = 4;
|
||
|
Clock_nets = 4;
|
||
|
; Hold Analysis
|
||
|
Fmax_0 = - (-);
|
||
|
Fmax_1 = - (-);
|
||
|
Fmax_2 = - (-);
|
||
|
Fmax_3 = - (-);
|
||
|
Failed = 0 (Total 4);
|
||
|
Clock_ports = 4;
|
||
|
Clock_nets = 4;
|