mirror of
https://github.com/garrettsworkshop/RAM2GS.git
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164 lines
8.4 KiB
Plaintext
164 lines
8.4 KiB
Plaintext
# Sat Aug 19 21:54:50 2023
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
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Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 139MB)
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Reading constraint file: Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc
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@L: Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt
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See clock summary report "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
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@N: FX493 |Applying initial value "0" on instance InitReady.
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@N: FX493 |Applying initial value "0" on instance Ready.
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@N: FX493 |Applying initial value "0" on instance RCKE.
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@N: FX493 |Applying initial value "0" on instance LEDEN.
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@N: FX493 |Applying initial value "0" on instance n8MEGEN.
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@N: FX493 |Applying initial value "1" on instance nRCAS.
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@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
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@N: FX493 |Applying initial value "0" on instance CmdUFMShift.
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@N: FX493 |Applying initial value "0" on instance CmdUFMWrite.
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@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
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@N: FX493 |Applying initial value "0" on instance CmdValid.
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@N: FX493 |Applying initial value "1" on instance nRCS.
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@N: FX493 |Applying initial value "1" on instance nRRAS.
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@N: FX493 |Applying initial value "0" on instance CmdUFMData.
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@N: FX493 |Applying initial value "0" on instance C1Submitted.
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@N: FX493 |Applying initial value "0" on instance ADSubmitted.
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@N: FX493 |Applying initial value "0" on instance XOR8MEG.
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@N: FX493 |Applying initial value "0" on instance CmdEnable.
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@N: FX493 |Applying initial value "1" on instance nRWE.
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Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
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Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
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Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
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Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
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@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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----------------------------------------------------------------------------------------
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0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65
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0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
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0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
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0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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========================================================================================
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Clock Load Summary
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***********************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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-----------------------------------------------------------------------------------------
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RCLK 65 RCLK(port) CASr2.C - -
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PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
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nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
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nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
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System 0 - - - -
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=========================================================================================
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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For details review file gcc_ICG_report.rpt
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@S |Clock Optimization Summary
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#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
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4 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------
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@KP:ckid0_0 RCLK port 65 nRWE
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@KP:ckid0_1 PHI2 port 19 RA11
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@KP:ckid0_2 nCCAS port 8 WRD[7:0]
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@KP:ckid0_3 nCRAS port 14 RowA[9:0]
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=======================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######
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@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
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Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 184MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sat Aug 19 21:54:51 2023
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###########################################################]
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