mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-25 15:33:32 +00:00
135 lines
6.4 KiB
Plaintext
135 lines
6.4 KiB
Plaintext
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: 5
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: 6
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: M
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
// Design: RAM2GS
|
|
// Package: TQFP100
|
|
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
|
// Version: Diamond (64-bit) 3.12.1.454
|
|
// Written on Thu Sep 21 05:40:06 2023
|
|
// M: Minimum Performance Grade
|
|
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
|
|
|
I/O Timing Report (All units are in ns)
|
|
|
|
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|
|
|
// Input Setup and Hold Times
|
|
|
|
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
|
----------------------------------------------------------------------
|
|
CROW[0] nCRAS F 2.913 4 -0.274 M
|
|
CROW[1] nCRAS F 2.475 4 -0.161 M
|
|
Din[0] PHI2 F 5.366 4 4.293 4
|
|
Din[0] nCCAS F 1.448 4 -0.034 M
|
|
Din[1] PHI2 F 4.971 4 4.173 4
|
|
Din[1] nCCAS F 0.519 4 0.708 4
|
|
Din[2] PHI2 F 5.192 4 4.173 4
|
|
Din[2] nCCAS F 1.948 4 -0.142 M
|
|
Din[3] PHI2 F 5.298 4 4.173 4
|
|
Din[3] nCCAS F 1.974 4 -0.157 M
|
|
Din[4] PHI2 F 4.281 4 4.173 4
|
|
Din[4] nCCAS F 1.060 4 0.217 4
|
|
Din[5] PHI2 F 5.059 4 4.173 4
|
|
Din[5] nCCAS F 1.956 4 -0.150 M
|
|
Din[6] PHI2 F 4.644 4 4.293 4
|
|
Din[6] nCCAS F 2.886 4 -0.382 M
|
|
Din[7] PHI2 F 5.316 4 4.293 4
|
|
Din[7] nCCAS F 2.381 4 -0.244 M
|
|
MAin[0] PHI2 F 4.362 4 1.145 4
|
|
MAin[0] nCRAS F 1.189 4 0.362 4
|
|
MAin[1] PHI2 F 4.386 4 0.999 4
|
|
MAin[1] nCRAS F 1.884 4 -0.024 M
|
|
MAin[2] PHI2 F 9.426 4 -0.750 M
|
|
MAin[2] nCRAS F 1.136 4 0.453 4
|
|
MAin[3] PHI2 F 10.458 4 -0.997 M
|
|
MAin[3] nCRAS F 1.564 4 0.067 4
|
|
MAin[4] PHI2 F 11.109 4 -1.209 M
|
|
MAin[4] nCRAS F 1.390 4 0.207 4
|
|
MAin[5] PHI2 F 9.884 4 -0.896 M
|
|
MAin[5] nCRAS F 1.269 4 0.218 4
|
|
MAin[6] PHI2 F 9.859 4 -0.845 M
|
|
MAin[6] nCRAS F 0.889 4 0.653 4
|
|
MAin[7] PHI2 F 10.678 4 -1.070 M
|
|
MAin[7] nCRAS F 1.186 4 0.309 4
|
|
MAin[8] nCRAS F 1.639 4 0.014 M
|
|
MAin[9] nCRAS F 1.097 4 0.457 4
|
|
PHI2 RCLK R -0.133 M 2.360 4
|
|
nCCAS RCLK R 2.943 4 -0.337 M
|
|
nCCAS nCRAS F 2.967 4 -0.214 M
|
|
nCRAS RCLK R 3.047 4 -0.402 M
|
|
nFWE PHI2 F 11.116 4 -1.189 M
|
|
nFWE nCRAS F 1.394 4 0.225 4
|
|
|
|
|
|
// Clock to Output Delay
|
|
|
|
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
|
------------------------------------------------------------------------
|
|
LED RCLK R 11.046 4 3.298 M
|
|
LED nCRAS F 11.710 4 3.359 M
|
|
RA[0] RCLK R 11.397 4 3.516 M
|
|
RA[0] nCRAS F 11.476 4 3.432 M
|
|
RA[10] RCLK R 7.888 4 2.711 M
|
|
RA[11] PHI2 R 9.755 4 3.200 M
|
|
RA[1] RCLK R 11.272 4 3.469 M
|
|
RA[1] nCRAS F 11.238 4 3.348 M
|
|
RA[2] RCLK R 11.235 4 3.468 M
|
|
RA[2] nCRAS F 11.665 4 3.453 M
|
|
RA[3] RCLK R 11.390 4 3.512 M
|
|
RA[3] nCRAS F 11.922 4 3.539 M
|
|
RA[4] RCLK R 11.662 4 3.573 M
|
|
RA[4] nCRAS F 11.818 4 3.505 M
|
|
RA[5] RCLK R 11.744 4 3.584 M
|
|
RA[5] nCRAS F 11.779 4 3.513 M
|
|
RA[6] RCLK R 11.738 4 3.607 M
|
|
RA[6] nCRAS F 11.836 4 3.531 M
|
|
RA[7] RCLK R 12.475 4 3.797 M
|
|
RA[7] nCRAS F 11.420 4 3.426 M
|
|
RA[8] RCLK R 11.122 4 3.431 M
|
|
RA[8] nCRAS F 11.667 4 3.471 M
|
|
RA[9] RCLK R 11.935 4 3.649 M
|
|
RA[9] nCRAS F 11.401 4 3.424 M
|
|
RBA[0] nCRAS F 8.903 4 2.891 M
|
|
RBA[1] nCRAS F 8.903 4 2.891 M
|
|
RCKE RCLK R 10.011 4 3.215 M
|
|
RDQMH RCLK R 10.790 4 3.354 M
|
|
RDQML RCLK R 11.053 4 3.450 M
|
|
RD[0] nCCAS F 8.977 4 3.012 M
|
|
RD[1] nCCAS F 8.977 4 3.012 M
|
|
RD[2] nCCAS F 8.977 4 3.012 M
|
|
RD[3] nCCAS F 8.977 4 3.012 M
|
|
RD[4] nCCAS F 8.977 4 3.012 M
|
|
RD[5] nCCAS F 8.977 4 3.012 M
|
|
RD[6] nCCAS F 8.977 4 3.012 M
|
|
RD[7] nCCAS F 8.977 4 3.012 M
|
|
nRCAS RCLK R 7.822 4 2.706 M
|
|
nRCS RCLK R 7.822 4 2.706 M
|
|
nRRAS RCLK R 7.822 4 2.706 M
|
|
nRWE RCLK R 7.803 4 2.713 M
|
|
WARNING: you must also run trce with hold speed: 4
|
|
WARNING: you must also run trce with setup speed: M
|