Apple-2-HW/RAM2GS
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RAM2GS/cpld/db/RAM4GS.hier_info
Zane Kaminski f99d3e4b9a Add GW4201D files
2020-07-25 04:32:25 -04:00

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|RAM4GS
PHI2 => Bank[0].CLK
PHI2 => Bank[1].CLK
PHI2 => Bank[2].CLK
PHI2 => Bank[3].CLK
PHI2 => Bank[4].CLK
PHI2 => Bank[5].CLK
PHI2 => Bank[6].CLK
PHI2 => Bank[7].CLK
PHI2 => RA11.CLK
PHI2 => PHI2r.DATAIN
PHI2 => CmdDRDIn.CLK
PHI2 => CmdDRCLK.CLK
PHI2 => CmdUFMPrgm.CLK
PHI2 => CmdUFMErase.CLK
PHI2 => CmdSubmitted.CLK
PHI2 => Cmdn8MEGEN.CLK
PHI2 => XOR8MEG.CLK
PHI2 => ADSubmitted.CLK
PHI2 => C1Submitted.CLK
PHI2 => UFMOscEN.CLK
PHI2 => CmdEnable.CLK
MAin[0] => RA.DATAA
MAin[0] => RowA.DATAB
MAin[0] => Equal0.IN7
MAin[0] => Equal1.IN7
MAin[0] => Equal3.IN6
MAin[1] => RA.DATAA
MAin[1] => RowA.DATAB
MAin[1] => Equal0.IN6
MAin[1] => Equal1.IN6
MAin[1] => Equal3.IN7
MAin[2] => RA.DATAA
MAin[2] => RowA.DATAB
MAin[2] => Equal0.IN5
MAin[2] => Equal1.IN5
MAin[2] => Equal3.IN5
MAin[3] => RA.DATAA
MAin[3] => RowA.DATAB
MAin[3] => Equal0.IN4
MAin[3] => Equal1.IN4
MAin[3] => Equal3.IN4
MAin[4] => RA.DATAA
MAin[4] => RowA.DATAB
MAin[4] => Equal0.IN3
MAin[4] => Equal1.IN3
MAin[4] => Equal3.IN3
MAin[5] => RA.DATAA
MAin[5] => RowA.DATAB
MAin[5] => Equal0.IN2
MAin[5] => Equal1.IN2
MAin[5] => Equal3.IN2
MAin[6] => RA.DATAA
MAin[6] => RowA.DATAB
MAin[6] => Equal0.IN1
MAin[6] => Equal1.IN1
MAin[6] => Equal3.IN1
MAin[7] => RA.DATAA
MAin[7] => RowA.DATAB
MAin[7] => Equal0.IN0
MAin[7] => Equal1.IN0
MAin[7] => Equal3.IN0
MAin[8] => RA.DATAA
MAin[8] => RowA.DATAB
MAin[9] => RA.DATAA
MAin[9] => comb.DATAA
MAin[9] => RowA.DATAB
MAin[9] => comb.DATAA
CROW[0] => RBA.DATAB
CROW[1] => RBA.DATAB
Din[0] => CmdDRDIn.DATAB
Din[0] => XOR8MEG.DATAB
Din[0] => WRD[0].DATAIN
Din[0] => Bank[0].DATAIN
Din[0] => Equal14.IN2
Din[0] => Equal15.IN4
Din[0] => Cmdn8MEGEN.DATAB
Din[1] => CmdDRCLK.DATAB
Din[1] => WRD[1].DATAIN
Din[1] => Bank[1].DATAIN
Din[1] => Equal14.IN7
Din[1] => Equal15.IN7
Din[2] => CmdUFMPrgm.DATAB
Din[2] => WRD[2].DATAIN
Din[2] => Bank[2].DATAIN
Din[2] => Equal14.IN6
Din[2] => Equal15.IN3
Din[3] => CmdUFMErase.DATAB
Din[3] => WRD[3].DATAIN
Din[3] => Bank[3].DATAIN
Din[3] => Equal14.IN5
Din[3] => Equal15.IN2
Din[4] => WRD[4].DATAIN
Din[4] => Bank[4].DATAIN
Din[4] => Equal14.IN4
Din[4] => Equal15.IN6
Din[4] => Equal16.IN3
Din[4] => Equal17.IN0
Din[4] => Equal18.IN3
Din[5] => WRD[5].DATAIN
Din[5] => Bank[5].DATAIN
Din[5] => Equal14.IN3
Din[5] => Equal15.IN1
Din[5] => Equal16.IN2
Din[5] => Equal17.IN3
Din[5] => Equal18.IN0
Din[6] => RA11.IN1
Din[6] => WRD[6].DATAIN
Din[6] => Bank[6].DATAIN
Din[6] => Equal14.IN1
Din[6] => Equal15.IN5
Din[6] => Equal16.IN1
Din[6] => Equal17.IN2
Din[6] => Equal18.IN2
Din[7] => WRD[7].DATAIN
Din[7] => Bank[7].DATAIN
Din[7] => Equal14.IN0
Din[7] => Equal15.IN0
Din[7] => Equal16.IN0
Din[7] => Equal17.IN1
Din[7] => Equal18.IN1
Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
nCCAS => WRD[0].CLK
nCCAS => WRD[1].CLK
nCCAS => WRD[2].CLK
nCCAS => WRD[3].CLK
nCCAS => WRD[4].CLK
nCCAS => WRD[5].CLK
nCCAS => WRD[6].CLK
nCCAS => WRD[7].CLK
nCCAS => comb.IN0
nCCAS => CBR.DATAIN
nCCAS => CASr.DATAIN
nCRAS => CBR.CLK
nCRAS => FWEr.CLK
nCRAS => RowA[0].CLK
nCRAS => RowA[1].CLK
nCRAS => RowA[2].CLK
nCRAS => RowA[3].CLK
nCRAS => RowA[4].CLK
nCRAS => RowA[5].CLK
nCRAS => RowA[6].CLK
nCRAS => RowA[7].CLK
nCRAS => RowA[8].CLK
nCRAS => RowA[9].CLK
nCRAS => RBA[0]~reg0.CLK
nCRAS => RBA[1]~reg0.CLK
nCRAS => RASr.DATAIN
nFWE => comb.IN1
nFWE => CMDWR.IN1
nFWE => ADWR.IN1
nFWE => C1WR.IN1
nFWE => FWEr.DATAIN
RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCLK => UFMProgram.CLK
RCLK => UFMErase.CLK
RCLK => UFMReqErase.CLK
RCLK => n8MEGEN.CLK
RCLK => UFMInitDone.CLK
RCLK => UFMD.CLK
RCLK => DRShift.CLK
RCLK => DRDIn.CLK
RCLK => DRCLK.CLK
RCLK => ARShift.CLK
RCLK => ARCLK.CLK
RCLK => Ready.CLK
RCLK => IS[0].CLK
RCLK => IS[1].CLK
RCLK => IS[2].CLK
RCLK => IS[3].CLK
RCLK => nRowColSel.CLK
RCLK => RCKEEN.CLK
RCLK => RA10.CLK
RCLK => nRWE~reg0.CLK
RCLK => nRCAS~reg0.CLK
RCLK => nRRAS~reg0.CLK
RCLK => nRCS~reg0.CLK
RCLK => RCKE~reg0.CLK
RCLK => InitReady.CLK
RCLK => FS[0].CLK
RCLK => FS[1].CLK
RCLK => FS[2].CLK
RCLK => FS[3].CLK
RCLK => FS[4].CLK
RCLK => FS[5].CLK
RCLK => FS[6].CLK
RCLK => FS[7].CLK
RCLK => FS[8].CLK
RCLK => FS[9].CLK
RCLK => FS[10].CLK
RCLK => FS[11].CLK
RCLK => FS[12].CLK
RCLK => FS[13].CLK
RCLK => FS[14].CLK
RCLK => FS[15].CLK
RCLK => FS[16].CLK
RCLK => FS[17].CLK
RCLK => S[0].CLK
RCLK => S[1].CLK
RCLK => CASr3.CLK
RCLK => CASr2.CLK
RCLK => CASr.CLK
RCLK => RASr3.CLK
RCLK => RASr2.CLK
RCLK => RASr.CLK
RCLK => PHI2r3.CLK
RCLK => PHI2r2.CLK
RCLK => PHI2r.CLK
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
|RAM4GS|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY
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