mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2025-02-20 09:29:07 +00:00
424 lines
17 KiB
Plaintext
424 lines
17 KiB
Plaintext
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Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-640HC
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Package: TQFP100
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Performance: 4
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Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
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Sat Aug 19 21:54:58 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
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Design file: lcmxo2_640hc_impl1_map.ncd
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Preference file: lcmxo2_640hc_impl1.prf
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Device,speed: LCMXO2-640HC,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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158 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q Bank_0io[2] (from PHI2_c +)
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Destination: FF Data in ADSubmitted (to PHI2_c -)
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Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
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Constraint Details:
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9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
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172.414ns delay constraint less
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0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
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Physical Path Details:
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Data path Din[2]_MGIOL to SLICE_10:
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Name Fanout Delay (ns) Site Resource
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C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
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ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
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CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
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ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
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CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
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ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
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CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
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ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
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CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
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ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
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CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
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ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
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--------
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9.223 (33.1% logic, 66.9% route), 6 logic levels.
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Report: 53.254MHz is the maximum frequency for this preference.
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================================================================================
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Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 338.168ns
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The internal maximum frequency of the following component is 150.150 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCCAS
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Delay: 6.660ns -- based on Minimum Pulse Width
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Report: 150.150MHz is the maximum frequency for this preference.
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================================================================================
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Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 338.168ns
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The internal maximum frequency of the following component is 150.150 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCRAS
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Delay: 6.660ns -- based on Minimum Pulse Width
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Report: 150.150MHz is the maximum frequency for this preference.
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================================================================================
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Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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844 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 6.226ns
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The internal maximum frequency of the following component is 102.312 MHz
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Logical Details: Cell type Pin name Component name
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Destination: EFB WBCLKI ufmefb/EFBInst_0
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Delay: 9.774ns -- based on Minimum Pulse Width
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Passed: The following path meets requirements by 6.270ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q S[0] (from RCLK_c +)
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Destination: FF Data in nRCS_0io (to RCLK_c +)
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Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
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Constraint Details:
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9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
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16.000ns delay constraint less
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0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
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Physical Path Details:
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Data path SLICE_16 to nRCS_MGIOL:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
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ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
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CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
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ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
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CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
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ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
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CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
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ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
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CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
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ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
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CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
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ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
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--------
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9.577 (30.6% logic, 69.4% route), 6 logic levels.
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Report: 102.312MHz is the maximum frequency for this preference.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Timing summary (Setup):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
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Sat Aug 19 21:54:58 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
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Copyright (c) 1995 AT&T Corp. All rights reserved.
|
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
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Copyright (c) 2001 Agere Systems All rights reserved.
|
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
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|
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
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Design file: lcmxo2_640hc_impl1_map.ncd
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Preference file: lcmxo2_640hc_impl1.prf
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Device,speed: LCMXO2-640HC,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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158 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q ADSubmitted (from PHI2_c -)
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Destination: FF Data in ADSubmitted (to PHI2_c -)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay SLICE_10 to SLICE_10 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path SLICE_10 to SLICE_10:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
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ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
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CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
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ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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================================================================================
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Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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844 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.351ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q CASr (from RCLK_c +)
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Destination: FF Data in CASr2 (to RCLK_c +)
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Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
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Constraint Details:
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0.332ns physical path delay SLICE_12 to SLICE_12 meets
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-0.019ns M_HLD and
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0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
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Physical Path Details:
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Data path SLICE_12 to SLICE_12:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
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ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
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--------
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0.332 (40.1% logic, 59.9% route), 1 logic levels.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Timing summary (Hold):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
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Timing summary (Setup and Hold):
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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