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RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_twr.html
Zane Kaminski a59177004e MAX, MachXO, MachXO2 working
2023-08-20 07:10:11 -04:00

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<HTML>
<HEAD><TITLE>Lattice TRACE Report</TITLE>
<STYLE TYPE="text/css">
<!--
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
-->
</STYLE>
</HEAD>
<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Aug 19 21:55:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
Report: 47.556MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
Report: 102.312MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 161.900ns (weighted slack = 323.800ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 10.175ns (30.0% logic, 70.0% route), 6 logic levels.
Constraint Details:
10.175ns physical path delay Din[6]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 161.900ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7
CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11
ROUTE 3 1.018 R5C8D.F1 to R4C8D.B0 CmdEnable16
CTOF_DEL --- 0.495 R4C8D.B0 to R4C8D.F0 SLICE_10
ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c)
--------
10.175 (30.0% logic, 70.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R4C8D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.099ns (weighted slack = 324.198ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdValid (to PHI2_c -)
Delay: 9.976ns (30.6% logic, 69.4% route), 6 logic levels.
Constraint Details:
9.976ns physical path delay Din[6]_MGIOL to SLICE_23 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.099ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_23:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7
CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24
ROUTE 8 0.808 R5C7A.F1 to R5C6D.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C6D.C0 to R5C6D.F0 SLICE_23
ROUTE 1 0.000 R5C6D.F0 to R5C6D.DI0 CmdValid_r (to PHI2_c)
--------
9.976 (30.6% logic, 69.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R5C6D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.113ns (weighted slack = 324.226ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 9.821ns (26.0% logic, 74.0% route), 5 logic levels.
Constraint Details:
9.821ns physical path delay Din[6]_MGIOL to SLICE_18 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 162.113ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_18:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7
CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24
ROUTE 8 1.148 R5C7A.F1 to R4C6C.CE XOR8MEG18 (to PHI2_c)
--------
9.821 (26.0% logic, 74.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R4C6C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.113ns (weighted slack = 324.226ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 9.821ns (26.0% logic, 74.0% route), 5 logic levels.
Constraint Details:
9.821ns physical path delay Din[6]_MGIOL to SLICE_25 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 162.113ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_25:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7
CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24
ROUTE 8 1.148 R5C7A.F1 to R4C6A.CE XOR8MEG18 (to PHI2_c)
--------
9.821 (26.0% logic, 74.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_25:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R4C6A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.197ns (weighted slack = 324.394ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdValid_fast (to PHI2_c -)
Delay: 9.878ns (30.9% logic, 69.1% route), 6 logic levels.
Constraint Details:
9.878ns physical path delay Din[6]_MGIOL to SLICE_24 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.197ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_24:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7
CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24
ROUTE 8 0.710 R5C7A.F1 to R5C7A.B0 XOR8MEG18
CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_24
ROUTE 1 0.000 R5C7A.F0 to R5C7A.DI0 N_36_fast (to PHI2_c)
--------
9.878 (30.9% logic, 69.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R5C7A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.260ns (weighted slack = 324.520ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[5] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.815ns (31.1% logic, 68.9% route), 6 logic levels.
Constraint Details:
9.815ns physical path delay Din[5]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.260ns
Physical Path Details:
Data path Din[5]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c)
ROUTE 1 1.753 IOL_T6B.IN to R4C7B.B1 Bank[5]
CTOF_DEL --- 0.495 R4C7B.B1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7
CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11
ROUTE 3 1.018 R5C8D.F1 to R4C8D.B0 CmdEnable16
CTOF_DEL --- 0.495 R4C8D.B0 to R4C8D.F0 SLICE_10
ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c)
--------
9.815 (31.1% logic, 68.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_T6B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R4C8D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.335ns (weighted slack = 324.670ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.740ns (31.3% logic, 68.7% route), 6 logic levels.
Constraint Details:
9.740ns physical path delay Din[7]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.335ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 1.678 IOL_L2A.IN to R4C7B.D1 Bank[7]
CTOF_DEL --- 0.495 R4C7B.D1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7
CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11
ROUTE 3 1.018 R5C8D.F1 to R4C8D.B0 CmdEnable16
CTOF_DEL --- 0.495 R4C8D.B0 to R4C8D.F0 SLICE_10
ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c)
--------
9.740 (31.3% logic, 68.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R4C8D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.452ns (weighted slack = 324.904ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 9.623ns (30.5% logic, 69.5% route), 6 logic levels.
Constraint Details:
9.623ns physical path delay Din[6]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.452ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7
CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11
ROUTE 3 0.585 R5C8D.F1 to R5C8A.M0 CmdEnable16
MTOOFX_DEL --- 0.376 R5C8A.M0 to R5C8A.OFX0 SLICE_17
ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c)
--------
9.623 (30.5% logic, 69.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R5C8A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.459ns (weighted slack = 324.918ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[5] (from PHI2_c +)
Destination: FF Data in CmdValid (to PHI2_c -)
Delay: 9.616ns (31.7% logic, 68.3% route), 6 logic levels.
Constraint Details:
9.616ns physical path delay Din[5]_MGIOL to SLICE_23 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.459ns
Physical Path Details:
Data path Din[5]_MGIOL to SLICE_23:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c)
ROUTE 1 1.753 IOL_T6B.IN to R4C7B.B1 Bank[5]
CTOF_DEL --- 0.495 R4C7B.B1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.040 R5C8B.F0 to R5C7A.B1 C1WR_7
CTOF_DEL --- 0.495 R5C7A.B1 to R5C7A.F1 SLICE_24
ROUTE 8 0.808 R5C7A.F1 to R5C6D.C0 XOR8MEG18
CTOF_DEL --- 0.495 R5C6D.C0 to R5C6D.F0 SLICE_23
ROUTE 1 0.000 R5C6D.F0 to R5C6D.DI0 CmdValid_r (to PHI2_c)
--------
9.616 (31.7% logic, 68.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_T6B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R5C6D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.465ns (weighted slack = 324.930ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 9.610ns (31.8% logic, 68.2% route), 6 logic levels.
Constraint Details:
9.610ns physical path delay Din[6]_MGIOL to SLICE_11 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 162.465ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_11:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 2.113 IOL_L2B.IN to R4C7B.A1 Bank[6]
CTOF_DEL --- 0.495 R4C7B.A1 to R4C7B.F1 SLICE_37
ROUTE 1 1.336 R4C7B.F1 to R2C6D.B0 un1_Bank_1_4
CTOF_DEL --- 0.495 R2C6D.B0 to R2C6D.F0 SLICE_94
ROUTE 2 1.627 R2C6D.F0 to R5C8B.C0 N_304
CTOF_DEL --- 0.495 R5C8B.C0 to R5C8B.F0 SLICE_90
ROUTE 5 1.029 R5C8B.F0 to R5C8D.B1 C1WR_7
CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 SLICE_11
ROUTE 3 0.453 R5C8D.F1 to R5C8D.C0 CmdEnable16
CTOF_DEL --- 0.495 R5C8D.C0 to R5C8D.F0 SLICE_11
ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_s (to PHI2_c)
--------
9.610 (31.8% logic, 68.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.712 8.PADDI to IOL_L2B.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 22 3.539 8.PADDI to R5C8D.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Report: 47.556MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.226ns
The internal maximum frequency of the following component is 102.312 MHz
Logical Details: Cell type Pin name Component name
Destination: EFB WBCLKI ufmefb/EFBInst_0
Delay: 9.774ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 6.966ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in wb_dati[7] (to RCLK_c +)
Delay: 8.868ns (33.0% logic, 67.0% route), 6 logic levels.
Constraint Details:
8.868ns physical path delay SLICE_2 to SLICE_57 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 6.966ns
Physical Path Details:
Data path SLICE_2 to SLICE_57:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c)
ROUTE 5 1.615 R6C5A.Q0 to R4C5D.C1 FS[15]
CTOF_DEL --- 0.495 R4C5D.C1 to R4C5D.F1 SLICE_76
ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109
ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119
CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83
ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91
CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81
ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7]
CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57
ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
--------
8.868 (33.0% logic, 67.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R6C5A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.141ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[16] (from RCLK_c +)
Destination: FF Data in wb_dati[7] (to RCLK_c +)
Delay: 8.693ns (33.7% logic, 66.3% route), 6 logic levels.
Constraint Details:
8.693ns physical path delay SLICE_2 to SLICE_57 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.141ns
Physical Path Details:
Data path SLICE_2 to SLICE_57:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c)
ROUTE 5 1.440 R6C5A.Q1 to R4C5D.B1 FS[16]
CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_76
ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109
ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119
CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83
ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91
CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81
ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7]
CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57
ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
--------
8.693 (33.7% logic, 66.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R6C5A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.241ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in wb_dati[7] (to RCLK_c +)
Delay: 8.593ns (34.1% logic, 65.9% route), 6 logic levels.
Constraint Details:
8.593ns physical path delay SLICE_1 to SLICE_57 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.241ns
Physical Path Details:
Data path SLICE_1 to SLICE_57:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c)
ROUTE 5 1.340 R6C5B.Q0 to R4C5D.A1 FS[17]
CTOF_DEL --- 0.495 R4C5D.A1 to R4C5D.F1 SLICE_76
ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109
ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119
CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83
ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91
CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81
ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7]
CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57
ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
--------
8.593 (34.1% logic, 65.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R6C5B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.305ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from RCLK_c +)
Destination: FF Data in nRCS_0io (to RCLK_c +)
Delay: 8.715ns (33.6% logic, 66.4% route), 6 logic levels.
Constraint Details:
8.715ns physical path delay SLICE_16 to nRCS_MGIOL meets
16.000ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 16.020ns) by 7.305ns
Physical Path Details:
Data path SLICE_16 to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C11B.CLK to R5C11B.Q0 SLICE_16 (from RCLK_c)
ROUTE 9 1.105 R5C11B.Q0 to R6C10D.C0 CO0
CTOF_DEL --- 0.495 R6C10D.C0 to R6C10D.F0 SLICE_45
ROUTE 4 0.461 R6C10D.F0 to R6C10D.C1 N_41
CTOF_DEL --- 0.495 R6C10D.C1 to R6C10D.F1 SLICE_45
ROUTE 2 0.972 R6C10D.F1 to R5C11A.D0 nRRAS_5_u_i_0
CTOF_DEL --- 0.495 R5C11A.D0 to R5C11A.F0 SLICE_77
ROUTE 1 0.693 R5C11A.F0 to R5C10C.B1 N_25
CTOF_DEL --- 0.495 R5C10C.B1 to R5C10C.F1 SLICE_117
ROUTE 1 0.958 R5C10C.F1 to R6C11A.D1 N_28_i_sn
CTOF_DEL --- 0.495 R6C11A.D1 to R6C11A.F1 SLICE_88
ROUTE 1 1.599 R6C11A.F1 to IOL_R6D.OPOS N_28_i (to RCLK_c)
--------
8.715 (33.6% logic, 66.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R5C11B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.243 62.PADDI to IOL_R6D.CLK RCLK_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.392ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.269ns (81.9% logic, 18.1% route), 2 logic levels.
Constraint Details:
8.269ns physical path delay ufmefb/EFBInst_0 to SLICE_47 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 7.392ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_47:
Name Fanout Delay (ns) Site Resource
WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 1 1.496 EFB.WBDATO0 to R4C5B.C0 wb_dato[0]
CTOF_DEL --- 0.495 R4C5B.C0 to R4C5B.F0 SLICE_47
ROUTE 1 0.000 R4C5B.F0 to R4C5B.DI0 n8MEGEN_6 (to RCLK_c)
--------
8.269 (81.9% logic, 18.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.243 62.PADDI to EFB.WBCLKI RCLK_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_47:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R4C5B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.416ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q InitReady (from RCLK_c +)
Destination: FF Data in wb_dati[7] (to RCLK_c +)
Delay: 8.418ns (34.8% logic, 65.2% route), 6 logic levels.
Constraint Details:
8.418ns physical path delay SLICE_31 to SLICE_57 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.416ns
Physical Path Details:
Data path SLICE_31 to SLICE_57:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C4D.CLK to R5C4D.Q0 SLICE_31 (from RCLK_c)
ROUTE 33 1.165 R5C4D.Q0 to R4C5D.D1 InitReady
CTOF_DEL --- 0.495 R4C5D.D1 to R4C5D.F1 SLICE_76
ROUTE 18 1.137 R4C5D.F1 to R2C3D.D0 wb_rst11
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_109
ROUTE 4 1.749 R2C3D.F0 to R3C3D.A0 N_119
CTOF_DEL --- 0.495 R3C3D.A0 to R3C3D.F0 SLICE_83
ROUTE 1 0.747 R3C3D.F0 to R3C3B.C0 N_91
CTOF_DEL --- 0.495 R3C3B.C0 to R3C3B.F0 SLICE_81
ROUTE 1 0.693 R3C3B.F0 to R3C3A.B1 wb_dati_5_1_iv_0_1[7]
CTOF_DEL --- 0.495 R3C3A.B1 to R3C3A.F1 SLICE_57
ROUTE 1 0.000 R3C3A.F1 to R3C3A.DI1 wb_dati_5[7] (to RCLK_c)
--------
8.418 (34.8% logic, 65.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R5C4D.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.490ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.171ns (72.9% logic, 27.1% route), 2 logic levels.
Constraint Details:
8.171ns physical path delay ufmefb/EFBInst_0 to SLICE_32 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 7.490ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_32:
Name Fanout Delay (ns) Site Resource
WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 1 2.215 EFB.WBDATO1 to R4C6D.A0 wb_dato[1]
CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 SLICE_32
ROUTE 1 0.000 R4C6D.F0 to R4C6D.DI0 LEDEN_6 (to RCLK_c)
--------
8.171 (72.9% logic, 27.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.243 62.PADDI to EFB.WBCLKI RCLK_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R4C6D.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.546ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in wb_adr[1] (to RCLK_c +)
Delay: 8.288ns (29.3% logic, 70.7% route), 5 logic levels.
Constraint Details:
8.288ns physical path delay SLICE_3 to SLICE_49 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.546ns
Physical Path Details:
Data path SLICE_3 to SLICE_49:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c)
ROUTE 22 2.071 R6C4D.Q0 to R4C5A.B1 FS[13]
CTOF_DEL --- 0.495 R4C5A.B1 to R4C5A.F1 SLICE_82
ROUTE 2 0.982 R4C5A.F1 to R4C5C.A0 un1_FS_20_3
CTOF_DEL --- 0.495 R4C5C.A0 to R4C5C.F0 SLICE_87
ROUTE 2 0.993 R4C5C.F0 to R4C4B.A0 wb_we95
CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_84
ROUTE 1 1.810 R4C4B.F0 to R2C2A.A1 N_181
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_49
ROUTE 1 0.000 R2C2A.F1 to R2C2A.DI1 wb_adr_5[1] (to RCLK_c)
--------
8.288 (29.3% logic, 70.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R6C4D.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_49:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R2C2A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.583ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in wb_dati[6] (to RCLK_c +)
Delay: 8.251ns (35.5% logic, 64.5% route), 6 logic levels.
Constraint Details:
8.251ns physical path delay SLICE_2 to SLICE_57 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 7.583ns
Physical Path Details:
Data path SLICE_2 to SLICE_57:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c)
ROUTE 5 1.615 R6C5A.Q0 to R4C5D.C1 FS[15]
CTOF_DEL --- 0.495 R4C5D.C1 to R4C5D.F1 SLICE_76
ROUTE 18 1.137 R4C5D.F1 to R2C3D.D1 wb_rst11
CTOF_DEL --- 0.495 R2C3D.D1 to R2C3D.F1 SLICE_109
ROUTE 2 0.982 R2C3D.F1 to R2C3A.A1 N_246
CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 SLICE_74
ROUTE 1 0.967 R2C3A.F1 to R2C3A.A0 N_98
CTOF_DEL --- 0.495 R2C3A.A0 to R2C3A.F0 SLICE_74
ROUTE 1 0.623 R2C3A.F0 to R3C3A.D0 wb_dati_5_1_iv_0_1[6]
CTOF_DEL --- 0.495 R3C3A.D0 to R3C3A.F0 SLICE_57
ROUTE 1 0.000 R3C3A.F0 to R3C3A.DI0 wb_dati_5[6] (to RCLK_c)
--------
8.251 (35.5% logic, 64.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R6C5A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R3C3A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.586ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2 (from RCLK_c +)
Destination: FF Data in nRCS_0io (to RCLK_c +)
Delay: 8.434ns (28.8% logic, 71.2% route), 5 logic levels.
Constraint Details:
8.434ns physical path delay SLICE_34 to nRCS_MGIOL meets
16.000ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 16.020ns) by 7.586ns
Physical Path Details:
Data path SLICE_34 to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 SLICE_34 (from RCLK_c)
ROUTE 10 1.972 R6C7A.Q1 to R5C11C.A1 RASr2
CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_63
ROUTE 7 0.780 R5C11C.F1 to R5C11A.C0 N_250
CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_77
ROUTE 1 0.693 R5C11A.F0 to R5C10C.B1 N_25
CTOF_DEL --- 0.495 R5C10C.B1 to R5C10C.F1 SLICE_117
ROUTE 1 0.958 R5C10C.F1 to R6C11A.D1 N_28_i_sn
CTOF_DEL --- 0.495 R6C11A.D1 to R6C11A.F1 SLICE_88
ROUTE 1 1.599 R6C11A.F1 to IOL_R6D.OPOS N_28_i (to RCLK_c)
--------
8.434 (28.8% logic, 71.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.070 62.PADDI to R6C7A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 47 3.243 62.PADDI to IOL_R6D.CLK RCLK_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Report: 102.312MHz is the maximum frequency for this preference.
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.556 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Aug 19 21:55:11 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o LCMXO2_640HC_impl1.twr -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 0.132 R4C8D.Q0 to R4C8D.A0 ADSubmitted
CTOF_DEL --- 0.101 R4C8D.A0 to R4C8D.F0 SLICE_10
ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 ADSubmitted_r (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R4C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R4C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMShift_fast (from PHI2_c -)
Destination: FF Data in CmdUFMShift_fast (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_21 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C6B.CLK to R5C6B.Q0 SLICE_21 (from PHI2_c)
ROUTE 2 0.132 R5C6B.Q0 to R5C6B.A0 CmdUFMShift_fast
CTOF_DEL --- 0.101 R5C6B.A0 to R5C6B.F0 SLICE_21
ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 CmdUFMShift_3_fast (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C6B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C6B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMWrite (from PHI2_c -)
Destination: FF Data in CmdUFMWrite (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_22 to SLICE_22 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_22 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q0 SLICE_22 (from PHI2_c)
ROUTE 2 0.132 R5C6A.Q0 to R5C6A.A0 CmdUFMWrite
CTOF_DEL --- 0.101 R5C6A.A0 to R5C6A.F0 SLICE_22
ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 CmdUFMWrite_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C6A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C6A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG (from PHI2_c -)
Destination: FF Data in XOR8MEG (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_46 to SLICE_46 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_46 to SLICE_46:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C7C.CLK to R5C7C.Q0 SLICE_46 (from PHI2_c)
ROUTE 2 0.132 R5C7C.Q0 to R5C7C.A0 XOR8MEG
CTOF_DEL --- 0.101 R5C7C.A0 to R5C7C.F0 SLICE_46
ROUTE 1 0.000 R5C7C.F0 to R5C7C.DI0 XOR8MEG_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_46:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C7C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_46:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C7C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.380ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMShift (from PHI2_c -)
Destination: FF Data in CmdUFMShift (to PHI2_c -)
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
Constraint Details:
0.367ns physical path delay SLICE_20 to SLICE_20 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C6C.CLK to R5C6C.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.133 R5C6C.Q0 to R5C6C.A0 CmdUFMShift
CTOF_DEL --- 0.101 R5C6C.A0 to R5C6C.F0 SLICE_20
ROUTE 1 0.000 R5C6C.F0 to R5C6C.DI0 CmdUFMShift_3 (to PHI2_c)
--------
0.367 (63.8% logic, 36.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C6C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C6C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.422ns (68.5% logic, 31.5% route), 2 logic levels.
Constraint Details:
0.422ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.435ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_17 (from PHI2_c)
ROUTE 4 0.133 R5C8A.Q0 to R5C8A.A0 CmdEnable
CTOOFX_DEL --- 0.156 R5C8A.A0 to R5C8A.OFX0 SLICE_17
ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c)
--------
0.422 (68.5% logic, 31.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels.
Constraint Details:
0.458ns physical path delay SLICE_11 to SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.471ns
Physical Path Details:
Data path SLICE_11 to SLICE_11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c)
ROUTE 2 0.224 R5C8D.Q0 to R5C8D.B0 C1Submitted
CTOF_DEL --- 0.101 R5C8D.B0 to R5C8D.F0 SLICE_11
ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_s (to PHI2_c)
--------
0.458 (51.1% logic, 48.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.527ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.514ns (56.2% logic, 43.8% route), 2 logic levels.
Constraint Details:
0.514ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.527ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_17 (from PHI2_c)
ROUTE 4 0.225 R5C8A.Q0 to R5C8A.B1 CmdEnable
CTOOFX_DEL --- 0.156 R5C8A.B1 to R5C8A.OFX0 SLICE_17
ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c)
--------
0.514 (56.2% logic, 43.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.550ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.537ns (53.8% logic, 46.2% route), 2 logic levels.
Constraint Details:
0.537ns physical path delay SLICE_10 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.550ns
Physical Path Details:
Data path SLICE_10 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 0.248 R4C8D.Q0 to R5C8A.D1 ADSubmitted
CTOOFX_DEL --- 0.156 R5C8A.D1 to R5C8A.OFX0 SLICE_17
ROUTE 1 0.000 R5C8A.OFX0 to R5C8A.DI0 CmdEnable_s (to PHI2_c)
--------
0.537 (53.8% logic, 46.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R4C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.550ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in XOR8MEG (to PHI2_c -)
Delay: 0.522ns (44.8% logic, 55.2% route), 2 logic levels.
Constraint Details:
0.522ns physical path delay SLICE_17 to SLICE_46 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 0.550ns
Physical Path Details:
Data path SLICE_17 to SLICE_46:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_17 (from PHI2_c)
ROUTE 4 0.142 R5C8A.Q0 to R5C7A.C1 CmdEnable
CTOF_DEL --- 0.101 R5C7A.C1 to R5C7A.F1 SLICE_24
ROUTE 8 0.146 R5C7A.F1 to R5C7C.CE XOR8MEG18 (to PHI2_c)
--------
0.522 (44.8% logic, 55.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_46:
Name Fanout Delay (ns) Site Resource
ROUTE 22 1.240 8.PADDI to R5C7C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 0.152 R5C9A.Q0 to R5C9A.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R5C9A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R5C9A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr2 (from RCLK_c +)
Destination: FF Data in CASr3 (to RCLK_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_12 to SLICE_106 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_12 to SLICE_106:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q1 SLICE_12 (from RCLK_c)
ROUTE 4 0.154 R5C9A.Q1 to R5C9D.M0 CASr2 (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R5C9A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_106:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R5C9D.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr (from RCLK_c +)
Destination: FF Data in RASr2 (to RCLK_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_34 to SLICE_34 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_34 to SLICE_34:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C7A.CLK to R6C7A.Q0 SLICE_34 (from RCLK_c)
ROUTE 2 0.154 R6C7A.Q0 to R6C7A.M1 RASr (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C7A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C7A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.313ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[6] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels.
Constraint Details:
0.307ns physical path delay SLICE_52 to ufmefb/EFBInst_0 meets
-0.060ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.006ns) by 0.313ns
Physical Path Details:
Data path SLICE_52 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q0 SLICE_52 (from RCLK_c)
ROUTE 2 0.174 R2C2C.Q0 to EFB.WBADRI6 wb_adr[6] (to RCLK_c)
--------
0.307 (43.3% logic, 56.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R2C2C.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c
--------
1.113 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.318ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[7] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.304ns (43.8% logic, 56.3% route), 1 logic levels.
Constraint Details:
0.304ns physical path delay SLICE_52 to ufmefb/EFBInst_0 meets
-0.068ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.014ns) by 0.318ns
Physical Path Details:
Data path SLICE_52 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q1 SLICE_52 (from RCLK_c)
ROUTE 1 0.171 R2C2C.Q1 to EFB.WBADRI7 wb_adr[7] (to RCLK_c)
--------
0.304 (43.8% logic, 56.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R2C2C.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c
--------
1.113 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.334ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[2] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels.
Constraint Details:
0.307ns physical path delay SLICE_50 to ufmefb/EFBInst_0 meets
-0.081ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.027ns) by 0.334ns
Physical Path Details:
Data path SLICE_50 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2B.CLK to R2C2B.Q0 SLICE_50 (from RCLK_c)
ROUTE 2 0.174 R2C2B.Q0 to EFB.WBADRI2 wb_adr[2] (to RCLK_c)
--------
0.307 (43.3% logic, 56.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_50:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R2C2B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c
--------
1.113 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.355ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_adr[1] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels.
Constraint Details:
0.307ns physical path delay SLICE_49 to ufmefb/EFBInst_0 meets
-0.102ns WBADRI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.048ns) by 0.355ns
Physical Path Details:
Data path SLICE_49 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C2A.CLK to R2C2A.Q1 SLICE_49 (from RCLK_c)
ROUTE 2 0.174 R2C2A.Q1 to EFB.WBADRI1 wb_adr[1] (to RCLK_c)
--------
0.307 (43.3% logic, 56.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_49:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R2C2A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.113 62.PADDI to EFB.WBCLKI RCLK_c
--------
1.113 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from RCLK_c +)
Destination: FF Data in FS[0] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C3A.CLK to R6C3A.Q1 SLICE_0 (from RCLK_c)
ROUTE 3 0.132 R6C3A.Q1 to R6C3A.A1 FS[0]
CTOF_DEL --- 0.101 R6C3A.A1 to R6C3A.F1 SLICE_0
ROUTE 1 0.000 R6C3A.F1 to R6C3A.DI1 FS_s[0] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C3A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C3A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in FS[17] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c)
ROUTE 5 0.132 R6C5B.Q0 to R6C5B.A0 FS[17]
CTOF_DEL --- 0.101 R6C5B.A0 to R6C5B.F0 SLICE_1
ROUTE 1 0.000 R6C5B.F0 to R6C5B.DI0 FS_s[17] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C5B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C5B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[16] (from RCLK_c +)
Destination: FF Data in FS[16] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c)
ROUTE 5 0.132 R6C5A.Q1 to R6C5A.A1 FS[16]
CTOF_DEL --- 0.101 R6C5A.A1 to R6C5A.F1 SLICE_2
ROUTE 1 0.000 R6C5A.F1 to R6C5A.DI1 FS_s[16] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C5A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 47 1.059 62.PADDI to R6C5A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 705 connections (72.09% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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