mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-28 21:49:21 +00:00
552 lines
15 KiB
Plaintext
552 lines
15 KiB
Plaintext
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comp 0: SLICE_0 (FSLICE)
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comp 1: SLICE_1 (FSLICE)
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comp 2: SLICE_2 (FSLICE)
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comp 3: SLICE_3 (FSLICE)
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comp 4: SLICE_4 (FSLICE)
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comp 5: SLICE_5 (FSLICE)
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comp 6: SLICE_6 (FSLICE)
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comp 7: SLICE_7 (FSLICE)
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comp 8: SLICE_8 (FSLICE)
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comp 9: SLICE_9 (FSLICE)
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ADSubmitted_r = (~CmdEnable16*((~C1WR_0_a2*ADSubmitted)+CmdEnable17))
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ADSubmitted.D = ADSubmitted_r
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ADSubmitted.CLK = ~PHI2_c
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ADSubmitted.SP = VCC
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ADSubmitted.LSR = GND
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CmdEnable17 = (N_147*(MAin_c[0]*(CmdEnable17_0_a2_4*CmdEnable17_0_a2_3)))
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comp 10: SLICE_14 (FSLICE)
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C1Submitted_RNO = (~MAin_c[1]*(CmdEnable16+C1Submitted)+MAin_c[1]*(~N_147*(CmdEnable16+C1Submitted)+N_147*CmdEnable16))
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C1Submitted.D = C1Submitted_RNO
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C1Submitted.CLK = ~PHI2_c
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C1Submitted.SP = VCC
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C1Submitted.LSR = GND
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CmdEnable16 = (N_147*(CmdEnable16_0_a2_5*CmdEnable16_0_a2_4))
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comp 11: SLICE_19 (FSLICE)
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N_177_i = (~CO0+S[1])
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CO0.D = N_177_i
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CO0.CLK = RCLK_c
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CO0.SP = VCC
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CO0.LSR = ~RASr2
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Ready_0_sqmuxa_0_a3_2 = (S[1]*(~RASr2*(IS[3]*CO0)))
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comp 12: SLICE_20 (FSLICE)
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CmdEnable_s = ((CmdEnable+ADSubmitted)*CmdEnable16)+(((C1Submitted*un1_CMDWR*CmdEnable17)+(CmdEnable*CmdEnable17)+(~un1_CMDWR*CmdEnable))*~CmdEnable16)
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CmdEnable.D = CmdEnable_s
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CmdEnable.CLK = ~PHI2_c
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CmdEnable.SP = VCC
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CmdEnable.LSR = GND
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comp 13: SLICE_21 (FSLICE)
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N_21_i = (~N_152*(~N_133*~N_132)+N_152*(~N_133*(~N_132*LEDEN)))
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CmdLEDEN.D = N_21_i
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CmdLEDEN.CLK = ~PHI2_c
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CmdLEDEN.SP = XOR8MEG18
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CmdLEDEN.LSR = GND
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N_152 = (~N_128*(Din_c[5]*~Din_c[3]))
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comp 14: SLICE_22 (FSLICE)
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N_460_0 = (CmdSubmitted_1_sqmuxa+CmdSubmitted)
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CmdSubmitted.D = N_460_0
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CmdSubmitted.CLK = ~PHI2_c
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CmdSubmitted.SP = VCC
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CmdSubmitted.LSR = GND
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N_136 = (PHI2r3*(~PHI2r2*(InitReady*CmdSubmitted)))
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comp 15: SLICE_26 (FSLICE)
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N_19_i = (~n8MEGEN*(~N_152*~Cmdn8MEGEN_4_u_i_0)+n8MEGEN*~Cmdn8MEGEN_4_u_i_0)
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Cmdn8MEGEN.D = N_19_i
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Cmdn8MEGEN.CLK = ~PHI2_c
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Cmdn8MEGEN.SP = XOR8MEG18
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Cmdn8MEGEN.LSR = GND
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Cmdn8MEGEN_4_u_i_0 = (~N_128*(~N_43*(~Cmdn8MEGEN+CmdEnable16_4)+N_43*CmdEnable16_4)+N_128*~Cmdn8MEGEN)
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comp 16: SLICE_29 (FSLICE)
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N_64_i_i = (~N_155*(Ready@~IS[0])+N_155*IS[0])
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IS[0].D = N_64_i_i
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IS[0].CLK = RCLK_c
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IS[0].SP = VCC
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IS[0].LSR = GND
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N_24 = ((~N_160*(~N_155*IS[0])+N_160*~N_155)+nRRAS_5_u_i_0)
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comp 17: SLICE_30 (FSLICE)
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N_56_i = (IS[1]@IS[0])
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IS[1].D = N_56_i
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IS[1].CLK = RCLK_c
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IS[1].SP = N_159_i
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IS[1].LSR = GND
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N_60_i_i = (IS[2]@(IS[1]*IS[0]))
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IS[2].D = N_60_i_i
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IS[2].CLK = RCLK_c
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IS[2].SP = N_159_i
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IS[2].LSR = GND
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comp 18: SLICE_31 (FSLICE)
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N_61_i_i = (~IS[0]*IS[3]+IS[0]*(~IS[1]*IS[3]+IS[1]*(IS[2]@IS[3])))
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IS[3].D = N_61_i_i
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IS[3].CLK = RCLK_c
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IS[3].SP = N_159_i
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IS[3].LSR = GND
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RA10s_i = ((~IS[3]+(IS[1]+IS[2]))+N_159)
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comp 19: SLICE_32 (FSLICE)
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N_461_0 = (InitReady3+InitReady)
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InitReady.D = N_461_0
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InitReady.CLK = RCLK_c
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InitReady.SP = VCC
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InitReady.LSR = GND
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UFMSDI_ens2_i_a0 = (~UFMSDI_ens2_i_a2_4_2*~InitReady+UFMSDI_ens2_i_a2_4_2*(~N_126*~InitReady+N_126*(N_51*~InitReady)))
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comp 20: SLICE_33 (FSLICE)
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N_70 = (~UFMSDO_c*(~InitReady+CmdLEDEN)+UFMSDO_c*(InitReady*CmdLEDEN))
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LEDEN.D = N_70
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LEDEN.CLK = RCLK_c
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LEDEN.SP = N_33
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LEDEN.LSR = GND
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LED_c = ((~LEDEN+CBR)+nCRAS_c)
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comp 21: SLICE_39 (FSLICE)
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RA11_2 = (~n8MEGEN*(XOR8MEG@Din_c[6])+n8MEGEN*XOR8MEG)
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RA_c[11].D = RA11_2
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RA_c[11].CLK = PHI2_c
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RA_c[11].SP = VCC
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RA_c[11].LSR = ~Ready_fast
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N_171 = (~un1_Din_4*XOR8MEG)
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comp 22: SLICE_41 (FSLICE)
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RCKEEN_8 = (~Ready*RCKEEN_8_u_0_0+Ready*(~RCKEEN_8_u_1*RCKEEN_8_u_0_0+RCKEEN_8_u_1*(~CBR+RCKEEN_8_u_0_0)))
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RCKEEN.D = RCKEEN_8
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RCKEEN.CLK = RCLK_c
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RCKEEN.SP = VCC
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RCKEEN.LSR = GND
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RCKEEN_8_u_1 = (~S[1]*(~FWEr_fast+CO0)+S[1]*(FWEr_fast*(~CO0+~CASr2)))
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PHI2r2.D = PHI2r
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PHI2r2.CLK = RCLK_c
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PHI2r2.SP = VCC
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PHI2r2.LSR = GND
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comp 23: SLICE_42 (FSLICE)
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RCKE_2 = (~RCKEEN*(RASr3*~RASr2)+RCKEEN*((RASr+RASr2)+RASr3))
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RCKE_c.D = RCKE_2
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RCKE_c.CLK = RCLK_c
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RCKE_c.SP = VCC
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RCKE_c.LSR = GND
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m18_0_a3_3 = (RASr2*(~IS[2]*(~IS[1]*IS[0])))
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PHI2r.D = PHI2_c
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PHI2r.CLK = RCLK_c
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PHI2r.SP = VCC
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PHI2r.LSR = GND
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comp 24: SLICE_43 (FSLICE)
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N_462_0 = (~InitReady*Ready+InitReady*(~N_165*(Ready+Ready_0_sqmuxa_0_a3_2)+N_165*Ready))
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Ready.D = N_462_0
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Ready.CLK = RCLK_c
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Ready.SP = VCC
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Ready.LSR = GND
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RCKEEN_8_u_0_0 = (~S_0_i_o2[1]*(~InitReady*(~RASr2*Ready)+InitReady*(~RASr2+~Ready))+S_0_i_o2[1]*(InitReady*~Ready))
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PHI2r3.D = PHI2r2
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PHI2r3.CLK = RCLK_c
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PHI2r3.SP = VCC
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PHI2r3.LSR = GND
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comp 25: SLICE_44 (FSLICE)
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N_463_0 = (Ready_0_sqmuxa+Ready_fast)
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Ready_fast.D = N_463_0
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Ready_fast.CLK = RCLK_c
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Ready_fast.SP = VCC
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Ready_fast.LSR = GND
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Ready_0_sqmuxa = (Ready_0_sqmuxa_0_a3_2*(~Ready*(~N_165*InitReady)))
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RASr.D = ~nCRAS_c
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RASr.CLK = RCLK_c
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RASr.SP = VCC
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RASr.LSR = GND
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comp 26: SLICE_50 (FSLICE)
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S_0_i_o2[1] = (CO0+S[1])
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S[1].D = S_0_i_o2[1]
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S[1].CLK = RCLK_c
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S[1].SP = VCC
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S[1].LSR = ~RASr2
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nRRAS_0_sqmuxa = (~CO0*(~S[1]*Ready))
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comp 27: SLICE_51 (FSLICE)
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UFMCLK_RNO = (~UFMCLK_r_i_m4_xx_mm_1*(~UFMCLK_c*(~nUFMCS15*N_139_i)+UFMCLK_c*~nUFMCS15)+UFMCLK_r_i_m4_xx_mm_1*(UFMCLK_c*(~nUFMCS15*~N_139_i)))
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UFMCLK_c.D = UFMCLK_RNO
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UFMCLK_c.CLK = RCLK_c
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UFMCLK_c.SP = VCC
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UFMCLK_c.LSR = GND
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UFMCLK_r_i_m4_xx_mm_1 = (~N_129*((~CmdUFMCLK+~InitReady)+UFMCLK_r_i_a2_2_2)+N_129*((~CmdUFMCLK*InitReady)+UFMCLK_r_i_a2_2_2))
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RASr2.D = RASr
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RASr2.CLK = RCLK_c
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RASr2.SP = VCC
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RASr2.LSR = GND
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comp 28: SLICE_52 (FSLICE)
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UFMSDI_RNO = (~UFMSDI_r_xx_mm_1*(UFMSDI_c*(~nUFMCS15*~N_139_i))+UFMSDI_r_xx_mm_1*(~UFMSDI_c*(~nUFMCS15*N_139_i)+UFMSDI_c*~nUFMCS15))
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UFMSDI_c.D = UFMSDI_RNO
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UFMSDI_c.CLK = RCLK_c
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UFMSDI_c.SP = VCC
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UFMSDI_c.LSR = GND
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N_139_i = (~PHI2r3*~InitReady+PHI2r3*(~PHI2r2*(~InitReady+CmdSubmitted)+PHI2r2*~InitReady))
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RASr3.D = RASr2
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RASr3.CLK = RCLK_c
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RASr3.SP = VCC
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RASr3.LSR = GND
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comp 29: SLICE_55 (FSLICE)
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RA_c[4] = (~nRowColSel*RowA[4]+nRowColSel*MAin_c[4])
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WRD[4].D = Din_c[4]
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WRD[4].CLK = ~nCCAS_c
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WRD[4].SP = VCC
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WRD[4].LSR = GND
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WRD[5].D = Din_c[5]
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WRD[5].CLK = ~nCCAS_c
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WRD[5].SP = VCC
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WRD[5].LSR = GND
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comp 30: SLICE_56 (FSLICE)
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N_126 = (~FS[9]*FS[7]+FS[9]*(~FS[7]*FS[5]))
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WRD[6].D = Din_c[6]
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WRD[6].CLK = ~nCCAS_c
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WRD[6].SP = VCC
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WRD[6].LSR = GND
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C1WR_0_a2_0_11 = (Bank[7]*(Bank[6]*(Bank[5]*~Bank[2])))
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WRD[7].D = Din_c[7]
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WRD[7].CLK = ~nCCAS_c
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WRD[7].SP = VCC
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WRD[7].LSR = GND
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comp 31: SLICE_57 (FSLICE)
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XOR8MEG_3 = (~XOR8MEG_3_u_0_a3_2*N_171+XOR8MEG_3_u_0_a3_2*((~LEDEN+~Din_c[1])+N_171))
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XOR8MEG.D = XOR8MEG_3
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XOR8MEG.CLK = ~PHI2_c
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XOR8MEG.SP = XOR8MEG18
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XOR8MEG.LSR = GND
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XOR8MEG_3_u_0_a3_2 = (un1_Din_4*(~Din_c[3]*(Din_c[2]*Din_c[0])))
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comp 32: SLICE_58 (FSLICE)
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N_69 = (~UFMSDO_c*(~InitReady+Cmdn8MEGEN)+UFMSDO_c*(InitReady*Cmdn8MEGEN))
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n8MEGEN.D = N_69
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n8MEGEN.CLK = RCLK_c
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n8MEGEN.SP = N_31
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n8MEGEN.LSR = GND
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N_151 = (~N_51*(~InitReady*~FS[8]))
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comp 33: SLICE_59 (FSLICE)
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N_37_i = (~g0_1*(~S[1]*(~nRCAS_0_sqmuxa_1*N_41)+S[1]*~nRCAS_0_sqmuxa_1)+g0_1*(~nRCAS_0_sqmuxa_1*N_41))
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nRCAS_c.D = N_37_i
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nRCAS_c.CLK = RCLK_c
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nRCAS_c.SP = VCC
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nRCAS_c.LSR = GND
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N_41 = (~S[1]*((~N_160+N_155)+Ready)+S[1]*(~Ready*(~N_160+N_155)))
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comp 34: SLICE_60 (FSLICE)
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N_28_i = (~RCKEEN_8_u_0_a2_1_out*~N_24+RCKEEN_8_u_0_a2_1_out*(~N_28_i_1*(~N_24*CBR)+N_28_i_1*~N_24))
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nRCS_c.D = N_28_i
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nRCS_c.CLK = RCLK_c
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nRCS_c.SP = VCC
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nRCS_c.LSR = GND
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N_28_i_1 = (~CASr2*(FWEr_fast+CO0)+CASr2*(~CASr3*(CO0@FWEr_fast)+CASr3*(FWEr_fast+CO0)))
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comp 35: SLICE_61 (FSLICE)
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N_24_i = (~IS[0]*(~N_155*(~N_160*~nRRAS_5_u_i_0)+N_155*~nRRAS_5_u_i_0)+IS[0]*(N_155*~nRRAS_5_u_i_0))
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nRRAS_c.D = N_24_i
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nRRAS_c.CLK = RCLK_c
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nRRAS_c.SP = VCC
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nRRAS_c.LSR = GND
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nRRAS_5_u_i_0 = (Ready*(~RCKE_c*(RASr2*~S_0_i_o2[1])+RCKE_c*~S_0_i_o2[1]))
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comp 36: SLICE_62 (FSLICE)
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N_39_i = (~m18_0_a2_1*((~G_17_1+~FWEr)+nRCAS_0_sqmuxa_1)+m18_0_a2_1*((G_17_1*~FWEr)+nRCAS_0_sqmuxa_1))
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nRWE_c.D = N_39_i
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nRWE_c.CLK = RCLK_c
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nRWE_c.SP = VCC
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nRWE_c.LSR = GND
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nRCAS_0_sqmuxa_1 = (Ready*(RASr2*(~S_0_i_o2[1]*CBR_fast)))
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comp 37: SLICE_63 (FSLICE)
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nRowColSel_0_0 = (~S[1]*(~Ready*N_179+Ready*(CO0+N_179))+S[1]*(~Ready*N_179+Ready*(~CO0+N_179)))
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nRowColSel.D = nRowColSel_0_0
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nRowColSel.CLK = RCLK_c
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nRowColSel.SP = VCC
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nRowColSel.LSR = nRRAS_0_sqmuxa
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N_179 = (Ready*(FWEr*(~CBR*~CASr3)))
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comp 38: SLICE_64 (FSLICE)
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nUFMCS_s_0_N_5_i = (~nUFMCS_s_0_N_5_i_N_2L1*((N_139_i+nUFMCS15)+nUFMCS_c)+nUFMCS_s_0_N_5_i_N_2L1*(~nUFMCS_c*nUFMCS15+nUFMCS_c*(~N_139_i+nUFMCS15)))
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nUFMCS_c.D = nUFMCS_s_0_N_5_i
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nUFMCS_c.CLK = RCLK_c
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nUFMCS_c.SP = VCC
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nUFMCS_c.LSR = GND
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nUFMCS15 = (~N_51*(~InitReady*(~FS[11]*~FS[10])))
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comp 39: nRWE_RNO_1/SLICE_65 (FSLICE)
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m18_0_a2_1 = ((~RASr2*RCKE_c*~CO0*~S[1])*Ready)+((InitReady*m18_0_a3_3*~CO0*~S[1])*~Ready)
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comp 40: SLICE_66 (FSLICE)
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UFMCLK_r_i_a2_2_2 = (N_95_5*(N_95_3*(~InitReady*FS[16])))
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RowA[0].D = MAin_c[0]
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RowA[0].CLK = ~nCRAS_c
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RowA[0].SP = VCC
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RowA[0].LSR = ~Ready_fast
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nUFMCS_s_0_N_5_i_N_2L1 = (~UFMCLK_r_i_a2_2_2*(~InitReady+CmdUFMCS))
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RowA[1].D = MAin_c[1]
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RowA[1].CLK = ~nCRAS_c
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RowA[1].SP = VCC
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RowA[1].LSR = ~Ready_fast
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comp 41: SLICE_67 (FSLICE)
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XOR8MEG18 = (N_147*(~MAin_c[1]*(MAin_c[0]*CmdEnable)))
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RowA[4].D = MAin_c[4]
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RowA[4].CLK = ~nCRAS_c
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RowA[4].SP = VCC
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RowA[4].LSR = ~Ready_fast
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CmdUFMCLK_1_sqmuxa = (~Din_c[3]*(Din_c[5]*(~N_128*XOR8MEG18)))
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RowA[5].D = MAin_c[5]
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RowA[5].CLK = ~nCRAS_c
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RowA[5].SP = VCC
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RowA[5].LSR = ~Ready_fast
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comp 42: SLICE_68 (FSLICE)
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N_31 = (~un1_FS_14_i_a2_0_1*N_136+un1_FS_14_i_a2_0_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
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un1_FS_14_i_a2_0_1 = (~FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
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comp 43: SLICE_69 (FSLICE)
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N_33 = (~un1_FS_13_i_a2_1*N_136+un1_FS_13_i_a2_1*(~N_137_8*N_136+N_137_8*(N_136+N_137_6)))
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un1_FS_13_i_a2_1 = (FS[5]*(~FS[3]*(~FS[2]*~FS[0])))
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comp 44: SLICE_70 (FSLICE)
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C1WR_0_a2 = (N_147*MAin_c[1])
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Bank[0].D = Din_c[0]
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Bank[0].CLK = PHI2_c
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Bank[0].SP = VCC
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Bank[0].LSR = GND
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N_147 = (C1WR_0_a2_0_11*(C1WR_0_a2_0_10*(Bank[1]*Bank[0])))
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Bank[1].D = Din_c[1]
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Bank[1].CLK = PHI2_c
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Bank[1].SP = VCC
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Bank[1].LSR = GND
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comp 45: SLICE_71 (FSLICE)
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C1WR_0_a2_0_10 = (C1WR_0_a2_0_4*(C1WR_0_a2_0_3*(Bank[4]*Bank[3])))
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Bank[2].D = Din_c[2]
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Bank[2].CLK = PHI2_c
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Bank[2].SP = VCC
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Bank[2].LSR = GND
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C1WR_0_a2_0_4 = (MAin_c[7]*(MAin_c[6]*(MAin_c[5]*MAin_c[4])))
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Bank[3].D = Din_c[3]
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Bank[3].CLK = PHI2_c
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Bank[3].SP = VCC
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Bank[3].LSR = GND
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comp 46: SLICE_72 (FSLICE)
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N_129 = (~N_51*(FS[11]*FS[4])+N_51*FS[1])
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RowA[2].D = MAin_c[2]
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RowA[2].CLK = ~nCRAS_c
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RowA[2].SP = VCC
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RowA[2].LSR = ~Ready_fast
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N_51 = ((FS[12]+FS[16])+UFMSDI_ens2_i_o2_0_3)
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RowA[3].D = MAin_c[3]
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RowA[3].CLK = ~nCRAS_c
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RowA[3].SP = VCC
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RowA[3].LSR = ~Ready_fast
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comp 47: SLICE_73 (FSLICE)
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N_159 = (N_155+Ready)
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CmdUFMCLK.D = Din_c[1]
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CmdUFMCLK.CLK = ~PHI2_c
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CmdUFMCLK.SP = CmdUFMCLK_1_sqmuxa
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CmdUFMCLK.LSR = GND
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N_155 = (((~InitReady+~RASr2)+S[1])+CO0)
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CmdUFMCS.D = Din_c[2]
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CmdUFMCS.CLK = ~PHI2_c
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CmdUFMCS.SP = CmdUFMCLK_1_sqmuxa
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CmdUFMCS.LSR = GND
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comp 48: SLICE_74 (FSLICE)
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InitReady3 = (N_95_5*(N_95_3*(FS[16]*FS[10])))
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CmdUFMSDI.D = Din_c[0]
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CmdUFMSDI.CLK = ~PHI2_c
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CmdUFMSDI.SP = CmdUFMCLK_1_sqmuxa
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CmdUFMSDI.LSR = GND
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N_95_3 = (FS[14]*FS[11])
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comp 49: SLICE_75 (FSLICE)
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N_133 = (~N_128*(~Din_c[5]*~Din_c[1]))
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CASr.D = ~nCCAS_c
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CASr.CLK = RCLK_c
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CASr.SP = VCC
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CASr.LSR = GND
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N_128 = ((~Din_c[4]+Din_c[6])+Din_c[7])
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CASr2.D = CASr
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CASr2.CLK = RCLK_c
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CASr2.SP = VCC
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CASr2.LSR = GND
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comp 50: SLICE_76 (FSLICE)
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CmdEnable16_0_a2_4 = (~MAin_c[0]*(~Din_c[3]*(~Din_c[1]*CmdEnable16_4)))
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Bank[4].D = Din_c[4]
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Bank[4].CLK = PHI2_c
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Bank[4].SP = VCC
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Bank[4].LSR = GND
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CmdEnable16_4 = (~Din_c[5]*Din_c[0])
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Bank[5].D = Din_c[5]
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Bank[5].CLK = PHI2_c
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Bank[5].SP = VCC
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Bank[5].LSR = GND
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comp 51: SLICE_77 (FSLICE)
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CmdEnable16_0_a2_5 = (MAin_c[1]*(Din_c[6]*(~Din_c[2]*CmdEnable16_1)))
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Bank[6].D = Din_c[6]
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Bank[6].CLK = PHI2_c
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Bank[6].SP = VCC
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Bank[6].LSR = GND
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CmdEnable16_1 = (Din_c[7]*~Din_c[4])
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Bank[7].D = Din_c[7]
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Bank[7].CLK = PHI2_c
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Bank[7].SP = VCC
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Bank[7].LSR = GND
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comp 52: SLICE_78 (FSLICE)
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CmdEnable17_0_a2_4 = (~N_43*(MAin_c[1]*(~Din_c[6]*Din_c[2])))
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CBR.D = ~nCCAS_c
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CBR.CLK = ~nCRAS_c
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CBR.SP = VCC
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CBR.LSR = GND
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N_43 = (~Din_c[5]+~Din_c[3])
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CBR_fast.D = ~nCCAS_c
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CBR_fast.CLK = ~nCRAS_c
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CBR_fast.SP = VCC
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CBR_fast.LSR = GND
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|
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comp 53: SLICE_79 (FSLICE)
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G_17_1 = (m6_0_a2_2*(S[1]*(CO0*~CBR)))
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WRD[0].D = Din_c[0]
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WRD[0].CLK = ~nCCAS_c
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WRD[0].SP = VCC
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WRD[0].LSR = GND
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m6_0_a2_2 = (Ready*(~CASr3*CASr2))
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WRD[1].D = Din_c[1]
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|
WRD[1].CLK = ~nCCAS_c
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WRD[1].SP = VCC
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WRD[1].LSR = GND
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|
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comp 54: SLICE_80 (FSLICE)
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g0_1 = (~g4_0_0_0*(~FWEr*(~CO0*~CBR_fast))+g4_0_0_0*(~FWEr*(~CO0*~CBR_fast)+FWEr*(CO0*~CBR_fast)))
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RowA[8].D = MAin_c[8]
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RowA[8].CLK = ~nCRAS_c
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|
RowA[8].SP = VCC
|
|
RowA[8].LSR = ~Ready_fast
|
|
g4_0_0_0 = (~CASr3*CASr2)
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RowA[9].D = MAin_c[9]
|
|
RowA[9].CLK = ~nCRAS_c
|
|
RowA[9].SP = VCC
|
|
RowA[9].LSR = ~Ready_fast
|
|
|
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comp 55: SLICE_81 (FSLICE)
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N_95_5 = (FS[17]*(FS[15]*(FS[13]*FS[12])))
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|
FWEr.D = ~nFWE_c
|
|
FWEr.CLK = ~nCRAS_c
|
|
FWEr.SP = VCC
|
|
FWEr.LSR = GND
|
|
UFMSDI_ens2_i_o2_0_3 = (((FS[13]+FS[14])+FS[15])+FS[17])
|
|
FWEr_fast.D = ~nFWE_c
|
|
FWEr_fast.CLK = ~nCRAS_c
|
|
FWEr_fast.SP = VCC
|
|
FWEr_fast.LSR = GND
|
|
|
|
comp 56: SLICE_82 (FSLICE)
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CmdSubmitted_1_sqmuxa = (~Din_c[3]*(~N_128*XOR8MEG18)+Din_c[3]*(~Din_c[5]*(~N_128*XOR8MEG18)))
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|
CASr3.D = CASr2
|
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CASr3.CLK = RCLK_c
|
|
CASr3.SP = VCC
|
|
CASr3.LSR = GND
|
|
N_132 = (~Din_c[3]*(~CmdLEDEN*N_128)+Din_c[3]*(~Din_c[5]*(~CmdLEDEN*N_128)+Din_c[5]*~CmdLEDEN))
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|
|
|
comp 57: SLICE_83 (FSLICE)
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N_165 = (~IS[2]+(~IS[1]+~IS[0]))
|
|
RBA_c[0].D = CROW_c[0]
|
|
RBA_c[0].CLK = ~nCRAS_c
|
|
RBA_c[0].SP = VCC
|
|
RBA_c[0].LSR = ~Ready_fast
|
|
N_160 = ((IS[1]+IS[2])+IS[3])
|
|
RBA_c[1].D = CROW_c[1]
|
|
RBA_c[1].CLK = ~nCRAS_c
|
|
RBA_c[1].SP = VCC
|
|
RBA_c[1].LSR = ~Ready_fast
|
|
|
|
comp 58: SLICE_84 (FSLICE)
|
|
N_137_6 = (FS[10]*(~FS[7]*(~FS[6]*~FS[1])))
|
|
UFMSDI_ens2_i_a2_4_2 = (FS[11]*(~FS[10]*(~FS[8]*FS[6])))
|
|
|
|
comp 59: SLICE_85 (FSLICE)
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un1_Din_4 = (~Din_c[7]*(~Din_c[6]*(~Din_c[5]*~Din_c[4])))
|
|
WRD[2].D = Din_c[2]
|
|
WRD[2].CLK = ~nCCAS_c
|
|
WRD[2].SP = VCC
|
|
WRD[2].LSR = GND
|
|
CmdEnable17_0_a2_3 = (~Din_c[4]*(Din_c[7]*(Din_c[0]*~Din_c[1])))
|
|
WRD[3].D = Din_c[3]
|
|
WRD[3].CLK = ~nCCAS_c
|
|
WRD[3].SP = VCC
|
|
WRD[3].LSR = GND
|
|
|
|
comp 60: SLICE_86 (FSLICE)
|
|
RA_c[9] = (~nRowColSel*RowA[9]+nRowColSel*MAin_c[9])
|
|
RDQML_c = (~nRowColSel+~MAin_c[9])
|
|
|
|
comp 61: SLICE_87 (FSLICE)
|
|
N_137_8 = (N_151*(FS[11]*(~FS[9]*FS[4])))
|
|
UFMSDI_r_xx_mm_1 = (~N_151*(~UFMSDI_ens2_i_a0*CmdUFMSDI)+N_151*~UFMSDI_ens2_i_a0)
|
|
|
|
comp 62: SLICE_88 (FSLICE)
|
|
RD_1_i = (nCCAS_c+nFWE_c)
|
|
RowA[6].D = MAin_c[6]
|
|
RowA[6].CLK = ~nCRAS_c
|
|
RowA[6].SP = VCC
|
|
RowA[6].LSR = ~Ready_fast
|
|
C1WR_0_a2_0_3 = (~nFWE_c*(MAin_c[3]*MAin_c[2]))
|
|
RowA[7].D = MAin_c[7]
|
|
RowA[7].CLK = ~nCRAS_c
|
|
RowA[7].SP = VCC
|
|
RowA[7].LSR = ~Ready_fast
|
|
|
|
comp 63: SLICE_89 (FSLICE)
|
|
RA_c[8] = (~nRowColSel*RowA[8]+nRowColSel*MAin_c[8])
|
|
RDQMH_c = (~nRowColSel+MAin_c[9])
|
|
|
|
comp 64: SLICE_90 (FSLICE)
|
|
RA_c[0] = (~nRowColSel*RowA[0]+nRowColSel*MAin_c[0])
|
|
un1_CMDWR = (~MAin_c[1]*(MAin_c[0]*N_147)+MAin_c[1]*N_147)
|
|
|
|
comp 65: SLICE_91 (FSLICE)
|
|
RA_c[1] = (~nRowColSel*RowA[1]+nRowColSel*MAin_c[1])
|
|
RA_c[7] = (~nRowColSel*RowA[7]+nRowColSel*MAin_c[7])
|
|
|
|
comp 66: SLICE_92 (FSLICE)
|
|
RA_c[2] = (~nRowColSel*RowA[2]+nRowColSel*MAin_c[2])
|
|
RA_c[6] = (~nRowColSel*RowA[6]+nRowColSel*MAin_c[6])
|
|
|
|
comp 67: SLICE_93 (FSLICE)
|
|
RA_c[3] = (~nRowColSel*RowA[3]+nRowColSel*MAin_c[3])
|
|
RA_c[5] = (~nRowColSel*RowA[5]+nRowColSel*MAin_c[5])
|
|
|
|
comp 68: SLICE_94 (FSLICE)
|
|
RCKEEN_8_u_0_a2_1_out = (S[1]*Ready)
|
|
RA_c[10].D = ~IS[0]
|
|
RA_c[10].CLK = RCLK_c
|
|
RA_c[10].SP = VCC
|
|
RA_c[10].LSR = RA10s_i
|
|
N_159_i = (~N_155*~Ready)
|