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Fix schematic label errors and pin assignments on 8755A device to match the schematic

This commit is contained in:
Tom Nisbet 2018-12-20 16:41:26 -05:00
parent 4dbabf7630
commit 98986f2922
3 changed files with 4 additions and 4 deletions
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4
TommyPROM/PromDevice8755A.cpp
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@ -2,9 +2,9 @@
#if defined(PROM_IS_8755A)
#define CE2 A0
#define CE1 A0
#define RD A1
#define CE1 A2
#define CE2 A2
#define AD10 A3
#define AD9 A4
#define AD8 A5

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docs/TommyPROM-8755A-sch.png
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4
hardware/TommyPROM-8755A Nano.sch
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@ -7248,7 +7248,7 @@ to compensate for the voltage loss from D1 and Q2.
<pinref part="IC1" gate="G$1" pin="A8"/>
</segment>
</net>
<net name="CE2" class="0">
<net name="CE1/PRG" class="0">
<segment>
<wire x1="15.24" y1="114.3" x2="-30.48" y2="114.3" width="0.1524" layer="91"/>
<wire x1="-30.48" y1="114.3" x2="-30.48" y2="55.88" width="0.1524" layer="91"/>
@ -7280,7 +7280,7 @@ to compensate for the voltage loss from D1 and Q2.
<pinref part="IC1" gate="G$1" pin="RD"/>
</segment>
</net>
<net name="CE1/PROG" class="0">
<net name="CE2" class="0">
<segment>
<wire x1="15.24" y1="109.22" x2="-25.4" y2="109.22" width="0.1524" layer="91"/>
<wire x1="-25.4" y1="109.22" x2="-25.4" y2="60.96" width="0.1524" layer="91"/>