Fix schematic label errors and pin assignments on 8755A device to match the schematic
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@ -2,9 +2,9 @@
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#if defined(PROM_IS_8755A)
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#if defined(PROM_IS_8755A)
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#define CE2 A0
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#define CE1 A0
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#define RD A1
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#define RD A1
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#define CE1 A2
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#define CE2 A2
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#define AD10 A3
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#define AD10 A3
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#define AD9 A4
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#define AD9 A4
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#define AD8 A5
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#define AD8 A5
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Before Width: | Height: | Size: 54 KiB After Width: | Height: | Size: 52 KiB |
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@ -7248,7 +7248,7 @@ to compensate for the voltage loss from D1 and Q2.
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<pinref part="IC1" gate="G$1" pin="A8"/>
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<pinref part="IC1" gate="G$1" pin="A8"/>
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</segment>
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</segment>
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</net>
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</net>
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<net name="CE2" class="0">
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<net name="CE1/PRG" class="0">
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<segment>
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<segment>
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<wire x1="15.24" y1="114.3" x2="-30.48" y2="114.3" width="0.1524" layer="91"/>
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<wire x1="15.24" y1="114.3" x2="-30.48" y2="114.3" width="0.1524" layer="91"/>
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<wire x1="-30.48" y1="114.3" x2="-30.48" y2="55.88" width="0.1524" layer="91"/>
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<wire x1="-30.48" y1="114.3" x2="-30.48" y2="55.88" width="0.1524" layer="91"/>
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@ -7280,7 +7280,7 @@ to compensate for the voltage loss from D1 and Q2.
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<pinref part="IC1" gate="G$1" pin="RD"/>
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<pinref part="IC1" gate="G$1" pin="RD"/>
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</segment>
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</segment>
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</net>
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</net>
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<net name="CE1/PROG" class="0">
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<net name="CE2" class="0">
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<segment>
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<segment>
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<wire x1="15.24" y1="109.22" x2="-25.4" y2="109.22" width="0.1524" layer="91"/>
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<wire x1="15.24" y1="109.22" x2="-25.4" y2="109.22" width="0.1524" layer="91"/>
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<wire x1="-25.4" y1="109.22" x2="-25.4" y2="60.96" width="0.1524" layer="91"/>
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<wire x1="-25.4" y1="109.22" x2="-25.4" y2="60.96" width="0.1524" layer="91"/>
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