Fixed rendering issues with reademe.
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README.md
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README.md
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@ -27,25 +27,27 @@ Connections from the 26-pin connector on the Apple IIe keyboard to the pins on
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the Teensy 2.0 pins. "--" denotes connection to the shift register, covered
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below.
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```
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IIe Connector Col/Row Arduino IDE Pin Teensy 2.0 Pin
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1 Y0 0 B0
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2 Y1 1 B1
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2 Y1 1 B1
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3 +5V +5v +5v
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4 Y2 2 B2
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4 Y2 2 B2
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5 SW1/CAPL -- --
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6 Y3 3 B3
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6 Y3 3 B3
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7 SW0/OAPL -- --
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8 Y4 24 E6
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8 Y4 24 E6
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9 CAPLOCK -- --
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10 Y5 4 B7
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10 Y5 4 B7
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11 CNTL -- --
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12 Y8 5 D0
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12 Y8 5 D0
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13 GND GND GND
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14 X0 6 D1
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14 X0 6 D1
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15 RESET -- --
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16 X2 9 C6
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17 X7 17 F6
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18 X1 10 C7
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18 X1 10 C7
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19 X5 16 F7
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20 X3 23 D5
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21 X4 15 B6
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@ -54,11 +56,13 @@ IIe Connector Col/Row Arduino IDE Pin Teensy 2.0 Pin
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24 SHIFT -- --
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25 Y7 13 B4
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26 X6 12 D7
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```
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Wiring note: With the keyboard sitting in front of you as though you were typing
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on it, pins 25/26 will be on the end of the connector closest to you, and pins
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1/2 will be on the end of the connector farthest from you:
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```
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+----------------+
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| | +-------+
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| | | 1/2 |
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@ -66,39 +70,35 @@ on it, pins 25/26 will be on the end of the connector closest to you, and pins
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| | | 25/26 |
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| | +-------+
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+----------------+
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```
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#### Modifier keys to shift register
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Follows DIP-8 package: http://www.ti.com/lit/ds/symlink/sn74ls165a.pdf
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```
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IIe Connector Col/Row Shift Register Input Notes
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5 SW1/CAPL B (pin 12) Active High
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7 SW0/OAPL A (pin 11) Active High
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9 CAPLOCK E (pin 3) Active Low, needs pull-up
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11 CNTL H (pin 6) Active Low, needs pull-up
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15 RESET G (pin 5) Active Low, needs pull-up, active low (only active with Control)
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24 SHIFT F (pin 4) Active Low, needs pull-up
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Shift Register Pins-to-Keys:
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0: open-apple, pull-down, active high
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1: closed-apple, pull-down, active high
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2: unused
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3: unused
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4: Caps-Lock, pull-up, active low
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5: Shift, pull-up, active low
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6: Reset, pull-up, active low (only active with Control)
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7: Control, pull-up, active low
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```
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#### Shift register to Teensy 2.0
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```
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Teensy 2.0 Pin Shift Register Pin
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18/F5 1: Parallel Load / SH/LD (active low)
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19/F4 15: Clock Enable / CLK INH (active low)
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20/F1 2: Clock Pulse / CLK (low-to-high edge triggered)
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21/F0 9: Data Pin (Q7)
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+5v 16: VCC
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GND 8: GND
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```
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Follows DIP-8 package: http://www.ti.com/lit/ds/symlink/sn74ls165a.pdf
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@ -106,10 +106,13 @@ Follows DIP-8 package: http://www.ti.com/lit/ds/symlink/sn74ls165a.pdf
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Leave these unconnected.
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```
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Teensy 2.0 Purpose
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7/D2 USB RX
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8/D3 USB TX
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11/D6 Caps Lock LED (LED_BUILTIN)
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```
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### Changes
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