mirror of
https://github.com/steve-chamberlin/fpga-disk-controller.git
synced 2024-12-26 03:32:52 +00:00
226 lines
8.0 KiB
HTML
226 lines
8.0 KiB
HTML
<HTML>
|
|
<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
|
|
<STYLE TYPE="text/css">
|
|
<!--
|
|
body,pre{
|
|
font-family:'Courier New', monospace;
|
|
color: #000000;
|
|
font-size:88%;
|
|
background-color: #ffffff;
|
|
}
|
|
h1 {
|
|
font-weight: bold;
|
|
margin-top: 24px;
|
|
margin-bottom: 10px;
|
|
border-bottom: 3px solid #000; font-size: 1em;
|
|
}
|
|
h2 {
|
|
font-weight: bold;
|
|
margin-top: 18px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.90em;
|
|
}
|
|
h3 {
|
|
font-weight: bold;
|
|
margin-top: 12px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.80em;
|
|
}
|
|
p {
|
|
font-size:78%;
|
|
}
|
|
P.Table {
|
|
margin-top: 4px;
|
|
margin-bottom: 4px;
|
|
margin-right: 4px;
|
|
margin-left: 4px;
|
|
}
|
|
table
|
|
{
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
border-collapse: collapse;
|
|
}
|
|
th {
|
|
font-weight:bold;
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
text-align:left;
|
|
font-size:78%;
|
|
}
|
|
td {
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
font-size:78%;
|
|
}
|
|
a {
|
|
color:#013C9A;
|
|
text-decoration:none;
|
|
}
|
|
|
|
a:visited {
|
|
color:#013C9A;
|
|
}
|
|
|
|
a:hover, a:active {
|
|
text-decoration:underline;
|
|
color:#5BAFD4;
|
|
}
|
|
.pass
|
|
{
|
|
background-color: #00ff00;
|
|
}
|
|
.fail
|
|
{
|
|
background-color: #ff0000;
|
|
}
|
|
.comment
|
|
{
|
|
font-size: 90%;
|
|
font-style: italic;
|
|
}
|
|
|
|
-->
|
|
</STYLE>
|
|
</HEAD>
|
|
<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>
|
|
synthesis: version Diamond (64-bit) 3.9.0.99.2
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
|
Thu Oct 05 12:19:47 2017
|
|
|
|
|
|
Command Line: synthesis -f yellowstone_blink_yellowstone_blink_lattice.synproj -gui
|
|
|
|
Synthesis options:
|
|
The -a option is MachXO2.
|
|
The -s option is 4.
|
|
The -t option is TQFP100.
|
|
The -d option is LCMXO2-1200HC.
|
|
Using package TQFP100.
|
|
Using performance grade 4.
|
|
|
|
|
|
##########################################################
|
|
|
|
### Lattice Family : MachXO2
|
|
|
|
### Device : LCMXO2-1200HC
|
|
|
|
### Package : TQFP100
|
|
|
|
### Speed : 4
|
|
|
|
##########################################################
|
|
|
|
|
|
|
|
INFO - synthesis: User-Selected Strategy Settings
|
|
Optimization goal = Balanced
|
|
Top-level module name = blink.
|
|
Target frequency = 1.000000 MHz.
|
|
Maximum fanout = 1000.
|
|
Timing path count = 3
|
|
BRAM utilization = 100.000000 %
|
|
DSP usage = true
|
|
DSP utilization = 100.000000 %
|
|
fsm_encoding_style = auto
|
|
resolve_mixed_drivers = 0
|
|
fix_gated_clocks = 1
|
|
|
|
Mux style = Auto
|
|
Use Carry Chain = true
|
|
carry_chain_length = 0
|
|
Loop Limit = 1950.
|
|
Use IO Insertion = TRUE
|
|
Use IO Reg = AUTO
|
|
|
|
Resource Sharing = TRUE
|
|
Propagate Constants = TRUE
|
|
Remove Duplicate Registers = TRUE
|
|
force_gsr = auto
|
|
ROM style = auto
|
|
RAM style = auto
|
|
The -comp option is FALSE.
|
|
The -syn option is FALSE.
|
|
-p C:/Users/chamberlin/Documents/Liron (searchpath added)
|
|
-p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added)
|
|
-p C:/Users/chamberlin/Documents/Liron/yellowstone_blink (searchpath added)
|
|
-p C:/Users/chamberlin/Documents/Liron (searchpath added)
|
|
Verilog design file = C:/Users/chamberlin/Documents/Liron/top.v
|
|
NGD file = yellowstone_blink_yellowstone_blink.ngd
|
|
-sdc option: SDC file input not used.
|
|
-lpf option: Output file option is ON.
|
|
Hardtimer checking is enabled (default). The -dt option is not used.
|
|
The -r option is OFF. [ Remove LOC Properties is OFF. ]
|
|
Technology check ok...
|
|
|
|
Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
|
Compile design.
|
|
Compile Design Begin
|
|
Analyzing Verilog file c:/users/chamberlin/documents/liron/top.v. VERI-1482
|
|
Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
|
Top module name (Verilog): blink
|
|
INFO - synthesis: c:/users/chamberlin/documents/liron/top.v(1): compiling module blink. VERI-1018
|
|
INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH. VERI-1018
|
|
WARNING - synthesis: c:/users/chamberlin/documents/liron/top.v(18): expression size 32 truncated to fit in target size 24. VERI-1209
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
|
|
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
|
|
Package Status: Final Version 1.42.
|
|
Top-level module name = blink.
|
|
|
|
|
|
|
|
GSR will not be inferred because no asynchronous signal was found in the netlist.
|
|
Applying 1.000000 MHz constraint to all clocks
|
|
|
|
WARNING - synthesis: No user .sdc file.
|
|
Results of NGD DRC are available in blink_drc.log.
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
|
|
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
|
|
All blocks are expanded and NGD expansion is successful.
|
|
Writing NGD file yellowstone_blink_yellowstone_blink.ngd.
|
|
|
|
################### Begin Area Report (blink)######################
|
|
Number of register bits => 21 of 1520 (1 % )
|
|
CCU2D => 11
|
|
FD1S3AX => 21
|
|
GSR => 1
|
|
OB => 2
|
|
OSCH => 1
|
|
################### End Area Report ##################
|
|
|
|
################### Begin BlackBox Report ######################
|
|
TSALL => 1
|
|
################### End BlackBox Report ##################
|
|
|
|
################### Begin Clock Report ######################
|
|
Clock Nets
|
|
Number of Clocks: 1
|
|
Net : clk, loads : 21
|
|
Clock Enable Nets
|
|
Number of Clock Enables: 0
|
|
Top 0 highest fanout Clock Enables:
|
|
Highest fanout non-clock nets
|
|
Top 10 highest fanout non-clock nets:
|
|
Net : pin_led_c_20, loads : 2
|
|
Net : n21, loads : 1
|
|
Net : n20, loads : 1
|
|
Net : n19, loads : 1
|
|
Net : n18, loads : 1
|
|
Net : n17, loads : 1
|
|
Net : n16, loads : 1
|
|
Net : n15, loads : 1
|
|
Net : n14, loads : 1
|
|
Net : n13, loads : 1
|
|
################### End Clock Report ##################
|
|
|
|
<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
|
|
--------------
|
|
--------------------------------------------------------------------------------
|
|
Constraint | Constraint| Actual|Levels
|
|
--------------------------------------------------------------------------------
|
|
| | |
|
|
create_clock -period 1000.000000 -name | | |
|
|
clk0 [get_nets clk] | 1.000 MHz| 181.028 MHz| 12
|
|
| | |
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
All constraints were met.
|
|
|
|
|
|
Peak Memory Usage: 49.246 MB
|
|
|
|
--------------------------------------------------------------
|
|
Elapsed CPU time for LSE flow : 0.406 secs
|
|
--------------------------------------------------------------
|
|
|
|
|
|
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
</PRE></FONT>
|
|
</BODY>
|
|
</HTML>
|