fpga-disk-controller/eagle/FPGA disk controller/ELL-i-DigitalIC.lbr

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<library>
<description>&lt;h3&gt;DigitalIC -- ELL-i open source co-op Eagle libraries&lt;/h3&gt;

&lt;p&gt;In this library you'll find digital ICs, such as MCUs, that are used in the ELL-i boards.&lt;/p&gt;

&lt;p&gt;Whenever possible, we prefer to use the components from the &lt;a href="https://github.com/Ell-i/SparkFun-Eagle-Libraries"&gt;SparkFun Public Eagle PCB Footprints&lt;/a&gt;, as they are available from &lt;a href="https://github.com/"&gt;GitHub&lt;/a&gt;. Whenever possible, we also prefer to push our components to the SparkFun libraries.  However, this is not always possible, and therefore we have our own libraries that for the most part contain components that cannot be found in the SparkFun libraries.&lt;/p&gt;</description>
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<package name="QFN-24_4MM">
<description>&lt;h3&gt;24 leads Quad-flat no-leads package (QNF)&lt;/h3&gt;

&lt;p&gt;4x4 mm, 0.5 mm pitch.   See the SparkFun-DigitalIC.lbr for additional QFN24 packages.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/QFN"&gt;Wikipedia article on QFNs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="QFN-24_4MM-H">
<description>&lt;h3&gt;24 leads Quad-flat no-leads package (QNF) with a hole&lt;/h3&gt;

&lt;p&gt;4x4 mm, 0.5 mm pitch, with a central hole.  This footprint may be better than the regular one, depending on your process and intentions.  See the SparkFun-DigitalIC.lbr for additional QFN24 packages.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/QFN"&gt;Wikipedia article on QFNs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<text x="-2.5" y="-3.15" size="0.4064" layer="27" ratio="10">&gt;VALUE</text>
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<package name="LQFP144">
<description>&lt;h3&gt;144 leads Low Profile Quad Flat Package (LQFP)&lt;/h3&gt;

&lt;p&gt;20x20 mm, 0.5 mm pitch, 1.5 mm height.&lt;/p&gt;

&lt;p&gt;&lt;b&gt;Note&lt;/b&gt; that this package has a "phantom" pad in the middle of it, i.e. a pad whose size is 0.00x0.00 mm, and who is named as NC (not connected).  This is needed as the STM32F42x has an extra pin (BYPASS_REG) in the WLCSP143 package, while it does not have it in the LQFP package.  This avoids us from having two different devices.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/LQFP"&gt;Wikipedia article on QFPs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="TQFP144">
<description>&lt;h3&gt;144 leads Thin Profile Quad Flat Package (TQFP)&lt;/h3&gt;

&lt;p&gt;20x20 mm, 0.5 mm pitch, 1 mm height.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/TQFP"&gt;Wikipedia article on QFPs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="LQFP100">
<description>&lt;h3&gt;100 leads Low Profile Quad Flat Package (LQFP)&lt;/h3&gt;

&lt;p&gt;14x14 mm, 0.5 mm pitch.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/LQFP"&gt;Wikipedia article on QFPs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="WLCSP143">
<description>&lt;h3&gt;143 balls Wafer Level Chip-Size Package (WLCSP)&lt;/h3&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/WLCSP"&gt;Wikipedia article&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;

&lt;p&gt;&lt;b&gt;Not&lt;/b&gt; proven in production.  Probably faulty, needs at least a review.&lt;/p&gt;</description>
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<package name="LQFP48">
<description>&lt;h3&gt;48 leads Low Profile Quad Flat Package (LQFP)&lt;/h3&gt;

&lt;p&gt;7x7 mm, 0.5 mm pitch.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/LQFP"&gt;Wikipedia article on QFPs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="LQFP64">
<description>&lt;h3&gt;64 leads Low Profile Quad Flat Package (LQFP)&lt;/h3&gt;

&lt;p&gt;10x10 mm, 0.5 mm pitch.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/LQFP"&gt;Wikipedia article on QFPs&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="CSBGA132-MACHXO2">
<description>&lt;h3&gt;132 balls chip sized Ball Grid Array (BGA) for Lattice MachXO2 series FPGAs&lt;/h3&gt;

&lt;p&gt;8x8 mm, 0.5 mm pitch.&lt;/p&gt;

&lt;p&gt;&lt;b&gt;Note&lt;/b&gt; that this package has extra non-connected invisible 0.0x0.0 sized pads, in the middle, named NC1-NC7.  That facilitates allowing csBGA 132 and TQFP 144 packages to be used with the same device.&lt;/p&gt;

&lt;p&gt;&lt;b&gt;Note&lt;/b&gt; that this package extra annotation in the Docu layer, showing which balls form together pin pairs in the FPGA pin assignment.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;Lattice &lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf"&gt;Package Diagrams&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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</package>
<package name="CSBGA132-ICE40">
<description>&lt;h3&gt;132 balls chip sized Ball Grid Array (BGA) for Lattice iCE40 series FPGAs&lt;/h3&gt;

&lt;p&gt;8x8 mm, 0.5 mm pitch.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;Lattice &lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/PackageDiagrams.pdf"&gt;Package Diagrams&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
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<package name="QFN-32">
<description>&lt;h3&gt;QFN 32-Pin package w/ Thermal Pad&lt;/h3&gt;
&lt;p&gt;&lt;b&gt;Note: Unproven!&lt;/b&gt;
&lt;p&gt;&lt;b&gt;Note&lt;/b&gt; that this package has two "phantom" pad in the middle of it, i.e. a pads whose size is 0.00x0.00 mm, and who are named as NC (not connected).  This avoids us from having two different ERP symbols.&lt;/p&gt;
&lt;p&gt;Copied from SparkFun-DigitalIC.lbr&lt;/p&gt;</description>
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<wire x1="-5.0546" y1="3.7846" x2="-3.7846" y2="5.0546" width="0.1524" layer="51"/>
<wire x1="-5.0546" y1="-5.0546" x2="5.0546" y2="-5.0546" width="0.1524" layer="51"/>
<wire x1="5.0546" y1="-5.0546" x2="5.0546" y2="5.0546" width="0.1524" layer="51"/>
<wire x1="5.0546" y1="5.0546" x2="-5.0546" y2="5.0546" width="0.1524" layer="51"/>
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<text x="-7.6962" y="3.7338" size="1.27" layer="51" ratio="6" rot="SR0">*</text>
<text x="-5.0038" y="7.62" size="2.0828" layer="25" ratio="10" rot="SR0">&gt;NAME</text>
<text x="-5.5626" y="-9.5758" size="2.0828" layer="27" ratio="10" rot="SR0">&gt;VALUE</text>
</package>
<package name="SOIC-16-NARROW">
<description>&lt;p&gt;
SOIC-16 package, narrow
&lt;/p&gt;
&lt;p&gt;
10 mm long, 6 mm wide.
150 mil (1.27 mm) pin spacing, 0.65 mm pad width, 1.75 mm pad length.
&lt;/p&gt;
&lt;p&gt;
JEDEC MS-012
&lt;/p&gt;
&lt;p&gt;
Not reviewed
&lt;/p&gt;
&lt;p&gt;
&lt;a href="http://grabcad.com/library/soic-package-narrow-8-10-14-and-16-pins-1"&gt;Possible step model&lt;/a&gt;
&lt;/p&gt;</description>
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<wire x1="5" y1="1.75" x2="5" y2="-1.75" width="0.127" layer="21"/>
<wire x1="5" y1="-1.75" x2="-5" y2="-1.75" width="0.127" layer="21"/>
<wire x1="-5" y1="-1.75" x2="-5" y2="1.75" width="0.127" layer="21"/>
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<smd name="3" x="-1.95" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="2" x="-3.25" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="1" x="-4.55" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="5" x="0.65" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="7" x="3.25" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="8" x="4.55" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="9" x="4.55" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="10" x="3.25" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="11" x="1.95" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="12" x="0.65" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="13" x="-0.65" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="14" x="-1.95" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="15" x="-3.25" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="16" x="-4.55" y="2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<smd name="6" x="1.95" y="-2.8" dx="1.75" dy="0.65" layer="1" rot="R90"/>
<text x="-3" y="0" size="1.27" layer="25">&gt;NAME</text>
<text x="-3" y="-1.5" size="1.27" layer="27">&gt;VALUE</text>
</package>
<package name="TQFP44-0.8MM">
<description>&lt;h3&gt;44-pin TGFP, 0.8 mm pitch, 10*10 mm body&lt;/h3&gt;
&lt;p&gt;Package drawn from &lt;a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf"&gt;Datasheet&lt;/a&gt; pages 154 and 155.
&lt;/p&gt;
&lt;p&gt;
Not reviewed
&lt;/p&gt;</description>
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<smd name="32" x="-3.2" y="5.7" dx="0.55" dy="1.5" layer="1"/>
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<smd name="28" x="0" y="5.7" dx="0.55" dy="1.5" layer="1"/>
<smd name="27" x="0.8" y="5.7" dx="0.55" dy="1.5" layer="1"/>
<smd name="26" x="1.6" y="5.7" dx="0.55" dy="1.5" layer="1"/>
<smd name="25" x="2.4" y="5.7" dx="0.55" dy="1.5" layer="1"/>
<smd name="24" x="3.2" y="5.7" dx="0.55" dy="1.5" layer="1"/>
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<rectangle x1="0.05" y1="2.18" x2="0.45" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="-0.45" y1="2.18" x2="-0.05" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="-0.95" y1="2.18" x2="-0.55" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="-1.45" y1="2.18" x2="-1.05" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="-1.95" y1="2.18" x2="-1.55" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="0.55" y1="2.18" x2="0.95" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="1.05" y1="2.18" x2="1.45" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="1.55" y1="2.18" x2="1.95" y2="2.42" layer="51" rot="R270"/>
<rectangle x1="-0.45" y1="-2.42" x2="-0.05" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="0.05" y1="-2.42" x2="0.45" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="0.55" y1="-2.42" x2="0.95" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="1.05" y1="-2.42" x2="1.45" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="1.55" y1="-2.42" x2="1.95" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="-0.95" y1="-2.42" x2="-0.55" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="-1.45" y1="-2.42" x2="-1.05" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="-1.95" y1="-2.42" x2="-1.55" y2="-2.18" layer="51" rot="R90"/>
<rectangle x1="2.1" y1="-0.37" x2="2.5" y2="-0.13" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="0.13" x2="2.5" y2="0.37" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="0.63" x2="2.5" y2="0.87" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="1.13" x2="2.5" y2="1.37" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="1.63" x2="2.5" y2="1.87" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="-0.87" x2="2.5" y2="-0.63" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="-1.37" x2="2.5" y2="-1.13" layer="51" rot="R180"/>
<rectangle x1="2.1" y1="-1.87" x2="2.5" y2="-1.63" layer="51" rot="R180"/>
<pad name="VIA4" x="-0.7" y="0.7" drill="0.4" stop="no" thermals="no"/>
<pad name="VIA3" x="0.7" y="0.7" drill="0.4" stop="no" thermals="no"/>
<pad name="VIA2" x="0.7" y="-0.7" drill="0.4" stop="no" thermals="no"/>
<pad name="VIA1" x="-0.7" y="-0.7" drill="0.4" stop="no" thermals="no"/>
<smd name="EP" x="0" y="0" dx="3.15" dy="3.15" layer="1" cream="no"/>
<smd name="NC1" x="0" y="0" dx="0" dy="0" layer="1" stop="no" thermals="no" cream="no"/>
<smd name="NC2" x="0" y="0" dx="0" dy="0" layer="1" stop="no" thermals="no" cream="no"/>
<rectangle x1="-1.45" y1="0.15" x2="-0.15" y2="1.45" layer="31"/>
<rectangle x1="0.15" y1="0.15" x2="1.45" y2="1.45" layer="31" rot="R270"/>
<rectangle x1="-1.45" y1="-1.45" x2="-0.15" y2="-0.15" layer="31" rot="R90"/>
<rectangle x1="0.15" y1="-1.45" x2="1.45" y2="-0.15" layer="31" rot="R180"/>
</package>
</packages>
<symbols>
<symbol name="LAN8720">
<description>&lt;h3&gt;LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver&lt;/h3&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf"&gt;Datasheet&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;

&lt;p&gt;TODO (perhaps): Replace with a more generic Ethernet PHY symbol&lt;/p&gt;</description>
<wire x1="-20.32" y1="25.4" x2="20.32" y2="25.4" width="0.254" layer="94"/>
<wire x1="20.32" y1="25.4" x2="20.32" y2="-27.94" width="0.254" layer="94"/>
<wire x1="20.32" y1="-27.94" x2="-20.32" y2="-27.94" width="0.254" layer="94"/>
<wire x1="-20.32" y1="-27.94" x2="-20.32" y2="25.4" width="0.254" layer="94"/>
<text x="-20.32" y="27.94" size="1.27" layer="95">&gt;NAME</text>
<text x="-20.32" y="-30.48" size="1.27" layer="96">&gt;VALUE</text>
<pin name="MDIO" x="-22.86" y="17.78" length="short"/>
<pin name="MDC" x="-22.86" y="15.24" length="short"/>
<pin name="NINT/REFCLKO" x="-22.86" y="12.7" length="short"/>
<pin name="TXD0" x="-22.86" y="7.62" length="short"/>
<pin name="TXD1" x="-22.86" y="5.08" length="short"/>
<pin name="TXEN" x="-22.86" y="2.54" length="short"/>
<pin name="RXD0" x="-22.86" y="0" length="short"/>
<pin name="RXD1" x="-22.86" y="-2.54" length="short"/>
<pin name="RXER" x="-22.86" y="-7.62" length="short"/>
<pin name="LED1/REGOFF" x="-22.86" y="-12.7" length="short"/>
<pin name="LED2/NINTSEL" x="-22.86" y="-15.24" length="short"/>
<pin name="NRST" x="-22.86" y="-20.32" length="short"/>
<pin name="TX+" x="22.86" y="17.78" length="short" rot="R180"/>
<pin name="TX-" x="22.86" y="12.7" length="short" rot="R180"/>
<pin name="RX+" x="22.86" y="-10.16" length="short" rot="R180"/>
<pin name="RX-" x="22.86" y="-15.24" length="short" rot="R180"/>
<pin name="XTAL1" x="-5.08" y="-30.48" length="short" rot="R90"/>
<pin name="XTAL2" x="5.08" y="-30.48" length="short" rot="R90"/>
<pin name="CRS_DV" x="-22.86" y="-5.08" length="short"/>
<pin name="RBIAS" x="12.7" y="-30.48" length="short" rot="R90"/>
<pin name="GND" x="-10.16" y="-30.48" length="short" rot="R90"/>
<pin name="VDD1A" x="-7.62" y="27.94" length="short" rot="R270"/>
<pin name="VDD2A" x="-2.54" y="27.94" length="short" rot="R270"/>
<pin name="VDDIO" x="2.54" y="27.94" length="short" rot="R270"/>
<pin name="VDDCR" x="7.62" y="27.94" length="short" rot="R270"/>
</symbol>
<symbol name="STM32-PA">
<description>&lt;h3&gt;STM32F-series MCU GPIO port A.&lt;/h3&gt;

&lt;p&gt;This port appears to be available, with all pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439.  The TSSOP20 package of the STM32F030 is an exception, exposing only PA0–PA7, PA9–PA10, PA13, and PA14.  The alternate functions vary from model to model.&lt;/p&gt;</description>
<pin name="PA0-ADC_IN0" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PA1-ADC_IN1" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PA2-ADC_IN2" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PA3-ADC_IN3" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PA4-ADC_IN4" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PA5-ADC_IN5" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PA6-ADC_IN6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PA7-ADC_IN7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PA8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PA9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PA10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PA11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PA12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PA13-SWDIO" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PA14-SWCLK" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PA15" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-15.24" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-15.24" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-14.824" y="21.436" size="1.778" layer="95">&gt;NAME</text>
<text x="-15.24" y="-25.4" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="STM32-PB">
<description>&lt;h3&gt;STM32F-series MCU GPIO port B.&lt;/h3&gt;

&lt;p&gt;This port appears to be available, with at least some pins exposed, throughout the STM32F-series, from STM32F030 to STM32F439.  The alternate functions vary from model to model.  The most commonly exposed pin is PB1, followed by PB0 and PB3–PB7, and then PB2 and PB8.&lt;/p&gt;</description>
<pin name="PB0-ADC_IN8" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PB1-ADC_IN9" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PB2" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PB3" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PB4" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PB5" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PB6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PB7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PB8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PB9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PB10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PB11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PB12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PB13" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PB14" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PB15" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-15.24" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-15.24" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-14.824" y="21.336" size="1.778" layer="95">&gt;NAME</text>
<text x="-14.84" y="-25.4" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="STM32-PC">
<description>&lt;h3&gt;STM32F-series MCU GPIO port C.&lt;/h3&gt;

&lt;p&gt;This port appears to be available, with at least some pins exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439.  The alternate functions vary from model to model.  In the lowest pin-count packages the port is not exposed.  The most commonly exposed pins are PC13–PC15.&lt;/p&gt;</description>
<pin name="PC0-ADC_IN10" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PC1-ADC_IN11" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PC2-ADC_IN12" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PC3-ADC_IN13" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PC4-ADC_IN14" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PC5-ADC_IN15" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PC6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PC7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PC8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PC9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PC10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PC11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PC12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PC13" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PC14-OSC32_IN" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PC15-OSC32_OUT" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-15.24" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-15.24" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-14.724" y="21.436" size="1.778" layer="95">&gt;NAME</text>
<text x="-15.24" y="-25.4" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="STM32-PD">
<description>&lt;h3&gt;STM32F-series MCU GPIO port D.&lt;/h3&gt;

&lt;p&gt;This port appears to be available, with at least one pin (PD2) exposed, throughout most of the STM32F-series, from STM32F030 to STM32F439. For example, STM32F050 does not have this port at all, and STM32F030 exposes PD2 in the largest LQPF64 package. The alternate functions vary from model to model.  In the lowest pin-count packages the port is not exposed.  &lt;/p&gt;</description>
<pin name="PD0" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PD1" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PD2" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PD3" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PD4" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PD5" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PD6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PD7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PD8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PD9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PD10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PD11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PD12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PD13" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PD14" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PD15" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-5.08" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-4.064" y="21.336" size="1.778" layer="95">&gt;NAME</text>
</symbol>
<symbol name="STM32-PE">
<description>&lt;h3&gt;STM32F-series MCU GPIO port E.&lt;/h3&gt;

&lt;p&gt;This port is available only in the higher end models of the STM32F-series.  The alternate functions vary from model to model.&lt;/p&gt;</description>
<pin name="PE0" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PE1" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PE2" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PE3" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PE4" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PE5" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PE6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PE7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PE8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PE9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PE10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PE11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PE12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PE13" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PE14" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PE15" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-5.08" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-4.064" y="21.336" size="1.778" layer="95">&gt;NAME</text>
</symbol>
<symbol name="STM32F4XX-PWR_WITH_BYPASS">
<description>&lt;h3&gt;STM32F-series MCU power pads, version 2.&lt;/h3&gt;

&lt;p&gt;This version has PDR_ON and BYPASS_REG pins.&lt;/p&gt;</description>
<pin name="VSS" x="12.7" y="0" length="short" direction="pwr" rot="R180"/>
<pin name="VSSA" x="12.7" y="-5.08" length="short" direction="pwr" rot="R180"/>
<pin name="VDD" x="-12.7" y="0" length="short" direction="pwr"/>
<pin name="VDDA" x="-12.7" y="-5.08" length="short" direction="pwr"/>
<pin name="VBAT" x="-12.7" y="5.08" length="short" direction="pwr"/>
<wire x1="-10.16" y1="10.16" x2="10.16" y2="10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="10.16" x2="10.16" y2="-20.32" width="0.254" layer="94"/>
<wire x1="10.16" y1="-20.32" x2="-10.16" y2="-20.32" width="0.254" layer="94"/>
<wire x1="-10.16" y1="-20.32" x2="-10.16" y2="10.16" width="0.254" layer="94"/>
<text x="-8.89" y="10.922" size="1.778" layer="94">&gt;NAME</text>
<pin name="PDR_ON" x="12.7" y="5.08" length="short" direction="in" rot="R180"/>
<pin name="BYPASS_REG" x="12.7" y="-10.16" length="short" direction="in" rot="R180"/>
<pin name="VCAP1" x="-12.7" y="-15.24" length="short"/>
<pin name="VCAP2" x="-12.7" y="-17.78" length="short"/>
</symbol>
<symbol name="STM32F4XX-CTL">
<description>&lt;h3&gt;STM32F-series MCU control pads, high-end.&lt;/h3&gt;

&lt;p&gt;This version has OSC_IN and OSC_OUT in PH0 and PH1, respectively, and has VREF+.&lt;/p&gt;</description>
<pin name="PH0-OSC_IN" x="-12.7" y="7.62" length="short"/>
<pin name="PH1-OSC_OUT" x="-12.7" y="5.08" length="short"/>
<pin name="NRST" x="-12.7" y="0" length="short"/>
<pin name="VREF+" x="-12.7" y="-7.62" length="short"/>
<pin name="BOOT0" x="-12.7" y="-2.54" length="short"/>
<wire x1="-10.16" y1="10.16" x2="10.16" y2="10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="10.16" x2="10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="-10.16" x2="-10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="-10.16" y1="-10.16" x2="-10.16" y2="10.16" width="0.254" layer="94"/>
<text x="-8.89" y="11.176" size="1.778" layer="95">&gt;NAME</text>
</symbol>
<symbol name="STM32-PF">
<description>&lt;h3&gt;STM32F-series MCU GPIO port F.&lt;/h3&gt;

&lt;p&gt;This port appears to be available throughout most of the STM32F-series, from STM32F030 to STM32F439.  The alternate functions vary from model to model.  In the lowest pin-count packages the port is not exposed.  The most commonly exposed pins are &lt;tt&gt;PF0&lt;/tt&gt;–&lt;tt&gt;PF1&lt;/tt&gt;, which are the external oscillator pins in the low-end devices.  In high-end devices the oscillator tends to be connected to &lt;tt&gt;PH0&lt;/tt&gt;–&lt;tt&gt;PH1&lt;/tt&gt; instead.  Consequently, if you have a low-end device that exposes only &lt;tt&gt;PF0&lt;/tt&gt;–&lt;tt&gt;PF1&lt;/tt&gt; as the oscillator, don't include this symbol but only a control symbol with the oscillator pins there.&lt;/p&gt;</description>
<pin name="PF0" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PF1" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PF2" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PF3" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PF4" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PF5" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PF6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PF7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PF8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PF9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PF10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PF11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PF12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PF13" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PF14" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PF15" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-5.08" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-4.064" y="21.336" size="1.778" layer="94">&gt;NAME</text>
</symbol>
<symbol name="STM32-PDF-LQFP64">
<description>&lt;h3&gt;STM32F-series MCU GPIO port D pin 2 and F pins 4-7.&lt;/h3&gt;

&lt;p&gt;Extra pins available in STM32F051
 LQFP64 package.&lt;/p&gt;</description>
<pin name="PD2" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PF4" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PF5" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PF6" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PF7" x="7.62" y="-5.08" length="short" rot="R180"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="-7.62" x2="-5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="-5.08" y1="7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
<text x="-4.064" y="8.636" size="1.778" layer="95">&gt;NAME</text>
</symbol>
<symbol name="STM32-PG">
<description>&lt;h3&gt;STM32F-series MCU GPIO port G.&lt;/h3&gt;

&lt;p&gt;This port is available only in the higher end models of the STM32F-series.  The alternate functions vary from model to model.&lt;/p&gt;</description>
<pin name="PG0" x="7.62" y="17.78" length="short" rot="R180"/>
<pin name="PG1" x="7.62" y="15.24" length="short" rot="R180"/>
<pin name="PG2" x="7.62" y="12.7" length="short" rot="R180"/>
<pin name="PG3" x="7.62" y="10.16" length="short" rot="R180"/>
<pin name="PG4" x="7.62" y="7.62" length="short" rot="R180"/>
<pin name="PG5" x="7.62" y="5.08" length="short" rot="R180"/>
<pin name="PG6" x="7.62" y="2.54" length="short" rot="R180"/>
<pin name="PG7" x="7.62" y="0" length="short" rot="R180"/>
<pin name="PG8" x="7.62" y="-2.54" length="short" rot="R180"/>
<pin name="PG9" x="7.62" y="-5.08" length="short" rot="R180"/>
<pin name="PG10" x="7.62" y="-7.62" length="short" rot="R180"/>
<pin name="PG11" x="7.62" y="-10.16" length="short" rot="R180"/>
<pin name="PG12" x="7.62" y="-12.7" length="short" rot="R180"/>
<pin name="PG13" x="7.62" y="-15.24" length="short" rot="R180"/>
<pin name="PG14" x="7.62" y="-17.78" length="short" rot="R180"/>
<pin name="PG15" x="7.62" y="-20.32" length="short" rot="R180"/>
<wire x1="5.08" y1="20.32" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-5.08" y1="20.32" x2="5.08" y2="20.32" width="0.254" layer="94"/>
<text x="-4.064" y="21.336" size="1.778" layer="94">&gt;NAME</text>
</symbol>
<symbol name="STM32FXXX-PWR">
<description>&lt;h3&gt;STM32F-series MCU power pads.&lt;/h3&gt;

&lt;p&gt;This version does not have the PDR_ON or BYPASS_REG pins.&lt;/p&gt;</description>
<pin name="VSS" x="12.7" y="0" length="short" direction="pwr" rot="R180"/>
<pin name="VSSA" x="12.7" y="-5.08" length="short" direction="pwr" rot="R180"/>
<pin name="VDD" x="-12.7" y="0" length="short" direction="pwr"/>
<pin name="VDDA" x="-12.7" y="-5.08" length="short" direction="pwr"/>
<pin name="VBAT" x="-12.7" y="5.08" length="short" direction="pwr"/>
<wire x1="-10.16" y1="10.16" x2="10.16" y2="10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="10.16" x2="10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="-10.16" x2="-10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="-10.16" y1="-10.16" x2="-10.16" y2="10.16" width="0.254" layer="94"/>
<text x="-8.89" y="10.922" size="1.778" layer="95">&gt;NAME</text>
<text x="-8.89" y="-12.7" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="STM32F0XX-CTL">
<description>&lt;h3&gt;STM32F-series MCU control pads, low-end.&lt;/h3&gt;

&lt;p&gt;This version has OSC_IN and OSC_OUT in PF0 and PF1, respectively, and has no VREF+.&lt;/p&gt;</description>
<pin name="PF0-OSC_IN" x="-12.7" y="7.62" length="short"/>
<pin name="PF1-OSC_OUT" x="-12.7" y="5.08" length="short"/>
<pin name="NRST" x="-12.7" y="0" length="short"/>
<pin name="BOOT0" x="-12.7" y="-5.08" length="short"/>
<wire x1="-10.16" y1="10.16" x2="10.16" y2="10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="10.16" x2="10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="-10.16" x2="-10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="-10.16" y1="-10.16" x2="-10.16" y2="10.16" width="0.254" layer="94"/>
<text x="-8.89" y="11.176" size="1.778" layer="95">&gt;NAME</text>
</symbol>
<symbol name="MACHXO2-ERB">
<description>&lt;h3&gt;Lattice MachXO2 Embedded Function Block (EFB) signal pins&lt;/h3&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/ApplicationNotes/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.pdf"&gt;Datasheet&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="TDO" x="22.86" y="2.54" length="middle" rot="R180"/>
<pin name="TDI" x="22.86" y="0" length="middle" rot="R180"/>
<pin name="TCK" x="22.86" y="-5.08" length="middle" rot="R180"/>
<pin name="TMS" x="22.86" y="-7.62" length="middle" rot="R180"/>
<pin name="SCL/PT12C" x="22.86" y="-15.24" length="middle" rot="R180"/>
<pin name="SDA/PT12D" x="22.86" y="-17.78" length="middle" rot="R180"/>
<pin name="DONE/PT17D" x="22.86" y="10.16" length="middle" rot="R180"/>
<pin name="INITN/PT17C" x="22.86" y="12.7" length="middle" rot="R180"/>
<pin name="PROGRAMN/PT15D" x="22.86" y="15.24" length="middle" rot="R180"/>
<pin name="SPISO/PB6D" x="-22.86" y="-5.08" length="middle"/>
<pin name="SISPI/PB20D" x="-22.86" y="-10.16" length="middle"/>
<pin name="MCLK/CCLK/PB6C" x="-22.86" y="-2.54" length="middle"/>
<pin name="CSSPIN/PB_2A..." x="-22.86" y="2.54" length="middle"/>
<pin name="SN/PB20C" x="-22.86" y="-12.7" length="middle"/>
<pin name="JTAGENB/PT15C" x="22.86" y="17.78" length="middle" rot="R180"/>
<wire x1="17.78" y1="20.32" x2="17.78" y2="-20.32" width="0.254" layer="94"/>
<wire x1="17.78" y1="-20.32" x2="-17.78" y2="-20.32" width="0.254" layer="94"/>
<wire x1="-17.78" y1="-20.32" x2="-17.78" y2="20.32" width="0.254" layer="94"/>
<wire x1="-17.78" y1="20.32" x2="17.78" y2="20.32" width="0.254" layer="94"/>
<pin name="PB_2B/4B/4D/5B/4B" x="-22.86" y="5.08" length="middle"/>
<text x="8.636" y="21.336" size="1.778" layer="94">&gt;NAME</text>
</symbol>
<symbol name="MACHXO2-CSBGA132-256-BOTTOM">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Additional bottom ports for csBGA 132&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PB_7A/12A/15A/18A/21A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PB_7B/12B/15B/18B/21B" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PB_7C/12C/18A/21A/24A" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PB_7D/12D/18B/21B/24B" x="10.16" y="-5.08" length="middle" rot="R180"/>
<wire x1="-27.94" y1="7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="-7.62" x2="-27.94" y2="-7.62" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-256-TOP">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Top ports in the csBGA 132 package, in addition to those available in QFN32.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PT_6A/6A/9A/9A/9A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PT_6B/6B/9B/9B/9B" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PT_8A/9A/12A/17A/18A" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PT_8B/9B/12B/17B/18B" x="10.16" y="-5.08" length="middle" rot="R180"/>
<wire x1="-27.94" y1="7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="-7.62" x2="-27.94" y2="-7.62" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-256-RIGHT">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Right ports in the csBGA 132 package, in addition to those available in QFN32.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PR_3D/3D/4D/5B/8B" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PR_3C/3C/4C/5A/8A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PR_3B/2D/3B/3B/5B" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PR_3A/2C/3A/3A/5A" x="10.16" y="12.7" length="middle" rot="R180"/>
<pin name="PR_2B/2B/2B/1B/2B" x="10.16" y="17.78" length="middle" rot="R180"/>
<pin name="PR_2A/2A/2A/1A/2A" x="10.16" y="20.32" length="middle" rot="R180"/>
<pin name="PR_5C/6C/9A/11A/15A" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PR_5D/6D/9B/11B/15B" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PR_6A/7A/9C/12A/16A" x="10.16" y="-10.16" length="middle" rot="R180"/>
<pin name="PR_6B/7B/9D/12B/16B" x="10.16" y="-12.7" length="middle" rot="R180"/>
<pin name="PR_6C/7C/10C/14A/19A" x="10.16" y="-17.78" length="middle" rot="R180"/>
<pin name="PR_6D/7D/10D/14B/19B" x="10.16" y="-20.32" length="middle" rot="R180"/>
<wire x1="-27.94" y1="22.86" x2="5.08" y2="22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="22.86" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-256-LEFT">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 256 / 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Left ports in the csBGA 132 package, in addition to those available in QFN32.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PL_3C/5A/5A/7C/10C" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PL_3D/5B/5B/7D/10D" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PL_5A/6A/8A/10A/14A" x="10.16" y="-10.16" length="middle" rot="R180"/>
<pin name="PL_5B/6B/8B/10B/14B" x="10.16" y="-12.7" length="middle" rot="R180"/>
<pin name="PL_6A/7C/10C/14A/20A" x="10.16" y="-17.78" length="middle" rot="R180"/>
<pin name="PL_6B/7D/10D/14B/20B" x="10.16" y="-20.32" length="middle" rot="R180"/>
<pin name="PL_3B/3B/3D/4B/7B" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PL_3A/3A/3C/4A/7A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PL_2D/2D/3B/3B/6B" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PL_2C/2C/3A/3A/6A" x="10.16" y="12.7" length="middle" rot="R180"/>
<pin name="PL_2B/2B/2D/2B/4B" x="10.16" y="17.78" length="middle" rot="R180"/>
<pin name="PL_2A/2A/2C/2A/4A" x="10.16" y="20.32" length="middle" rot="R180"/>
<wire x1="-27.94" y1="22.86" x2="5.08" y2="22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="22.86" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="5.08" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<text x="-27.94" y="17.78" size="1.778" layer="94" rot="R270">csBGA132 PL 256/640/...</text>
</symbol>
<symbol name="MACHXO2-CSBGA132-640-TOP">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Top ports in the csBGA 132 package, in addition to those available in 256.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV"&gt;MachXO2 640 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PT_/10A/15A/19A/21A" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PT_/10B/15B/19B/21B" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PT_/11A/16C/22A/25A" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PT_/11B/16D/22B/25B" x="10.16" y="-7.62" length="middle" rot="R180"/>
<pin name="PT_/6D/10B/11B/11B" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PT_/6C/10A/11A/11A" x="10.16" y="10.16" length="middle" rot="R180"/>
<wire x1="-27.94" y1="12.7" x2="5.08" y2="12.7" width="0.254" layer="94"/>
<wire x1="5.08" y1="12.7" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-640-LEFT">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Left ports in the csBGA 132 package, in addition to those available in 256.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV"&gt;MachXO2 640 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PL_/5D/5D/9B/13B" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PL_/5C/5C/9A/13A" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PL_/3D/4B/5B/8B" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PL_/3C/4A/5A/8A" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PL_/6C/8C/11A/16A" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PL_/6D/8D/11B/16B" x="10.16" y="-7.62" length="middle" rot="R180"/>
<wire x1="-27.94" y1="12.7" x2="5.08" y2="12.7" width="0.254" layer="94"/>
<wire x1="5.08" y1="12.7" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-640-RIGHT">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Right ports in the csBGA 132 package, in addition to those available in 256.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV"&gt;MachXO2 640 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PR_/6A/8C/10A/14A" x="7.62" y="-5.08" length="middle" rot="R180"/>
<pin name="PR_/6B/8D/10B/14B" x="7.62" y="-7.62" length="middle" rot="R180"/>
<pin name="PR_/3B/4B/4B/6B" x="7.62" y="7.62" length="middle" rot="R180"/>
<pin name="PR_/3A/4A/4A/6A" x="7.62" y="10.16" length="middle" rot="R180"/>
<pin name="PR_/5A/5A/6A/9A" x="7.62" y="2.54" length="middle" rot="R180"/>
<pin name="PR_/5B/5B/6B/9B" x="7.62" y="0" length="middle" rot="R180"/>
<wire x1="-27.94" y1="12.7" x2="2.54" y2="12.7" width="0.254" layer="94"/>
<wire x1="2.54" y1="12.7" x2="2.54" y2="-10.16" width="0.254" layer="94"/>
<wire x1="2.54" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-640-BOTTOM">
<description>&lt;h3&gt;Lattice MachXO2 csBGA 132 common I/O pins for 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Bottom ports in the csBGA 132 package, in addition to those available in 256.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-640Pinout.CSV"&gt;MachXO2 640 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PB_/14A/18C/22A/27A" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PB_/14B/18D/22B/27B" x="10.16" y="-7.62" length="middle" rot="R180"/>
<pin name="PB_/4C/6A/6A/7A" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PB_/4D/6B/6B/7B" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PB_/10A/11C/12A/15A" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PB_/10B/11D/12B/15B" x="10.16" y="0" length="middle" rot="R180"/>
<wire x1="-27.94" y1="12.7" x2="5.08" y2="12.7" width="0.254" layer="94"/>
<wire x1="5.08" y1="12.7" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-1200-TOP">
<description>&lt;h3&gt;Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Top ports in the csBGA 132 package, in addition to those available in 640.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV"&gt;MachXO2 1200 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PT_//17B/24B/27B" x="12.7" y="-7.62" length="middle" rot="R180"/>
<pin name="PT_//17A/23A/27A" x="12.7" y="-5.08" length="middle" rot="R180"/>
<pin name="PT_//16B/21B/24B" x="12.7" y="0" length="middle" rot="R180"/>
<pin name="PT_//16A/21A/24A" x="12.7" y="2.54" length="middle" rot="R180"/>
<pin name="PT_//11A/13A/14A" x="12.7" y="10.16" length="middle" rot="R180"/>
<pin name="PT_//11B/13B/14B" x="12.7" y="7.62" length="middle" rot="R180"/>
<wire x1="-25.4" y1="12.7" x2="7.62" y2="12.7" width="0.254" layer="94"/>
<wire x1="7.62" y1="12.7" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
<wire x1="7.62" y1="-10.16" x2="-25.4" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-1200-LEFT">
<description>&lt;h3&gt;Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Left ports in the csBGA 132 package, in addition to those available in 640.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV"&gt;MachXO2 1200 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PL_//2B/1B/3B" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PL_//2A/1A/3A" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PL_//4C/6A/9A" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PL_//4D/6B/9B" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PL_//10B/13B/19B" x="10.16" y="-7.62" length="middle" rot="R180"/>
<wire x1="-27.94" y1="10.16" x2="5.08" y2="10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="10.16" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-1200-RIGHT">
<description>&lt;h3&gt;Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Right ports in the csBGA 132 package, in addition to those available in 640.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV"&gt;MachXO2 1200 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PR_//8A/9A/13A" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PR_//8B/9B/13B" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PR_//10A/13A/18A" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PR_//10B/13B/18B" x="10.16" y="-7.62" length="middle" rot="R180"/>
<pin name="PR_//2D/2B/3B" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PR_//2C/2A/3A" x="10.16" y="10.16" length="middle" rot="R180"/>
<wire x1="-27.94" y1="12.7" x2="5.08" y2="12.7" width="0.254" layer="94"/>
<wire x1="5.08" y1="12.7" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-1200-BOTTOM">
<description>&lt;h3&gt;Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Bottom ports in the csBGA 132 package, in addition to those available in 640.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV"&gt;MachXO2 1200 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PB_//20B/24B/29B" x="10.16" y="-10.16" length="middle" rot="R180"/>
<pin name="PB_//9D/9B/10B" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PB_//4A/3A/3A" x="10.16" y="12.7" length="middle" rot="R180"/>
<pin name="PB_//4B/3B/3B" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PB_//15C/19A/23A" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PB_//15D/19B/23B" x="10.16" y="-5.08" length="middle" rot="R180"/>
<wire x1="-27.94" y1="15.24" x2="5.08" y2="15.24" width="0.254" layer="94"/>
<wire x1="5.08" y1="15.24" x2="5.08" y2="-15.24" width="0.254" layer="94"/>
<wire x1="5.08" y1="-15.24" x2="-27.94" y2="-15.24" width="0.254" layer="94"/>
<pin name="PB_//20A/24A/29A" x="10.16" y="-12.7" length="middle" rot="R180"/>
<pin name="PB_//9C/9A/10A" x="10.16" y="5.08" length="middle" rot="R180"/>
</symbol>
<symbol name="MACHXO2-CSBGA132-PWR">
<description>&lt;h3&gt;Lattice MachXO2 common power pins for 256 / 640 / 1200 / 2000 / 4000&lt;/h3&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="VCC@A1" x="-22.86" y="20.32" length="middle"/>
<pin name="GND@A5" x="-22.86" y="12.7" length="middle"/>
<pin name="VCC@A14" x="-22.86" y="22.86" length="middle"/>
<pin name="VCCIO0@A8" x="-22.86" y="5.08" length="middle"/>
<pin name="VCCIO0@B10" x="-22.86" y="0" length="middle"/>
<pin name="GND@B11" x="-22.86" y="-5.08" length="middle"/>
<pin name="VCCIO0@C5" x="-22.86" y="2.54" length="middle"/>
<pin name="VCCIO3/5@D3" x="22.86" y="27.94" length="middle" rot="R180"/>
<pin name="GND@D2" x="22.86" y="22.86" length="middle" rot="R180"/>
<pin name="VCCIO1@D14" x="-22.86" y="-12.7" length="middle"/>
<pin name="GND@D13" x="-22.86" y="-22.86" length="middle"/>
<pin name="VCCIO4@G1" x="22.86" y="15.24" length="middle" rot="R180"/>
<pin name="GND@G2" x="22.86" y="10.16" length="middle" rot="R180"/>
<pin name="VCCIO1@H14" x="-22.86" y="-15.24" length="middle"/>
<pin name="GND@H13" x="-22.86" y="-25.4" length="middle"/>
<pin name="VCCIO1@L12" x="-22.86" y="-17.78" length="middle"/>
<pin name="GND@L13" x="-22.86" y="-27.94" length="middle"/>
<pin name="VCCIO2@M6" x="22.86" y="-17.78" length="middle" rot="R180"/>
<pin name="GND@P5" x="22.86" y="-22.86" length="middle" rot="R180"/>
<pin name="VCCIO2@N11" x="22.86" y="-15.24" length="middle" rot="R180"/>
<pin name="VCCIO2@P1" x="22.86" y="-12.7" length="middle" rot="R180"/>
<pin name="GND@P10" x="-22.86" y="15.24" length="middle"/>
<pin name="VCC@P14" x="-22.86" y="27.94" length="middle"/>
<pin name="VCC@N1" x="-22.86" y="25.4" length="middle"/>
<pin name="GND@L2" x="22.86" y="-5.08" length="middle" rot="R180"/>
<pin name="VCCIO3@L1" x="22.86" y="0" length="middle" rot="R180"/>
<wire x1="-17.78" y1="-30.48" x2="-17.78" y2="30.48" width="0.254" layer="94"/>
<wire x1="-17.78" y1="30.48" x2="17.78" y2="30.48" width="0.254" layer="94"/>
<wire x1="17.78" y1="30.48" x2="17.78" y2="-30.48" width="0.254" layer="94"/>
<wire x1="17.78" y1="-30.48" x2="-17.78" y2="-30.48" width="0.254" layer="94"/>
</symbol>
<symbol name="MACHXO2-QFN32-PWR">
<description>&lt;h3&gt;Lattice MachXO2 common power pins for QFN32 package&lt;/h3&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="VCC" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="GND" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="VCCIO0" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="VCCIO1" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="VCCIO2" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="VCCIO3" x="10.16" y="-7.62" length="middle" rot="R180"/>
<wire x1="-10.16" y1="-10.16" x2="-10.16" y2="10.16" width="0.254" layer="94"/>
<wire x1="-10.16" y1="10.16" x2="5.08" y2="10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="10.16" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="-10.16" x2="-10.16" y2="-10.16" width="0.254" layer="94"/>
<text x="-4.064" y="11.176" size="1.778" layer="95">&gt;NAME</text>
<text x="-5.08" y="-12.7" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="ELLI-STM32-PA">
<wire x1="-38.1" y1="20.32" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-38.1" y1="20.32" x2="-15.24" y2="20.32" width="0.254" layer="94"/>
<wire x1="-15.24" y1="-22.86" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<text x="-35.56" y="17.78" size="1.27" layer="94" align="center-left">Arduino A0</text>
<text x="-35.56" y="15.24" size="1.27" layer="94" align="center-left">ETH RMII_REF_CLK</text>
<text x="-35.56" y="12.7" size="1.27" layer="94" align="center-left">ETH RMII_MDIO</text>
<text x="-35.56" y="10.16" size="1.27" layer="94" align="center-left">Arduino D6</text>
<text x="-35.56" y="7.62" size="1.27" layer="94" align="center-left">Arduino A2</text>
<text x="-35.56" y="5.08" size="1.27" layer="94" align="center-left">Arduino A3</text>
<text x="-35.56" y="2.54" size="1.27" layer="94" align="center-left">Arduino D12 / SPI MISO</text>
<text x="-35.56" y="0" size="1.27" layer="94" align="center-left">ETH RMII_CRS_DV</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left">MCO</text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left">Arduino D1 / TX</text>
<text x="-35.56" y="-7.62" size="1.27" layer="94" align="center-left">Arduino D0 / RX</text>
<text x="-35.56" y="-10.16" size="1.27" layer="94" align="center-left">Arduino D3 / CTS</text>
<text x="-35.56" y="-12.7" size="1.27" layer="94" align="center-left">Arduino D4 / RTS</text>
<text x="-35.56" y="-15.24" size="1.27" layer="94" align="center-left">JTMS / SWDIO</text>
<text x="-35.56" y="-17.78" size="1.27" layer="94" align="center-left">JTCK / SWCLK</text>
<text x="-35.56" y="-20.32" size="1.27" layer="94" align="center-left">JTDI / Arduino D10 / SPI SS</text>
</symbol>
<symbol name="ELLI-SMALL-STM32-PA">
<description>&lt;h3&gt;ELL-i functions for STM32F Port A&lt;/h3&gt;

&lt;p&gt;STM32F051/030 64-pin TQFP version&lt;/p&gt;</description>
<wire x1="-38.1" y1="20.32" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-38.1" y1="20.32" x2="-15.24" y2="20.32" width="0.254" layer="94"/>
<wire x1="-15.24" y1="-22.86" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<text x="-35.56" y="17.78" size="1.27" layer="94" align="center-left">Arduino A0</text>
<text x="-35.56" y="15.24" size="1.27" layer="94" align="center-left">ENC28J60 Interrupt</text>
<text x="-35.56" y="12.7" size="1.27" layer="94" align="center-left">Arduino A1</text>
<text x="-35.56" y="10.16" size="1.27" layer="94" align="center-left">Arduino D6</text>
<text x="-35.56" y="7.62" size="1.27" layer="94" align="center-left">Arduino A2</text>
<text x="-35.56" y="5.08" size="1.27" layer="94" align="center-left">Arduino A3</text>
<text x="-35.56" y="2.54" size="1.27" layer="94" align="center-left">D12 / SPI1_MISO</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left">MCO</text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left">Arduino D1 / TX</text>
<text x="-35.56" y="-7.62" size="1.27" layer="94" align="center-left">Arduino D0 / RX</text>
<text x="-35.56" y="-10.16" size="1.27" layer="94" align="center-left">Arduino D3 / CTS</text>
<text x="-35.56" y="-12.7" size="1.27" layer="94" align="center-left">Arduino D4 / RTS</text>
<text x="-35.56" y="-15.24" size="1.27" layer="94" align="center-left">SWDIO</text>
<text x="-35.56" y="-17.78" size="1.27" layer="94" align="center-left">SWCLK</text>
<text x="-35.56" y="-20.32" size="1.27" layer="94" align="center-left">Arduino D10</text>
</symbol>
<symbol name="ELLI-STM32-PB">
<wire x1="-38.1" y1="20.32" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-38.1" y1="20.32" x2="-15.24" y2="20.32" width="0.254" layer="94"/>
<wire x1="-15.24" y1="-22.86" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<text x="-35.56" y="17.78" size="1.27" layer="94" align="center-left">Arduino D9 (PWM)</text>
<text x="-35.56" y="15.24" size="1.27" layer="94" align="center-left">Arduino D5 (PWM)</text>
<text x="-35.56" y="12.7" size="1.27" layer="94" align="center-left">-&gt; MachXO2 SN</text>
<text x="-35.56" y="10.16" size="1.27" layer="94" align="center-left">JTDO / Arduino D13 / SPI1_SCK</text>
<text x="-35.56" y="7.62" size="1.27" layer="94" align="center-left">JNRST / JTAGENB</text>
<text x="-35.56" y="5.08" size="1.27" layer="94" align="center-left">Arduino D11 (PWM) / SPI1_MOSI</text>
<text x="-35.56" y="2.54" size="1.27" layer="94" align="center-left">Arduino A5 / I2C_SCL</text>
<text x="-35.56" y="0" size="1.27" layer="94" align="center-left">FMC_NL/NADV</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left">Arduino D7</text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left">Arduino A4 / I2C_SDA</text>
<text x="-35.56" y="-7.62" size="1.27" layer="94" align="center-left">ELL-i I2C2_SCL</text>
<text x="-35.56" y="-10.16" size="1.27" layer="94" align="center-left">ELL-i I2C2 SDA</text>
<text x="-35.56" y="-12.7" size="1.27" layer="94" align="center-left">ELL-i SPI2_SS / CAN2_RX</text>
<text x="-35.56" y="-15.24" size="1.27" layer="94" align="center-left">ELL-i SPI2_SCK / CAN2_TX</text>
<text x="-35.56" y="-17.78" size="1.27" layer="94" align="center-left">ELL-i SPI2_MISO</text>
<text x="-35.56" y="-20.32" size="1.27" layer="94" align="center-left">ELL-i SPI2_MOSI</text>
</symbol>
<symbol name="ELLI-SMALL-STM32-PB">
<description>&lt;h3&gt;ELL-i functions for STM32F Port B&lt;/h3&gt;

&lt;p&gt;STM32F051/030 64-pin TQFP version&lt;/p&gt;</description>
<wire x1="-38.1" y1="20.32" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-38.1" y1="20.32" x2="-15.24" y2="20.32" width="0.254" layer="94"/>
<wire x1="-15.24" y1="-22.86" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<text x="-35.56" y="17.78" size="1.27" layer="94" align="center-left">Arduino D9 (PWM)</text>
<text x="-35.56" y="15.24" size="1.27" layer="94" align="center-left">Arduino D5 (PWM)</text>
<text x="-35.56" y="12.7" size="1.27" layer="94" align="center-left">-&gt; MachXO2 SN*</text>
<text x="-35.56" y="10.16" size="1.27" layer="94" align="center-left">Arduino D13 / SPI_SCK</text>
<text x="-35.56" y="7.62" size="1.27" layer="94" align="center-left">-&gt; MachXO2 JTAGENB</text>
<text x="-35.56" y="5.08" size="1.27" layer="94" align="center-left">Arduino D11 (PWM) / SPI_MOSI</text>
<text x="-35.56" y="2.54" size="1.27" layer="94" align="center-left">Arduino A5 / I2C_SCL</text>
<text x="-35.56" y="0" size="1.27" layer="94" align="center-left">Arduino D8</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left">Arduino D7</text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left">ARduino A4 / I2C_SDA</text>
<text x="-35.56" y="-7.62" size="1.27" layer="94" align="center-left">ELL-i I2C2_SCL</text>
<text x="-35.56" y="-10.16" size="1.27" layer="94" align="center-left">ELL-i I2C2 SDA</text>
<text x="-35.56" y="-12.7" size="1.27" layer="94" align="center-left">ELL-i SPI2_SS / CAN2_RX</text>
<text x="-35.56" y="-15.24" size="1.27" layer="94" align="center-left">ELL-i SPI2_SCK / CAN2_TX</text>
<text x="-35.56" y="-17.78" size="1.27" layer="94" align="center-left">ELL-i SPI2_MISO</text>
<text x="-35.56" y="-20.32" size="1.27" layer="94" align="center-left">ELL-i SPI2_MOSI</text>
</symbol>
<symbol name="ELLI-STM32-PC">
<wire x1="-38.1" y1="20.32" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-38.1" y1="20.32" x2="-15.24" y2="20.32" width="0.254" layer="94"/>
<wire x1="-15.24" y1="-22.86" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<text x="-35.56" y="17.78" size="1.27" layer="94" align="center-left">FMC_SNDWE</text>
<text x="-35.56" y="15.24" size="1.27" layer="94" align="center-left">ETH MDC</text>
<text x="-35.56" y="12.7" size="1.27" layer="94" align="center-left">FMC_SNDE0</text>
<text x="-35.56" y="10.16" size="1.27" layer="94" align="center-left">FMC_SDCKE0</text>
<text x="-35.56" y="7.62" size="1.27" layer="94" align="center-left">ETH RMII_RXD0</text>
<text x="-35.56" y="5.08" size="1.27" layer="94" align="center-left">ETH RMII_RXD1</text>
<text x="-35.56" y="2.54" size="1.27" layer="94" align="center-left">ELL-i LVSD 6T</text>
<text x="-35.56" y="0" size="1.27" layer="94" align="center-left">ELL-i LVDS 6C</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left"></text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left"></text>
<text x="-35.56" y="-7.62" size="1.27" layer="94" align="center-left">ELL-i USART3_TX</text>
<text x="-35.56" y="-10.16" size="1.27" layer="94" align="center-left">ELL-i USART3_RX</text>
<text x="-35.56" y="-12.7" size="1.27" layer="94" align="center-left">-&gt; MachXO2 CSSPIN</text>
<text x="-35.56" y="-15.24" size="1.27" layer="94" align="center-left">TAMP1</text>
<text x="-35.56" y="-17.78" size="1.27" layer="94" align="center-left">OSC32_IN</text>
<text x="-35.56" y="-20.32" size="1.27" layer="94" align="center-left">OSC32_OUT</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left">-&gt; MachXO2 PROGRAMN</text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left">-&gt; MachXO2 JTDI</text>
</symbol>
<symbol name="ELLI-SMALL-STM32-PC">
<description>&lt;h3&gt;ELL-i functions for STM32F Port C&lt;/h3&gt;

&lt;p&gt;STM32F051/030 64-pin TQFP version&lt;/p&gt;</description>
<wire x1="-38.1" y1="20.32" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-38.1" y1="20.32" x2="-15.24" y2="20.32" width="0.254" layer="94"/>
<wire x1="-15.24" y1="-22.86" x2="-38.1" y2="-22.86" width="0.254" layer="94"/>
<text x="-35.56" y="17.78" size="1.27" layer="94" align="center-left">ELL-i LVDS 3T</text>
<text x="-35.56" y="15.24" size="1.27" layer="94" align="center-left">ELL-i LVDS 3C</text>
<text x="-35.56" y="12.7" size="1.27" layer="94" align="center-left">ELL-i LVDS 4T</text>
<text x="-35.56" y="10.16" size="1.27" layer="94" align="center-left">ELL-i LVDS 4C</text>
<text x="-35.56" y="7.62" size="1.27" layer="94" align="center-left">ELL-i LVDS 5T</text>
<text x="-35.56" y="5.08" size="1.27" layer="94" align="center-left">ELL-i LVDS 5C</text>
<text x="-35.56" y="2.54" size="1.27" layer="94" align="center-left">ELL-i LVDS 6T</text>
<text x="-35.56" y="0" size="1.27" layer="94" align="center-left">ELL-i LVDS 6C</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left"></text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left"></text>
<text x="-35.56" y="-7.62" size="1.27" layer="94" align="center-left">ELL-i USART3_TX (GPIO)</text>
<text x="-35.56" y="-10.16" size="1.27" layer="94" align="center-left">ELL-i USART3_RX (GPIO)</text>
<text x="-35.56" y="-12.7" size="1.27" layer="94" align="center-left">-&gt; MachXO2CSSPIN</text>
<text x="-35.56" y="-15.24" size="1.27" layer="94" align="center-left">TAMP1</text>
<text x="-35.56" y="-17.78" size="1.27" layer="94" align="center-left">OSC32_IN</text>
<text x="-35.56" y="-20.32" size="1.27" layer="94" align="center-left">OSC32_OUT</text>
<text x="-35.56" y="-2.54" size="1.27" layer="94" align="center-left">-&gt; Mach XO2 PROGRAMN</text>
<text x="-35.56" y="-5.08" size="1.27" layer="94" align="center-left">-&gt; Mach XO2 JTDI</text>
</symbol>
<symbol name="ELLI-STM32-PD">
<wire x1="-27.94" y1="20.32" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-27.94" y1="20.32" x2="-5.08" y2="20.32" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<text x="-25.4" y="17.78" size="1.27" layer="94" align="center-left">FMC_D2</text>
<text x="-25.4" y="15.24" size="1.27" layer="94" align="center-left">FMC_D3</text>
<text x="-25.4" y="10.16" size="1.27" layer="94" align="center-left">FMC_CLK</text>
<text x="-25.4" y="7.62" size="1.27" layer="94" align="center-left">FMC_NOE</text>
<text x="-25.4" y="5.08" size="1.27" layer="94" align="center-left">FMC_NWE</text>
<text x="-25.4" y="2.54" size="1.27" layer="94" align="center-left">FMC_NWAIT</text>
<text x="-25.4" y="0" size="1.27" layer="94" align="center-left">FMC_NE1</text>
<text x="-25.4" y="-2.54" size="1.27" layer="94" align="center-left">FMC_D13</text>
<text x="-25.4" y="-5.08" size="1.27" layer="94" align="center-left">FMC_D14</text>
<text x="-25.4" y="-7.62" size="1.27" layer="94" align="center-left">FMC_D15</text>
<text x="-25.4" y="-10.16" size="1.27" layer="94" align="center-left">FMC_A16</text>
<text x="-25.4" y="-12.7" size="1.27" layer="94" align="center-left">FMC_A17</text>
<text x="-25.4" y="-15.24" size="1.27" layer="94" align="center-left">FMC_A18</text>
<text x="-25.4" y="-17.78" size="1.27" layer="94" align="center-left">FMC_D0</text>
<text x="-25.4" y="-20.32" size="1.27" layer="94" align="center-left">FMC_D1</text>
<text x="-25.4" y="12.7" size="1.27" layer="94" align="center-left">Arduino D2</text>
</symbol>
<symbol name="ELLI-STM32-PE">
<wire x1="-27.94" y1="20.32" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-27.94" y1="20.32" x2="-5.08" y2="20.32" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<text x="-25.4" y="17.78" size="1.27" layer="94" align="center-left">FMC_NBL0</text>
<text x="-25.4" y="15.24" size="1.27" layer="94" align="center-left">FMC_NBL1</text>
<text x="-25.4" y="12.7" size="1.27" layer="94" align="center-left">FMC_A23</text>
<text x="-25.4" y="10.16" size="1.27" layer="94" align="center-left">FMC_A19</text>
<text x="-25.4" y="7.62" size="1.27" layer="94" align="center-left">FMC_A20</text>
<text x="-25.4" y="5.08" size="1.27" layer="94" align="center-left">FMC_A21</text>
<text x="-25.4" y="2.54" size="1.27" layer="94" align="center-left">FMC_A22</text>
<text x="-25.4" y="0" size="1.27" layer="94" align="center-left">FMC_D4</text>
<text x="-25.4" y="-2.54" size="1.27" layer="94" align="center-left">FMC_D5</text>
<text x="-25.4" y="-5.08" size="1.27" layer="94" align="center-left">FMC_D6</text>
<text x="-25.4" y="-7.62" size="1.27" layer="94" align="center-left">FMC_D7</text>
<text x="-25.4" y="-10.16" size="1.27" layer="94" align="center-left">FMC_D8</text>
<text x="-25.4" y="-12.7" size="1.27" layer="94" align="center-left">FMC_D9</text>
<text x="-25.4" y="-15.24" size="1.27" layer="94" align="center-left">FMC_D10</text>
<text x="-25.4" y="-17.78" size="1.27" layer="94" align="center-left">FMC_D11</text>
<text x="-25.4" y="-20.32" size="1.27" layer="94" align="center-left">FMC_D12</text>
</symbol>
<symbol name="ELLI-STM32-PF">
<wire x1="-27.94" y1="20.32" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-27.94" y1="20.32" x2="-5.08" y2="20.32" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<text x="-25.4" y="17.78" size="1.27" layer="94" align="center-left">FMC_A0</text>
<text x="-25.4" y="15.24" size="1.27" layer="94" align="center-left">FMC_A1</text>
<text x="-25.4" y="12.7" size="1.27" layer="94" align="center-left">FMC_A2</text>
<text x="-25.4" y="10.16" size="1.27" layer="94" align="center-left">FMC_A3</text>
<text x="-25.4" y="7.62" size="1.27" layer="94" align="center-left">FMC_A4</text>
<text x="-25.4" y="5.08" size="1.27" layer="94" align="center-left">FMC_A5</text>
<text x="-25.4" y="2.54" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="0" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="-2.54" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="-5.08" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="-7.62" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="-10.16" size="1.27" layer="94" align="center-left">FMC_SNDRAS</text>
<text x="-25.4" y="-12.7" size="1.27" layer="94" align="center-left">FMC_A6</text>
<text x="-25.4" y="-15.24" size="1.27" layer="94" align="center-left">FMC_A7</text>
<text x="-25.4" y="-17.78" size="1.27" layer="94" align="center-left">FMC_A8</text>
<text x="-25.4" y="-20.32" size="1.27" layer="94" align="center-left">FMC_A9</text>
<text x="-25.4" y="2.54" size="1.27" layer="94" align="center-left">Arduino A1</text>
<text x="-25.4" y="0" size="1.27" layer="94" align="center-left">ELL-i LVDS 2T</text>
<text x="-25.4" y="-2.54" size="1.27" layer="94" align="center-left">ELL-i LVDS 1C</text>
<text x="-25.4" y="-5.08" size="1.27" layer="94" align="center-left">ELL-i LVDS 1T</text>
<text x="-25.4" y="-7.62" size="1.27" layer="94" align="center-left">ELL-i LVDS 2C</text>
</symbol>
<symbol name="ELLI-STM32-PG">
<wire x1="-27.94" y1="20.32" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-27.94" y1="20.32" x2="-5.08" y2="20.32" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<text x="-25.4" y="17.78" size="1.27" layer="94" align="center-left">FMC_A10</text>
<text x="-25.4" y="15.24" size="1.27" layer="94" align="center-left">FMC_A11</text>
<text x="-25.4" y="12.7" size="1.27" layer="94" align="center-left">FMC_A12</text>
<text x="-25.4" y="10.16" size="1.27" layer="94" align="center-left">FMC_A13</text>
<text x="-25.4" y="7.62" size="1.27" layer="94" align="center-left">FMC_A14</text>
<text x="-25.4" y="5.08" size="1.27" layer="94" align="center-left">FMC_A15</text>
<text x="-25.4" y="2.54" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="0" size="1.27" layer="94" align="center-left"></text>
<text x="-25.4" y="-2.54" size="1.27" layer="94" align="center-left">FMC_SDCLK</text>
<text x="-25.4" y="-5.08" size="1.27" layer="94" align="center-left">FMC_NE2</text>
<text x="-25.4" y="-7.62" size="1.27" layer="94" align="center-left">FMC_NE3</text>
<text x="-25.4" y="-10.16" size="1.27" layer="94" align="center-left">ETH RMII_TXEN</text>
<text x="-25.4" y="-12.7" size="1.27" layer="94" align="center-left">FMC_NE4</text>
<text x="-25.4" y="-15.24" size="1.27" layer="94" align="center-left">ETH RMII_TXD0</text>
<text x="-25.4" y="-17.78" size="1.27" layer="94" align="center-left">ETH RMII_TXD1</text>
<text x="-25.4" y="2.54" size="1.27" layer="94" align="center-left">Arduino D8</text>
<text x="-25.4" y="0" size="1.27" layer="94" align="center-left">ELL-i LVDS 5T</text>
<text x="-25.4" y="-20.32" size="1.27" layer="94" align="center-left">FMC_SNDCAS</text>
</symbol>
<symbol name="MACHXO2-QFN32-256">
<description>&lt;h3&gt;Lattice MachXO2 common I/O pins for 256&lt;/h3&gt;

&lt;p&gt;Generic pins available in the QFN32 package.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-256Pinout.CSV"&gt;MachXO2 256 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PR_5A/5C/5C/7A/10A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PR_5B/5D/5D/7B/10B" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PL_5C/7A/9A/12A/17A" x="10.16" y="12.7" length="middle" rot="R180"/>
<pin name="PL_5D/7B/9B/12B/17B" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PB_4C/10C/11A/16A/20A" x="10.16" y="-10.16" length="middle" rot="R180"/>
<pin name="PB_4D/10D/11B/16B/20B" x="10.16" y="-12.7" length="middle" rot="R180"/>
<pin name="PB_4A/6C/9A/11A/13A" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PB_4B/6D/9B/11B/13B" x="10.16" y="-5.08" length="middle" rot="R180"/>
<wire x1="5.08" y1="15.24" x2="5.08" y2="-15.24" width="0.254" layer="94"/>
<wire x1="5.08" y1="15.24" x2="-27.94" y2="15.24" width="0.254" layer="94"/>
<wire x1="5.08" y1="-15.24" x2="-27.94" y2="-15.24" width="0.254" layer="94"/>
<text x="-4.064" y="16.256" size="1.778" layer="94">&gt;NAME</text>
</symbol>
<symbol name="MACHXO2-TQFP144-1200">
<description>&lt;h3&gt;Lattice MachXO2 common I/O pins for 1200 / 2000 / 4000&lt;/h3&gt;

&lt;p&gt;Ports in the TQFP 144 package for MachXO2 1200, in addition to those available in csBGA 132 package.&lt;/p&gt;

&lt;ul&gt;
  &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO2-1200Pinout.CSV"&gt;MachXO2 1200 pinout&lt;/a&gt; (CSV)&lt;/li&gt;
&lt;/ul&gt;</description>
<pin name="PL_//10A/13A/19A" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PT_//9C/10A/10A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PT_//9D/10B/10B" x="10.16" y="2.54" length="middle" rot="R180"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="-5.08" x2="-27.94" y2="-5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="7.62" x2="-27.94" y2="7.62" width="0.254" layer="94"/>
<text x="-22.86" y="-2.54" size="1.27" layer="94" rot="R90">TQFP144-
only pins</text>
</symbol>
<symbol name="MACHXO2-TQFP144-2000">
<pin name="PR_///7D/10D/15B" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PL_///7A/10A/10A" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PL_///7B/10B/10B" x="10.16" y="2.54" length="middle" rot="R180"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="-7.62" x2="-27.94" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="7.62" x2="-27.94" y2="7.62" width="0.254" layer="94"/>
<text x="-22.86" y="-5.08" size="1.27" layer="94" rot="R90">TQFP144-
only pins</text>
<pin name="PR_///7C/10C/15A" x="10.16" y="-2.54" length="middle" rot="R180"/>
</symbol>
<symbol name="ELLI-SMALL-MACHXO2-ALL">
<description>&lt;h3&gt;ELL-i I/O pins for Lattice MachXO2&lt;/h3&gt;

&lt;p&gt;Generic pins  in the QFN32 package.&lt;/p&gt;</description>
<wire x1="-27.94" y1="15.24" x2="-60.96" y2="15.24" width="0.254" layer="94"/>
<wire x1="-60.96" y1="15.24" x2="-60.96" y2="-15.24" width="0.254" layer="94"/>
<wire x1="-60.96" y1="-15.24" x2="-27.94" y2="-15.24" width="0.254" layer="94"/>
<text x="-58.42" y="12.7" size="1.778" layer="94" align="center-left">LVDS 3T</text>
<text x="-58.42" y="10.16" size="1.778" layer="94" align="center-left">LVDS 3C</text>
<text x="-58.42" y="-2.54" size="1.778" layer="94" align="center-left">LVDS 1T</text>
<text x="-58.42" y="-5.08" size="1.778" layer="94" align="center-left">LVDS 1C</text>
<text x="-58.42" y="-10.16" size="1.778" layer="94" align="center-left">LVDS 2T</text>
<text x="-58.42" y="-12.7" size="1.778" layer="94" align="center-left">LVDS 2C</text>
<text x="-58.42" y="5.08" size="1.778" layer="94" align="center-left">MCO</text>
<text x="-58.42" y="2.54" size="1.778" layer="94" align="center-left">Arduino D8</text>
</symbol>
<symbol name="ELLI-MACHXO2-256-QNF32">
<description>&lt;h3&gt;ELL-i I/O pins for Lattice MachXO2&lt;/h3&gt;

&lt;p&gt;The "QFN32 package" pins for ELL-i when TQFP144 package is used.&lt;/p&gt;</description>
<wire x1="-27.94" y1="15.24" x2="-60.96" y2="15.24" width="0.254" layer="94"/>
<wire x1="-60.96" y1="15.24" x2="-60.96" y2="-15.24" width="0.254" layer="94"/>
<wire x1="-60.96" y1="-15.24" x2="-27.94" y2="-15.24" width="0.254" layer="94"/>
<text x="-58.42" y="12.7" size="1.778" layer="94" align="center-left">DDR2 TBD</text>
<text x="-58.42" y="10.16" size="1.778" layer="94" align="center-left">DDR2 TBD</text>
<text x="-58.42" y="-2.54" size="1.778" layer="94" align="center-left">Memory CLK</text>
<text x="-58.42" y="-5.08" size="1.778" layer="94" align="center-left">Memory NE1</text>
<text x="-58.42" y="-10.16" size="1.778" layer="94" align="center-left">Arduino D5 / JNRST</text>
<text x="-58.42" y="-12.7" size="1.778" layer="94" align="center-left">Arduino D6</text>
<text x="-58.42" y="5.08" size="1.778" layer="94" align="center-left">DDR2 CLK TBD</text>
<text x="-58.42" y="2.54" size="1.778" layer="94" align="center-left">DDR2 CLK TBD</text>
</symbol>
<symbol name="ELLI-MACHXO2-256-LEFT">
<wire x1="-27.94" y1="22.86" x2="-60.96" y2="22.86" width="0.254" layer="94"/>
<wire x1="-60.96" y1="22.86" x2="-60.96" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-60.96" y1="-22.86" x2="-27.94" y2="-22.86" width="0.254" layer="94"/>
<text x="-58.42" y="20.32" size="1.778" layer="94" align="center-left">Memory AD2</text>
<text x="-58.42" y="17.78" size="1.778" layer="94" align="center-left">Memory AD3</text>
<text x="-58.42" y="12.7" size="1.778" layer="94" align="center-left">Memory AD4</text>
<text x="-58.42" y="10.16" size="1.778" layer="94" align="center-left">Memory AD5</text>
<text x="-58.42" y="5.08" size="1.778" layer="94" align="center-left">Memory AD6</text>
<text x="-58.42" y="2.54" size="1.778" layer="94" align="center-left">Memory AD7</text>
<text x="-58.42" y="-2.54" size="1.778" layer="94" align="center-left">Memory AD14</text>
<text x="-58.42" y="-5.08" size="1.778" layer="94" align="center-left">Memory AD15</text>
<text x="-58.42" y="-10.16" size="1.778" layer="94" align="center-left">Memory A18</text>
<text x="-58.42" y="-12.7" size="1.778" layer="94" align="center-left">Memory A19</text>
<text x="-58.42" y="-17.78" size="1.778" layer="94" align="center-left">DDR2 TBD</text>
<text x="-58.42" y="-20.32" size="1.778" layer="94" align="center-left">DDR2 TBD</text>
</symbol>
<symbol name="ELLI-MACHXO2-640-LEFT">
<wire x1="-27.94" y1="12.7" x2="-60.96" y2="12.7" width="0.254" layer="94"/>
<wire x1="-60.96" y1="12.7" x2="-60.96" y2="-10.16" width="0.254" layer="94"/>
<wire x1="-60.96" y1="-10.16" x2="-27.94" y2="-10.16" width="0.254" layer="94"/>
<text x="-58.42" y="10.16" size="1.778" layer="94" align="center-left">Memory AD8</text>
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<description>&lt;h3&gt;ELL-i functions for STM32F Porta D and F&lt;/h3&gt;

&lt;p&gt;STM32F051/030 64-pin TQFP version&lt;/p&gt;</description>
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<wire x1="-30.988" y1="-17.78" x2="-32.0548" y2="-18.288" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-20.32" x2="-32.0548" y2="-19.812" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-20.32" x2="-32.0548" y2="-20.828" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-22.86" x2="-32.0548" y2="-22.352" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-22.86" x2="-32.0548" y2="-23.368" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-25.4" x2="-32.0548" y2="-24.892" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-25.4" x2="-32.0548" y2="-25.908" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-27.94" x2="-32.0548" y2="-27.432" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-27.94" x2="-32.0548" y2="-28.448" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-30.48" x2="-32.0548" y2="-29.972" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-30.48" x2="-32.0548" y2="-30.988" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-33.02" x2="-32.0548" y2="-32.512" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-33.02" x2="-32.0548" y2="-33.528" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-35.56" x2="-32.0548" y2="-35.052" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-35.56" x2="-32.0548" y2="-36.068" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-38.1" x2="-32.0548" y2="-37.592" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-38.1" x2="-32.0548" y2="-38.608" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-40.64" x2="-32.0548" y2="-40.132" width="0.1524" layer="94"/>
<wire x1="-30.988" y1="-40.64" x2="-32.0548" y2="-41.148" width="0.1524" layer="94"/>
<wire x1="30.988" y1="43.18" x2="32.0548" y2="43.688" width="0.1524" layer="94"/>
<wire x1="30.988" y1="43.18" x2="32.0548" y2="42.672" width="0.1524" layer="94"/>
<wire x1="32.5628" y1="43.688" x2="33.6042" y2="43.18" width="0.1524" layer="94"/>
<wire x1="32.5628" y1="42.672" x2="33.6042" y2="43.18" width="0.1524" layer="94"/>
<wire x1="-30.48" y1="58.42" x2="-30.48" y2="-66.04" width="0.1524" layer="94"/>
<wire x1="-30.48" y1="-66.04" x2="30.48" y2="-66.04" width="0.1524" layer="94"/>
<wire x1="30.48" y1="-66.04" x2="30.48" y2="58.42" width="0.1524" layer="94"/>
<wire x1="30.48" y1="58.42" x2="-30.48" y2="58.42" width="0.1524" layer="94"/>
<text x="-4.7244" y="62.4586" size="2.0828" layer="95" ratio="10" rot="SR0">&gt;NAME</text>
<text x="-7.493" y="-70.5866" size="2.0828" layer="96" ratio="10" rot="SR0">&gt;VALUE</text>
</symbol>
<symbol name="FST3257">
<description>Quad 2:1 high-speed CMOS TTL-compatible multiplexer
&lt;h3&gt;Description&lt;/h3&gt;
&lt;p&gt;
The Fairchild Switch FST3257 is a quad 2:1 high-speed CMOS TTL-compatible multiplexer / demultiplexer bus
switch. 
&lt;/p&gt;
&lt;p&gt;
The low on resistance of the switch allows
inputs to be connected to outputs without adding
propagation delay or generating additional ground
bounce noise.
&lt;/p&gt;
&lt;p&gt;
When /OE is LOW, the select pin connects the A port to
the selected B port output. When /OE is HIGH, the
switch is OPEN and a high-impedance state exists
between the two ports.
&lt;/p&gt;
&lt;p&gt;
&lt;a HREF="www.fairchildsemi.com/ds/FS/FST3257.pdf"&gt; Datasheet &lt;/a&gt;
&lt;/p&gt;
&lt;p&gt;
Not reviewed
&lt;/p&gt;</description>
<pin name="1A" x="-15.24" y="10.16" length="middle"/>
<pin name="2B" x="-15.24" y="7.62" length="middle"/>
<pin name="3C" x="-15.24" y="5.08" length="middle"/>
<pin name="4D" x="-15.24" y="2.54" length="middle"/>
<pin name="1A1" x="15.24" y="10.16" length="middle" rot="R180"/>
<pin name="2B1" x="15.24" y="7.62" length="middle" rot="R180"/>
<pin name="3C1" x="15.24" y="5.08" length="middle" rot="R180"/>
<pin name="4D1" x="15.24" y="2.54" length="middle" rot="R180"/>
<pin name="1A0" x="15.24" y="-2.54" length="middle" rot="R180"/>
<pin name="2B0" x="15.24" y="-5.08" length="middle" rot="R180"/>
<pin name="3C0" x="15.24" y="-7.62" length="middle" rot="R180"/>
<pin name="4D0" x="15.24" y="-10.16" length="middle" rot="R180"/>
<pin name="S" x="15.24" y="-15.24" length="middle" direction="in" rot="R180"/>
<pin name="!EN" x="15.24" y="-17.78" length="middle" direction="in" rot="R180"/>
<pin name="GND" x="0" y="-27.94" length="middle" direction="pwr" rot="R90"/>
<pin name="VCC" x="0" y="20.32" length="middle" direction="pwr" rot="R270"/>
<wire x1="-10.16" y1="15.24" x2="10.16" y2="15.24" width="0.254" layer="94"/>
<wire x1="10.16" y1="15.24" x2="10.16" y2="-22.86" width="0.254" layer="94"/>
<wire x1="10.16" y1="-22.86" x2="-10.16" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-10.16" y1="-22.86" x2="-10.16" y2="15.24" width="0.254" layer="94"/>
<text x="2.54" y="19.05" size="1.778" layer="95">&gt;NAME</text>
<text x="2.54" y="-27.94" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="STM32-M-64-LQFP">
<wire x1="-50.8" y1="45.72" x2="50.8" y2="45.72" width="0.254" layer="94"/>
<wire x1="50.8" y1="45.72" x2="50.8" y2="-48.26" width="0.254" layer="94"/>
<wire x1="50.8" y1="-48.26" x2="-50.8" y2="-48.26" width="0.254" layer="94"/>
<wire x1="-50.8" y1="-48.26" x2="-50.8" y2="45.72" width="0.254" layer="94"/>
<text x="-50.8" y="-50.8" size="1.9304" layer="95">&gt;NAME</text>
<text x="-50.8" y="45.72" size="1.9304" layer="95">&gt;VALUE</text>
<pin name="VBAT" x="-55.88" y="43.18" length="middle" direction="sup"/>
<pin name="PC13-TAMPER-RTC" x="-55.88" y="40.64" length="middle"/>
<pin name="PC14-OSC32_IN" x="-55.88" y="38.1" length="middle"/>
<pin name="PC15-OSC32_OUT" x="-55.88" y="35.56" length="middle"/>
<pin name="PD0-OSC_IN-CANRX" x="-55.88" y="33.02" length="middle" direction="in"/>
<pin name="PD1-OSC_OUT-CANTX" x="-55.88" y="30.48" length="middle" direction="out"/>
<pin name="NRST" x="-55.88" y="27.94" length="middle" function="dot"/>
<pin name="VSSA" x="-55.88" y="25.4" length="middle" direction="sup"/>
<pin name="VDDA" x="-55.88" y="22.86" length="middle" direction="sup"/>
<pin name="PA0-WKUP/USART2CTS/ADC0/TIM2CH1ETR" x="-55.88" y="17.78" length="middle"/>
<pin name="PA1-USART2RTS/ADC1/TIM2CH2" x="-55.88" y="15.24" length="middle"/>
<pin name="PA2-USART2TX/ADC2/TIM2CH3" x="-55.88" y="12.7" length="middle"/>
<pin name="PA3-USART2RX/ADC3/TIM2CH4" x="-55.88" y="10.16" length="middle"/>
<pin name="PA4-SPI1NSS/ADC4/USART2CK" x="-55.88" y="7.62" length="middle"/>
<pin name="PA5-SPI1SCK/ADC5" x="-55.88" y="5.08" length="middle"/>
<pin name="PA6-SPI1MISO/ADC6/TIM3CH1-TIM1BKIN" x="-55.88" y="2.54" length="middle"/>
<pin name="PA7-SPI1MOSI/ADC7/TIM3CH2-TIM1CH1N" x="-55.88" y="0" length="middle"/>
<pin name="PB0-ADC8/TIM3CH3-TIM1CH2N" x="55.88" y="43.18" length="middle" rot="R180"/>
<pin name="PB1-ADC9/TIM3CH4-TIM1CH3N" x="55.88" y="40.64" length="middle" rot="R180"/>
<pin name="PB2/BOOT1" x="55.88" y="38.1" length="middle" rot="R180"/>
<pin name="PB10-I2C2SCL/USART3TX-TIM2CH3" x="55.88" y="-12.7" length="middle" rot="R180"/>
<pin name="PB11-I2C2SDA/USART3RX-TIM2CH4" x="55.88" y="-15.24" length="middle" rot="R180"/>
<pin name="VSS1" x="55.88" y="5.08" length="middle" direction="sup" rot="R180"/>
<pin name="VDD1" x="55.88" y="7.62" length="middle" direction="sup" rot="R180"/>
<pin name="PB12-SPI2NSS/I2C2SMBAI/USART3CK/TIM1BKIN" x="55.88" y="-17.78" length="middle" rot="R180"/>
<pin name="PB13-SPI2SCK/USART3CTS/TIM1CH1N" x="55.88" y="-20.32" length="middle" rot="R180"/>
<pin name="PB14-SPI2MISO/USART3RTS/TIM1CH2N" x="55.88" y="-22.86" length="middle" rot="R180"/>
<pin name="PB15-SPI2MOSI/TIM1CH3N" x="55.88" y="-25.4" length="middle" rot="R180"/>
<pin name="PA8-USART1CK/MCO/TIM1CH1" x="-55.88" y="-5.08" length="middle"/>
<pin name="PA9-USART1TX/TIM1CH2" x="-55.88" y="-7.62" length="middle"/>
<pin name="PA10-USART1RX/TIM1CH3" x="-55.88" y="-10.16" length="middle"/>
<pin name="PA11-USART1CTS/CANRX/USBDM/TIM1CH4" x="-55.88" y="-12.7" length="middle"/>
<pin name="PA12-USART1RTS/CANTX/USBDP/TIM1ETR" x="-55.88" y="-15.24" length="middle"/>
<pin name="PA13/JTMS/SWDIO" x="-55.88" y="-17.78" length="middle"/>
<pin name="VSS2" x="55.88" y="2.54" length="middle" direction="sup" rot="R180"/>
<pin name="VDD2" x="55.88" y="10.16" length="middle" direction="sup" rot="R180"/>
<pin name="PA14/JTCK/SWCLK" x="-55.88" y="-20.32" length="middle"/>
<pin name="PA15/JTDI-TIM2CH1ETR/SPI1NSS" x="-55.88" y="-22.86" length="middle"/>
<pin name="PB3/JTDO--TIM2CH2/TRACESWO/SPI1SCK" x="55.88" y="35.56" length="middle" rot="R180"/>
<pin name="PB4/JNTRST--TIM3CH1/SPI1MISO" x="55.88" y="33.02" length="middle" rot="R180"/>
<pin name="PB5-I2C1SMBAI-TIM3CH2/SPI1MOSI" x="55.88" y="30.48" length="middle" rot="R180"/>
<pin name="PB6-I2C1SCL/TIM4CH1-USART1TX" x="55.88" y="27.94" length="middle" rot="R180"/>
<pin name="PB7-I2C1SDA/TIM4CH2-USART1RX" x="55.88" y="25.4" length="middle" rot="R180"/>
<pin name="BOOT0" x="55.88" y="20.32" length="middle" direction="in" rot="R180"/>
<pin name="PB8-TIM4CH3-I2C1SCL/CANRX" x="55.88" y="-7.62" length="middle" rot="R180"/>
<pin name="PB9-TIM4CH4-I2C1SDA/CANTX" x="55.88" y="-10.16" length="middle" rot="R180"/>
<pin name="VSS3" x="55.88" y="0" length="middle" direction="sup" rot="R180"/>
<pin name="VDD3" x="55.88" y="12.7" length="middle" direction="sup" rot="R180"/>
<pin name="PC0-ADC10" x="-55.88" y="-27.94" length="middle"/>
<pin name="PC1-ADC11" x="-55.88" y="-30.48" length="middle"/>
<pin name="PC2-ADC12" x="-55.88" y="-33.02" length="middle"/>
<pin name="PC3-ADC13" x="-55.88" y="-35.56" length="middle"/>
<pin name="PC4-ADC14" x="-55.88" y="-38.1" length="middle"/>
<pin name="PC5-ADC15" x="-55.88" y="-40.64" length="middle"/>
<pin name="PC6-TIM3CH1" x="-55.88" y="-43.18" length="middle"/>
<pin name="PC7-TIM3CH2" x="-55.88" y="-45.72" length="middle"/>
<pin name="PC8-TIM3CH3" x="55.88" y="-30.48" length="middle" rot="R180"/>
<pin name="PC9-TIM3CH4" x="55.88" y="-33.02" length="middle" rot="R180"/>
<pin name="PC10--USART3TX" x="55.88" y="-35.56" length="middle" rot="R180"/>
<pin name="PC11--USART3RX" x="55.88" y="-38.1" length="middle" rot="R180"/>
<pin name="PC12--USART3CK" x="55.88" y="-40.64" length="middle" rot="R180"/>
<pin name="PD2-TIM3ETR" x="55.88" y="-45.72" length="middle" rot="R180"/>
<pin name="VDD4" x="55.88" y="15.24" length="middle" rot="R180"/>
<pin name="VSS4" x="55.88" y="-2.54" length="middle" rot="R180"/>
</symbol>
<symbol name="STM32F1XX-PD-CTL">
<description>&lt;b&gt;STM32F-series MCU control pads&lt;/b&gt;</description>
<wire x1="-10.16" y1="5.08" x2="10.16" y2="5.08" width="0.254" layer="94"/>
<wire x1="10.16" y1="5.08" x2="10.16" y2="-5.08" width="0.254" layer="94"/>
<wire x1="10.16" y1="-5.08" x2="-10.16" y2="-5.08" width="0.254" layer="94"/>
<pin name="PD0" x="-12.7" y="2.54" length="short" direction="in"/>
<pin name="PD1" x="12.7" y="2.54" length="short" direction="out" rot="R180"/>
<pin name="PD2" x="12.7" y="0" length="short" rot="R180"/>
<text x="-9.5" y="5.8" size="1.778" layer="95">&gt;NAME</text>
<text x="-9.26" y="-7.5" size="1.778" layer="96">&gt;VALUE</text>
<wire x1="-10.16" y1="5.08" x2="-10.16" y2="-5.08" width="0.254" layer="94"/>
<pin name="BOOT0" x="-12.7" y="-2.54" length="short" direction="in"/>
<pin name="NRST" x="12.7" y="-2.54" length="short" rot="R180"/>
</symbol>
<symbol name="STM32F1XX-PWR">
<description>&lt;b&gt;STM32F1-series MCU Power pads&lt;/b&gt;</description>
<wire x1="-9.66" y1="15.24" x2="7.62" y2="15.24" width="0.254" layer="94"/>
<wire x1="7.62" y1="15.24" x2="7.62" y2="-15.24" width="0.254" layer="94"/>
<wire x1="7.62" y1="-15.24" x2="-9.66" y2="-15.24" width="0.254" layer="94"/>
<pin name="VBAT" x="10.16" y="12.7" length="short" direction="sup" rot="R180"/>
<pin name="VSSA" x="10.16" y="10.16" length="short" direction="sup" rot="R180"/>
<pin name="VDDA" x="10.16" y="7.62" length="short" direction="sup" rot="R180"/>
<pin name="VDD1" x="10.16" y="5.08" length="short" direction="sup" rot="R180"/>
<pin name="VDD2" x="10.16" y="2.54" length="short" direction="sup" rot="R180"/>
<pin name="VDD3" x="10.16" y="0" length="short" direction="sup" rot="R180"/>
<pin name="VDD4" x="10.16" y="-2.54" length="short" direction="sup" rot="R180"/>
<pin name="VSS1" x="10.16" y="-5.08" length="short" direction="sup" rot="R180"/>
<pin name="VSS2" x="10.16" y="-7.62" length="short" direction="sup" rot="R180"/>
<pin name="VSS3" x="10.16" y="-10.16" length="short" direction="sup" rot="R180"/>
<pin name="VSS4" x="10.16" y="-12.7" length="short" direction="sup" rot="R180"/>
<text x="-9.04" y="16.18" size="1.778" layer="95">&gt;NAME</text>
<text x="-8.84" y="-18.02" size="1.778" layer="96">&gt;VALUE</text>
</symbol>
<symbol name="ENC424J600">
<description>&lt;h3&gt;ENC424J600&lt;/h3&gt;
&lt;p&gt;
The ENC424J600 and ENC624J600 are stand-alone,
Fast Ethernet controllers with an industry standard
Serial Peripheral Interface (SPI) or a flexible parallel
interface. They are designed to serve as an Ethernet
network interface for any microcontroller equipped with
SPI or a standard parallel port.
&lt;/p&gt;
&lt;p&gt;
This is 44 pin version of device, &lt;a href="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf"&gt;Datasheet&lt;/a&gt;
&lt;/p&gt;
&lt;p&gt;
Not reviewed
&lt;/p&gt;</description>
<pin name="VDD" x="-22.86" y="33.02" length="middle" direction="pwr"/>
<pin name="VDDPLL" x="-22.86" y="30.48" length="middle" direction="pwr"/>
<pin name="VDDRX" x="-22.86" y="27.94" length="middle" direction="pwr"/>
<pin name="VDDOSC" x="-22.86" y="25.4" length="middle" direction="pwr"/>
<pin name="VDDTX" x="-22.86" y="22.86" length="middle" direction="pwr"/>
<pin name="RBIAS" x="-22.86" y="15.24" length="middle" direction="in"/>
<pin name="!CS!/CS" x="22.86" y="33.02" length="middle" direction="in" rot="R180"/>
<pin name="SCK/AL" x="22.86" y="30.48" length="middle" direction="in" rot="R180"/>
<pin name="SI/RD/!RW" x="22.86" y="25.4" length="middle" direction="in" rot="R180"/>
<pin name="OSC1" x="22.86" y="15.24" length="middle" direction="in" rot="R180"/>
<pin name="VCAP" x="-22.86" y="20.32" length="middle" direction="pwr"/>
<pin name="TPIN+" x="-22.86" y="7.62" length="middle" direction="in"/>
<pin name="TPIN-" x="-22.86" y="5.08" length="middle" direction="in"/>
<pin name="VSS2" x="-22.86" y="-20.32" length="middle" direction="pwr"/>
<pin name="VSS1" x="-22.86" y="-22.86" length="middle" direction="pwr"/>
<pin name="VSSOSC" x="-22.86" y="-25.4" length="middle" direction="pwr"/>
<pin name="VSSPLL" x="-22.86" y="-27.94" length="middle" direction="pwr"/>
<pin name="VSSTX1" x="-22.86" y="-30.48" length="middle" direction="pwr"/>
<pin name="VSSRX" x="-22.86" y="-33.02" length="middle" direction="pwr"/>
<pin name="VSSTX2" x="-22.86" y="-35.56" length="middle" direction="pwr"/>
<pin name="TPOUT-" x="-22.86" y="-2.54" length="middle" direction="out"/>
<pin name="TPOUT+" x="-22.86" y="0" length="middle" direction="out"/>
<pin name="OSC2" x="22.86" y="12.7" length="middle" direction="out" rot="R180"/>
<pin name="SO/WR/EN" x="22.86" y="27.94" length="middle" rot="R180"/>
<pin name="!INT!/SPISEL" x="22.86" y="22.86" length="middle" rot="R180"/>
<pin name="LEDA" x="22.86" y="-33.02" length="middle" direction="out" rot="R180"/>
<pin name="LEDB" x="22.86" y="-35.56" length="middle" direction="out" rot="R180"/>
<pin name="AD0" x="22.86" y="7.62" length="middle" rot="R180"/>
<pin name="AD1" x="22.86" y="5.08" length="middle" rot="R180"/>
<pin name="AD2" x="22.86" y="2.54" length="middle" rot="R180"/>
<pin name="AD3" x="22.86" y="0" length="middle" rot="R180"/>
<pin name="AD4" x="22.86" y="-2.54" length="middle" rot="R180"/>
<pin name="AD5" x="22.86" y="-5.08" length="middle" rot="R180"/>
<pin name="AD6" x="22.86" y="-7.62" length="middle" rot="R180"/>
<pin name="AD7" x="22.86" y="-10.16" length="middle" rot="R180"/>
<pin name="AD8" x="22.86" y="-12.7" length="middle" rot="R180"/>
<pin name="AD9" x="22.86" y="-15.24" length="middle" rot="R180"/>
<pin name="AD10" x="22.86" y="-17.78" length="middle" rot="R180"/>
<pin name="AD11" x="22.86" y="-20.32" length="middle" rot="R180"/>
<pin name="AD12" x="22.86" y="-22.86" length="middle" rot="R180"/>
<pin name="AD13" x="22.86" y="-25.4" length="middle" rot="R180"/>
<pin name="AD14" x="22.86" y="-27.94" length="middle" rot="R180"/>
<text x="-4.7244" y="37.0586" size="2.0828" layer="95" font="vector" ratio="10" rot="SR0">&gt;NAME</text>
<text x="-4.953" y="-42.6466" size="2.0828" layer="96" font="vector" ratio="10" rot="SR0">&gt;VALUE</text>
<pin name="CLKOUT" x="22.86" y="20.32" length="middle" direction="out" rot="R180"/>
<pin name="PSPCFG0" x="-22.86" y="12.7" length="middle" direction="in"/>
<wire x1="-17.78" y1="-38.1" x2="-17.78" y2="35.56" width="0.254" layer="94"/>
<wire x1="-17.78" y1="35.56" x2="17.78" y2="35.56" width="0.254" layer="94"/>
<wire x1="17.78" y1="35.56" x2="17.78" y2="-38.1" width="0.254" layer="94"/>
<wire x1="17.78" y1="-38.1" x2="-17.78" y2="-38.1" width="0.254" layer="94"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="LAN8720" prefix="U" uservalue="yes">
<description>&lt;h3&gt;Small Footprint RMII 10/100 Ethernet Transceiver&lt;/h3&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf"&gt;Datasheet&lt;/a&gt;&lt;/li&gt;
  &lt;li&gt;Mouser: &lt;a href=""&gt;886-LAN8720AI-CP&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;</description>
<gates>
<gate name="G$1" symbol="LAN8720" x="0" y="0"/>
</gates>
<devices>
<device name="" package="QFN-24_4MM">
<connects>
<connect gate="G$1" pin="CRS_DV" pad="11"/>
<connect gate="G$1" pin="GND" pad="THERM"/>
<connect gate="G$1" pin="LED1/REGOFF" pad="3"/>
<connect gate="G$1" pin="LED2/NINTSEL" pad="2"/>
<connect gate="G$1" pin="MDC" pad="13"/>
<connect gate="G$1" pin="MDIO" pad="12"/>
<connect gate="G$1" pin="NINT/REFCLKO" pad="14"/>
<connect gate="G$1" pin="NRST" pad="15"/>
<connect gate="G$1" pin="RBIAS" pad="24"/>
<connect gate="G$1" pin="RX+" pad="23"/>
<connect gate="G$1" pin="RX-" pad="22"/>
<connect gate="G$1" pin="RXD0" pad="8"/>
<connect gate="G$1" pin="RXD1" pad="7"/>
<connect gate="G$1" pin="RXER" pad="10"/>
<connect gate="G$1" pin="TX+" pad="21"/>
<connect gate="G$1" pin="TX-" pad="20"/>
<connect gate="G$1" pin="TXD0" pad="17"/>
<connect gate="G$1" pin="TXD1" pad="18"/>
<connect gate="G$1" pin="TXEN" pad="16"/>
<connect gate="G$1" pin="VDD1A" pad="19"/>
<connect gate="G$1" pin="VDD2A" pad="1"/>
<connect gate="G$1" pin="VDDCR" pad="6"/>
<connect gate="G$1" pin="VDDIO" pad="9"/>
<connect gate="G$1" pin="XTAL1" pad="5"/>
<connect gate="G$1" pin="XTAL2" pad="4"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
<device name="-H" package="QFN-24_4MM-H">
<connects>
<connect gate="G$1" pin="CRS_DV" pad="11"/>
<connect gate="G$1" pin="GND" pad="THERM"/>
<connect gate="G$1" pin="LED1/REGOFF" pad="3"/>
<connect gate="G$1" pin="LED2/NINTSEL" pad="2"/>
<connect gate="G$1" pin="MDC" pad="13"/>
<connect gate="G$1" pin="MDIO" pad="12"/>
<connect gate="G$1" pin="NINT/REFCLKO" pad="14"/>
<connect gate="G$1" pin="NRST" pad="15"/>
<connect gate="G$1" pin="RBIAS" pad="24"/>
<connect gate="G$1" pin="RX+" pad="23"/>
<connect gate="G$1" pin="RX-" pad="22"/>
<connect gate="G$1" pin="RXD0" pad="8"/>
<connect gate="G$1" pin="RXD1" pad="7"/>
<connect gate="G$1" pin="RXER" pad="10"/>
<connect gate="G$1" pin="TX+" pad="21"/>
<connect gate="G$1" pin="TX-" pad="20"/>
<connect gate="G$1" pin="TXD0" pad="17"/>
<connect gate="G$1" pin="TXD1" pad="18"/>
<connect gate="G$1" pin="TXEN" pad="16"/>
<connect gate="G$1" pin="VDD1A" pad="19"/>
<connect gate="G$1" pin="VDD2A" pad="1"/>
<connect gate="G$1" pin="VDDCR" pad="6"/>
<connect gate="G$1" pin="VDDIO" pad="9"/>
<connect gate="G$1" pin="XTAL1" pad="5"/>
<connect gate="G$1" pin="XTAL2" pad="4"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F429Z" prefix="U">
<description>&lt;h3&gt;STM32F427 / 429 in LQFP144 or WLCSP143 package.&lt;/h3&gt;

&lt;p&gt;STM32F4-series Cortex-M4 microcontroller in a 144 or 143 lead package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf"&gt;Datasheet (DM00071990.pdf)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="PA" symbol="STM32-PA" x="-45.72" y="0"/>
<gate name="PB" symbol="STM32-PB" x="-17.78" y="0"/>
<gate name="PC" symbol="STM32-PC" x="12.7" y="0"/>
<gate name="PD" symbol="STM32-PD" x="33.02" y="0"/>
<gate name="PE" symbol="STM32-PE" x="53.34" y="0"/>
<gate name="PWR" symbol="STM32F4XX-PWR_WITH_BYPASS" x="-38.1" y="-45.72"/>
<gate name="CTL" symbol="STM32F4XX-CTL" x="2.54" y="-45.72"/>
<gate name="PF" symbol="STM32-PF" x="83.82" y="0"/>
<gate name="PG" symbol="STM32-PG" x="101.6" y="0"/>
</gates>
<devices>
<device name="T" package="LQFP144">
<connects>
<connect gate="CTL" pin="BOOT0" pad="138"/>
<connect gate="CTL" pin="NRST" pad="25"/>
<connect gate="CTL" pin="PH0-OSC_IN" pad="23"/>
<connect gate="CTL" pin="PH1-OSC_OUT" pad="24"/>
<connect gate="CTL" pin="VREF+" pad="32"/>
<connect gate="PA" pin="PA0-ADC_IN0" pad="34"/>
<connect gate="PA" pin="PA1-ADC_IN1" pad="35"/>
<connect gate="PA" pin="PA10" pad="102"/>
<connect gate="PA" pin="PA11" pad="103"/>
<connect gate="PA" pin="PA12" pad="104"/>
<connect gate="PA" pin="PA13-SWDIO" pad="105"/>
<connect gate="PA" pin="PA14-SWCLK" pad="109"/>
<connect gate="PA" pin="PA15" pad="110"/>
<connect gate="PA" pin="PA2-ADC_IN2" pad="36"/>
<connect gate="PA" pin="PA3-ADC_IN3" pad="37"/>
<connect gate="PA" pin="PA4-ADC_IN4" pad="40"/>
<connect gate="PA" pin="PA5-ADC_IN5" pad="41"/>
<connect gate="PA" pin="PA6-ADC_IN6" pad="42"/>
<connect gate="PA" pin="PA7-ADC_IN7" pad="43"/>
<connect gate="PA" pin="PA8" pad="100"/>
<connect gate="PA" pin="PA9" pad="101"/>
<connect gate="PB" pin="PB0-ADC_IN8" pad="46"/>
<connect gate="PB" pin="PB1-ADC_IN9" pad="47"/>
<connect gate="PB" pin="PB10" pad="69"/>
<connect gate="PB" pin="PB11" pad="70"/>
<connect gate="PB" pin="PB12" pad="73"/>
<connect gate="PB" pin="PB13" pad="74"/>
<connect gate="PB" pin="PB14" pad="75"/>
<connect gate="PB" pin="PB15" pad="76"/>
<connect gate="PB" pin="PB2" pad="48"/>
<connect gate="PB" pin="PB3" pad="133"/>
<connect gate="PB" pin="PB4" pad="134"/>
<connect gate="PB" pin="PB5" pad="135"/>
<connect gate="PB" pin="PB6" pad="136"/>
<connect gate="PB" pin="PB7" pad="137"/>
<connect gate="PB" pin="PB8" pad="139"/>
<connect gate="PB" pin="PB9" pad="140"/>
<connect gate="PC" pin="PC0-ADC_IN10" pad="26"/>
<connect gate="PC" pin="PC1-ADC_IN11" pad="27"/>
<connect gate="PC" pin="PC10" pad="111"/>
<connect gate="PC" pin="PC11" pad="112"/>
<connect gate="PC" pin="PC12" pad="113"/>
<connect gate="PC" pin="PC13" pad="7"/>
<connect gate="PC" pin="PC14-OSC32_IN" pad="8"/>
<connect gate="PC" pin="PC15-OSC32_OUT" pad="9"/>
<connect gate="PC" pin="PC2-ADC_IN12" pad="28"/>
<connect gate="PC" pin="PC3-ADC_IN13" pad="29"/>
<connect gate="PC" pin="PC4-ADC_IN14" pad="44"/>
<connect gate="PC" pin="PC5-ADC_IN15" pad="45"/>
<connect gate="PC" pin="PC6" pad="96"/>
<connect gate="PC" pin="PC7" pad="97"/>
<connect gate="PC" pin="PC8" pad="98"/>
<connect gate="PC" pin="PC9" pad="99"/>
<connect gate="PD" pin="PD0" pad="114"/>
<connect gate="PD" pin="PD1" pad="115"/>
<connect gate="PD" pin="PD10" pad="79"/>
<connect gate="PD" pin="PD11" pad="80"/>
<connect gate="PD" pin="PD12" pad="81"/>
<connect gate="PD" pin="PD13" pad="82"/>
<connect gate="PD" pin="PD14" pad="85"/>
<connect gate="PD" pin="PD15" pad="86"/>
<connect gate="PD" pin="PD2" pad="116"/>
<connect gate="PD" pin="PD3" pad="117"/>
<connect gate="PD" pin="PD4" pad="118"/>
<connect gate="PD" pin="PD5" pad="119"/>
<connect gate="PD" pin="PD6" pad="122"/>
<connect gate="PD" pin="PD7" pad="123"/>
<connect gate="PD" pin="PD8" pad="77"/>
<connect gate="PD" pin="PD9" pad="78"/>
<connect gate="PE" pin="PE0" pad="141"/>
<connect gate="PE" pin="PE1" pad="142"/>
<connect gate="PE" pin="PE10" pad="63"/>
<connect gate="PE" pin="PE11" pad="64"/>
<connect gate="PE" pin="PE12" pad="65"/>
<connect gate="PE" pin="PE13" pad="66"/>
<connect gate="PE" pin="PE14" pad="67"/>
<connect gate="PE" pin="PE15" pad="68"/>
<connect gate="PE" pin="PE2" pad="1"/>
<connect gate="PE" pin="PE3" pad="2"/>
<connect gate="PE" pin="PE4" pad="3"/>
<connect gate="PE" pin="PE5" pad="4"/>
<connect gate="PE" pin="PE6" pad="5"/>
<connect gate="PE" pin="PE7" pad="58"/>
<connect gate="PE" pin="PE8" pad="59"/>
<connect gate="PE" pin="PE9" pad="60"/>
<connect gate="PF" pin="PF0" pad="10"/>
<connect gate="PF" pin="PF1" pad="11"/>
<connect gate="PF" pin="PF10" pad="22"/>
<connect gate="PF" pin="PF11" pad="49"/>
<connect gate="PF" pin="PF12" pad="50"/>
<connect gate="PF" pin="PF13" pad="53"/>
<connect gate="PF" pin="PF14" pad="54"/>
<connect gate="PF" pin="PF15" pad="55"/>
<connect gate="PF" pin="PF2" pad="12"/>
<connect gate="PF" pin="PF3" pad="13"/>
<connect gate="PF" pin="PF4" pad="14"/>
<connect gate="PF" pin="PF5" pad="15"/>
<connect gate="PF" pin="PF6" pad="18"/>
<connect gate="PF" pin="PF7" pad="19"/>
<connect gate="PF" pin="PF8" pad="20"/>
<connect gate="PF" pin="PF9" pad="21"/>
<connect gate="PG" pin="PG0" pad="56"/>
<connect gate="PG" pin="PG1" pad="57"/>
<connect gate="PG" pin="PG10" pad="125"/>
<connect gate="PG" pin="PG11" pad="126"/>
<connect gate="PG" pin="PG12" pad="127"/>
<connect gate="PG" pin="PG13" pad="128"/>
<connect gate="PG" pin="PG14" pad="129"/>
<connect gate="PG" pin="PG15" pad="132"/>
<connect gate="PG" pin="PG2" pad="87"/>
<connect gate="PG" pin="PG3" pad="88"/>
<connect gate="PG" pin="PG4" pad="89"/>
<connect gate="PG" pin="PG5" pad="90"/>
<connect gate="PG" pin="PG6" pad="91"/>
<connect gate="PG" pin="PG7" pad="92"/>
<connect gate="PG" pin="PG8" pad="93"/>
<connect gate="PG" pin="PG9" pad="124"/>
<connect gate="PWR" pin="BYPASS_REG" pad="NC"/>
<connect gate="PWR" pin="PDR_ON" pad="143"/>
<connect gate="PWR" pin="VBAT" pad="6" route="any"/>
<connect gate="PWR" pin="VCAP1" pad="71"/>
<connect gate="PWR" pin="VCAP2" pad="106"/>
<connect gate="PWR" pin="VDD" pad="17 30 39 52 62 72 84 95 108 121 131 144"/>
<connect gate="PWR" pin="VDDA" pad="33"/>
<connect gate="PWR" pin="VSS" pad="16 38 51 61 83 94 107 120 130"/>
<connect gate="PWR" pin="VSSA" pad="31"/>
</connects>
<technologies>
<technology name="G">
<attribute name="FLASH" value="1024K"/>
</technology>
<technology name="I">
<attribute name="FLASH" value="2048K"/>
</technology>
</technologies>
</device>
<device name="Y" package="WLCSP143">
<connects>
<connect gate="CTL" pin="BOOT0" pad="C9"/>
<connect gate="CTL" pin="NRST" pad="H9"/>
<connect gate="CTL" pin="PH0-OSC_IN" pad="J11"/>
<connect gate="CTL" pin="PH1-OSC_OUT" pad="H10"/>
<connect gate="CTL" pin="VREF+" pad="L11"/>
<connect gate="PA" pin="PA0-ADC_IN0" pad="K9"/>
<connect gate="PA" pin="PA1-ADC_IN1" pad="K8"/>
<connect gate="PA" pin="PA10" pad="D5"/>
<connect gate="PA" pin="PA11" pad="D4"/>
<connect gate="PA" pin="PA12" pad="E1"/>
<connect gate="PA" pin="PA13-SWDIO" pad="D3"/>
<connect gate="PA" pin="PA14-SWCLK" pad="B1"/>
<connect gate="PA" pin="PA15" pad="C2"/>
<connect gate="PA" pin="PA2-ADC_IN2" pad="L9"/>
<connect gate="PA" pin="PA3-ADC_IN3" pad="M11"/>
<connect gate="PA" pin="PA4-ADC_IN4" pad="M10"/>
<connect gate="PA" pin="PA5-ADC_IN5" pad="M9"/>
<connect gate="PA" pin="PA6-ADC_IN6" pad="N10"/>
<connect gate="PA" pin="PA7-ADC_IN7" pad="L8"/>
<connect gate="PA" pin="PA8" pad="F1"/>
<connect gate="PA" pin="PA9" pad="E2"/>
<connect gate="PB" pin="PB0-ADC_IN8" pad="N8"/>
<connect gate="PB" pin="PB1-ADC_IN9" pad="K7"/>
<connect gate="PB" pin="PB10" pad="M3"/>
<connect gate="PB" pin="PB11" pad="N3"/>
<connect gate="PB" pin="PB12" pad="M2"/>
<connect gate="PB" pin="PB13" pad="N1"/>
<connect gate="PB" pin="PB14" pad="K3"/>
<connect gate="PB" pin="PB15" pad="J3"/>
<connect gate="PB" pin="PB2" pad="L7"/>
<connect gate="PB" pin="PB3" pad="B7"/>
<connect gate="PB" pin="PB4" pad="C7"/>
<connect gate="PB" pin="PB5" pad="C8"/>
<connect gate="PB" pin="PB6" pad="A8"/>
<connect gate="PB" pin="PB7" pad="B8"/>
<connect gate="PB" pin="PB8" pad="A9"/>
<connect gate="PB" pin="PB9" pad="B9"/>
<connect gate="PC" pin="PC0-ADC_IN10" pad="H8"/>
<connect gate="PC" pin="PC1-ADC_IN11" pad="K11"/>
<connect gate="PC" pin="PC10" pad="A2"/>
<connect gate="PC" pin="PC11" pad="B2"/>
<connect gate="PC" pin="PC12" pad="C3"/>
<connect gate="PC" pin="PC13" pad="D10"/>
<connect gate="PC" pin="PC14-OSC32_IN" pad="D11"/>
<connect gate="PC" pin="PC15-OSC32_OUT" pad="E11"/>
<connect gate="PC" pin="PC2-ADC_IN12" pad="J10"/>
<connect gate="PC" pin="PC3-ADC_IN13" pad="J9"/>
<connect gate="PC" pin="PC4-ADC_IN14" pad="M8"/>
<connect gate="PC" pin="PC5-ADC_IN15" pad="N9"/>
<connect gate="PC" pin="PC6" pad="F2"/>
<connect gate="PC" pin="PC7" pad="F3"/>
<connect gate="PC" pin="PC8" pad="E4"/>
<connect gate="PC" pin="PC9" pad="E3"/>
<connect gate="PD" pin="PD0" pad="B3"/>
<connect gate="PD" pin="PD1" pad="C4"/>
<connect gate="PD" pin="PD10" pad="H4"/>
<connect gate="PD" pin="PD11" pad="K2"/>
<connect gate="PD" pin="PD12" pad="H6"/>
<connect gate="PD" pin="PD13" pad="H5"/>
<connect gate="PD" pin="PD14" pad="J2"/>
<connect gate="PD" pin="PD15" pad="K1"/>
<connect gate="PD" pin="PD2" pad="A3"/>
<connect gate="PD" pin="PD3" pad="B4"/>
<connect gate="PD" pin="PD4" pad="B5"/>
<connect gate="PD" pin="PD5" pad="A4"/>
<connect gate="PD" pin="PD6" pad="F4"/>
<connect gate="PD" pin="PD7" pad="A5"/>
<connect gate="PD" pin="PD8" pad="L2"/>
<connect gate="PD" pin="PD9" pad="M1"/>
<connect gate="PE" pin="PE0" pad="B10"/>
<connect gate="PE" pin="PE1" pad="A10"/>
<connect gate="PE" pin="PE10" pad="J4"/>
<connect gate="PE" pin="PE11" pad="K4"/>
<connect gate="PE" pin="PE12" pad="L4"/>
<connect gate="PE" pin="PE13" pad="N4"/>
<connect gate="PE" pin="PE14" pad="M4"/>
<connect gate="PE" pin="PE15" pad="L3"/>
<connect gate="PE" pin="PE2" pad="D8"/>
<connect gate="PE" pin="PE3" pad="C10"/>
<connect gate="PE" pin="PE4" pad="B11"/>
<connect gate="PE" pin="PE5" pad="D9"/>
<connect gate="PE" pin="PE6" pad="E8"/>
<connect gate="PE" pin="PE7" pad="L5"/>
<connect gate="PE" pin="PE8" pad="M5"/>
<connect gate="PE" pin="PE9" pad="N5"/>
<connect gate="PF" pin="PF0" pad="F11"/>
<connect gate="PF" pin="PF1" pad="E9"/>
<connect gate="PF" pin="PF10" pad="G9"/>
<connect gate="PF" pin="PF11" pad="M7"/>
<connect gate="PF" pin="PF12" pad="N7"/>
<connect gate="PF" pin="PF13" pad="K6"/>
<connect gate="PF" pin="PF14" pad="L6"/>
<connect gate="PF" pin="PF15" pad="M6"/>
<connect gate="PF" pin="PF2" pad="F10"/>
<connect gate="PF" pin="PF3" pad="G11"/>
<connect gate="PF" pin="PF4" pad="F9"/>
<connect gate="PF" pin="PF5" pad="F8"/>
<connect gate="PF" pin="PF6" pad="G10"/>
<connect gate="PF" pin="PF7" pad="F7"/>
<connect gate="PF" pin="PF8" pad="H11"/>
<connect gate="PF" pin="PF9" pad="G8"/>
<connect gate="PG" pin="PG0" pad="N6"/>
<connect gate="PG" pin="PG1" pad="K5"/>
<connect gate="PG" pin="PG10" pad="C6"/>
<connect gate="PG" pin="PG11" pad="B6"/>
<connect gate="PG" pin="PG12" pad="A6"/>
<connect gate="PG" pin="PG13" pad="D6"/>
<connect gate="PG" pin="PG14" pad="F6"/>
<connect gate="PG" pin="PG15" pad="A7"/>
<connect gate="PG" pin="PG2" pad="J1"/>
<connect gate="PG" pin="PG3" pad="G3"/>
<connect gate="PG" pin="PG4" pad="G5"/>
<connect gate="PG" pin="PG5" pad="G6"/>
<connect gate="PG" pin="PG6" pad="G4"/>
<connect gate="PG" pin="PG7" pad="H1"/>
<connect gate="PG" pin="PG8" pad="G2"/>
<connect gate="PG" pin="PG9" pad="E5"/>
<connect gate="PWR" pin="BYPASS_REG" pad="N11"/>
<connect gate="PWR" pin="PDR_ON" pad="A11"/>
<connect gate="PWR" pin="VBAT" pad="C11"/>
<connect gate="PWR" pin="VCAP1" pad="N2"/>
<connect gate="PWR" pin="VCAP2" pad="D1"/>
<connect gate="PWR" pin="VDD" pad="A1 C1 C5 D7 E6 E10 G1 G7 J5 J6 J7 J8 L1" route="any"/>
<connect gate="PWR" pin="VDDA" pad="L10"/>
<connect gate="PWR" pin="VSS" pad="D2 E7 F5 H2 H3 H7"/>
<connect gate="PWR" pin="VSSA" pad="K10"/>
</connects>
<technologies>
<technology name="G"/>
<technology name="I"/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F429V" prefix="U">
<description>&lt;h3&gt;STM32F427 / 429 in LQFP100 package.&lt;/h3&gt;

&lt;p&gt;STM32F4-series Cortex-M4 microcontroller in a 100 lead package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00071990.pdf"&gt;Datasheet (DM00071990.pdf)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="PA" symbol="STM32-PA" x="-45.72" y="0"/>
<gate name="PB" symbol="STM32-PB" x="-17.78" y="0"/>
<gate name="PC" symbol="STM32-PC" x="12.7" y="0"/>
<gate name="PD" symbol="STM32-PD" x="33.02" y="0"/>
<gate name="PE" symbol="STM32-PE" x="53.34" y="0"/>
<gate name="PWR" symbol="STM32FXXX-PWR" x="-38.1" y="-45.72"/>
<gate name="CTL" symbol="STM32F4XX-CTL" x="5.08" y="-45.72"/>
</gates>
<devices>
<device name="T" package="LQFP100">
<connects>
<connect gate="CTL" pin="BOOT0" pad="94"/>
<connect gate="CTL" pin="NRST" pad="14"/>
<connect gate="CTL" pin="PH0-OSC_IN" pad="12"/>
<connect gate="CTL" pin="PH1-OSC_OUT" pad="13"/>
<connect gate="CTL" pin="VREF+" pad="21"/>
<connect gate="PA" pin="PA0-ADC_IN0" pad="23"/>
<connect gate="PA" pin="PA1-ADC_IN1" pad="24"/>
<connect gate="PA" pin="PA10" pad="69"/>
<connect gate="PA" pin="PA11" pad="70"/>
<connect gate="PA" pin="PA12" pad="71"/>
<connect gate="PA" pin="PA13-SWDIO" pad="72"/>
<connect gate="PA" pin="PA14-SWCLK" pad="76"/>
<connect gate="PA" pin="PA15" pad="77"/>
<connect gate="PA" pin="PA2-ADC_IN2" pad="25"/>
<connect gate="PA" pin="PA3-ADC_IN3" pad="26"/>
<connect gate="PA" pin="PA4-ADC_IN4" pad="29"/>
<connect gate="PA" pin="PA5-ADC_IN5" pad="30"/>
<connect gate="PA" pin="PA6-ADC_IN6" pad="31"/>
<connect gate="PA" pin="PA7-ADC_IN7" pad="32"/>
<connect gate="PA" pin="PA8" pad="67"/>
<connect gate="PA" pin="PA9" pad="68"/>
<connect gate="PB" pin="PB0-ADC_IN8" pad="35"/>
<connect gate="PB" pin="PB1-ADC_IN9" pad="36"/>
<connect gate="PB" pin="PB10" pad="47"/>
<connect gate="PB" pin="PB11" pad="48"/>
<connect gate="PB" pin="PB12" pad="51"/>
<connect gate="PB" pin="PB13" pad="52"/>
<connect gate="PB" pin="PB14" pad="53"/>
<connect gate="PB" pin="PB15" pad="54"/>
<connect gate="PB" pin="PB2" pad="37"/>
<connect gate="PB" pin="PB3" pad="89"/>
<connect gate="PB" pin="PB4" pad="90"/>
<connect gate="PB" pin="PB5" pad="91"/>
<connect gate="PB" pin="PB6" pad="92"/>
<connect gate="PB" pin="PB7" pad="93"/>
<connect gate="PB" pin="PB8" pad="95"/>
<connect gate="PB" pin="PB9" pad="96"/>
<connect gate="PC" pin="PC0-ADC_IN10" pad="15"/>
<connect gate="PC" pin="PC1-ADC_IN11" pad="16"/>
<connect gate="PC" pin="PC10" pad="78"/>
<connect gate="PC" pin="PC11" pad="79"/>
<connect gate="PC" pin="PC12" pad="80"/>
<connect gate="PC" pin="PC13" pad="7"/>
<connect gate="PC" pin="PC14-OSC32_IN" pad="8"/>
<connect gate="PC" pin="PC15-OSC32_OUT" pad="9"/>
<connect gate="PC" pin="PC2-ADC_IN12" pad="17"/>
<connect gate="PC" pin="PC3-ADC_IN13" pad="18"/>
<connect gate="PC" pin="PC4-ADC_IN14" pad="33"/>
<connect gate="PC" pin="PC5-ADC_IN15" pad="34"/>
<connect gate="PC" pin="PC6" pad="63"/>
<connect gate="PC" pin="PC7" pad="64"/>
<connect gate="PC" pin="PC8" pad="65"/>
<connect gate="PC" pin="PC9" pad="66"/>
<connect gate="PD" pin="PD0" pad="81"/>
<connect gate="PD" pin="PD1" pad="82"/>
<connect gate="PD" pin="PD10" pad="57"/>
<connect gate="PD" pin="PD11" pad="58"/>
<connect gate="PD" pin="PD12" pad="59"/>
<connect gate="PD" pin="PD13" pad="60"/>
<connect gate="PD" pin="PD14" pad="61"/>
<connect gate="PD" pin="PD15" pad="62"/>
<connect gate="PD" pin="PD2" pad="83"/>
<connect gate="PD" pin="PD3" pad="84"/>
<connect gate="PD" pin="PD4" pad="85"/>
<connect gate="PD" pin="PD5" pad="86"/>
<connect gate="PD" pin="PD6" pad="87"/>
<connect gate="PD" pin="PD7" pad="88"/>
<connect gate="PD" pin="PD8" pad="55"/>
<connect gate="PD" pin="PD9" pad="56"/>
<connect gate="PE" pin="PE0" pad="97"/>
<connect gate="PE" pin="PE1" pad="98"/>
<connect gate="PE" pin="PE10" pad="41"/>
<connect gate="PE" pin="PE11" pad="42"/>
<connect gate="PE" pin="PE12" pad="43"/>
<connect gate="PE" pin="PE13" pad="44"/>
<connect gate="PE" pin="PE14" pad="45"/>
<connect gate="PE" pin="PE15" pad="46"/>
<connect gate="PE" pin="PE2" pad="1"/>
<connect gate="PE" pin="PE3" pad="2"/>
<connect gate="PE" pin="PE4" pad="3"/>
<connect gate="PE" pin="PE5" pad="4"/>
<connect gate="PE" pin="PE6" pad="5"/>
<connect gate="PE" pin="PE7" pad="38"/>
<connect gate="PE" pin="PE8" pad="39"/>
<connect gate="PE" pin="PE9" pad="40"/>
<connect gate="PWR" pin="VBAT" pad="6"/>
<connect gate="PWR" pin="VDD" pad="11 19 28 50 75 100"/>
<connect gate="PWR" pin="VDDA" pad="22"/>
<connect gate="PWR" pin="VSS" pad="10 27 74 99"/>
<connect gate="PWR" pin="VSSA" pad="20"/>
</connects>
<technologies>
<technology name="G">
<attribute name="FLASH" value="1024K"/>
</technology>
<technology name="I">
<attribute name="FLASH" value="2048K"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F051C" prefix="U">
<description>&lt;h3&gt;STM32F051 in LQPF48 package.&lt;/h3&gt;

&lt;p&gt;STM32F0-series Cortex-M0 microcontroller in a 48 lead package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf"&gt;Datasheet&lt;/a&gt; (DM00039193.pdf)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="PA" symbol="STM32-PA" x="-30.48" y="20.32"/>
<gate name="PB" symbol="STM32-PB" x="5.08" y="20.32"/>
<gate name="PWR" symbol="STM32FXXX-PWR" x="-35.56" y="-22.86"/>
<gate name="CTL" symbol="STM32F0XX-CTL" x="0" y="-22.86"/>
</gates>
<devices>
<device name="T" package="LQFP48">
<connects>
<connect gate="CTL" pin="BOOT0" pad="44"/>
<connect gate="CTL" pin="NRST" pad="7"/>
<connect gate="CTL" pin="PF0-OSC_IN" pad="5"/>
<connect gate="CTL" pin="PF1-OSC_OUT" pad="6"/>
<connect gate="PA" pin="PA0-ADC_IN0" pad="10"/>
<connect gate="PA" pin="PA1-ADC_IN1" pad="11"/>
<connect gate="PA" pin="PA10" pad="31"/>
<connect gate="PA" pin="PA11" pad="32"/>
<connect gate="PA" pin="PA12" pad="33"/>
<connect gate="PA" pin="PA13-SWDIO" pad="34"/>
<connect gate="PA" pin="PA14-SWCLK" pad="37"/>
<connect gate="PA" pin="PA15" pad="38"/>
<connect gate="PA" pin="PA2-ADC_IN2" pad="12"/>
<connect gate="PA" pin="PA3-ADC_IN3" pad="13"/>
<connect gate="PA" pin="PA4-ADC_IN4" pad="14"/>
<connect gate="PA" pin="PA5-ADC_IN5" pad="15"/>
<connect gate="PA" pin="PA6-ADC_IN6" pad="16"/>
<connect gate="PA" pin="PA7-ADC_IN7" pad="17"/>
<connect gate="PA" pin="PA8" pad="29"/>
<connect gate="PA" pin="PA9" pad="30"/>
<connect gate="PB" pin="PB0-ADC_IN8" pad="18"/>
<connect gate="PB" pin="PB1-ADC_IN9" pad="19"/>
<connect gate="PB" pin="PB10" pad="21"/>
<connect gate="PB" pin="PB11" pad="22"/>
<connect gate="PB" pin="PB12" pad="25"/>
<connect gate="PB" pin="PB13" pad="26"/>
<connect gate="PB" pin="PB14" pad="27"/>
<connect gate="PB" pin="PB15" pad="28"/>
<connect gate="PB" pin="PB2" pad="20"/>
<connect gate="PB" pin="PB3" pad="39"/>
<connect gate="PB" pin="PB4" pad="40"/>
<connect gate="PB" pin="PB5" pad="41"/>
<connect gate="PB" pin="PB6" pad="42"/>
<connect gate="PB" pin="PB7" pad="43"/>
<connect gate="PB" pin="PB8" pad="45"/>
<connect gate="PB" pin="PB9" pad="46"/>
<connect gate="PWR" pin="VBAT" pad="1"/>
<connect gate="PWR" pin="VDD" pad="24 48"/>
<connect gate="PWR" pin="VDDA" pad="9"/>
<connect gate="PWR" pin="VSS" pad="23 47"/>
<connect gate="PWR" pin="VSSA" pad="8"/>
</connects>
<technologies>
<technology name="4">
<attribute name="FLASH" value="16K" constant="no"/>
</technology>
<technology name="6">
<attribute name="FLASH" value="32K"/>
</technology>
<technology name="8">
<attribute name="FLASH" value="64K"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F051R" prefix="U">
<description>&lt;h3&gt;STM32F051 in LQPF64 package.&lt;/h3&gt;

&lt;p&gt;STM32F0-series Cortex-M0 microcontroller in 64 lead package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.st.com/web/en/resource/technical/document/datasheet/DM00039193.pdf"&gt;Datasheet&lt;/a&gt; (DM00039193.pdf)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="PA" symbol="STM32-PA" x="-50.8" y="20.32"/>
<gate name="PB" symbol="STM32-PB" x="-12.7" y="20.32"/>
<gate name="PC" symbol="STM32-PC" x="25.4" y="20.32"/>
<gate name="PWR" symbol="STM32FXXX-PWR" x="-35.56" y="-22.86"/>
<gate name="CTL" symbol="STM32F0XX-CTL" x="0" y="-22.86"/>
<gate name="PDF" symbol="STM32-PDF-LQFP64" x="22.86" y="-22.86"/>
</gates>
<devices>
<device name="T" package="LQFP64">
<connects>
<connect gate="CTL" pin="BOOT0" pad="60"/>
<connect gate="CTL" pin="NRST" pad="7"/>
<connect gate="CTL" pin="PF0-OSC_IN" pad="5"/>
<connect gate="CTL" pin="PF1-OSC_OUT" pad="6"/>
<connect gate="PA" pin="PA0-ADC_IN0" pad="14"/>
<connect gate="PA" pin="PA1-ADC_IN1" pad="15"/>
<connect gate="PA" pin="PA10" pad="43"/>
<connect gate="PA" pin="PA11" pad="44"/>
<connect gate="PA" pin="PA12" pad="45"/>
<connect gate="PA" pin="PA13-SWDIO" pad="46"/>
<connect gate="PA" pin="PA14-SWCLK" pad="49"/>
<connect gate="PA" pin="PA15" pad="50"/>
<connect gate="PA" pin="PA2-ADC_IN2" pad="16"/>
<connect gate="PA" pin="PA3-ADC_IN3" pad="17"/>
<connect gate="PA" pin="PA4-ADC_IN4" pad="20"/>
<connect gate="PA" pin="PA5-ADC_IN5" pad="21"/>
<connect gate="PA" pin="PA6-ADC_IN6" pad="22"/>
<connect gate="PA" pin="PA7-ADC_IN7" pad="23"/>
<connect gate="PA" pin="PA8" pad="41"/>
<connect gate="PA" pin="PA9" pad="42"/>
<connect gate="PB" pin="PB0-ADC_IN8" pad="26"/>
<connect gate="PB" pin="PB1-ADC_IN9" pad="27"/>
<connect gate="PB" pin="PB10" pad="29"/>
<connect gate="PB" pin="PB11" pad="30"/>
<connect gate="PB" pin="PB12" pad="33"/>
<connect gate="PB" pin="PB13" pad="34"/>
<connect gate="PB" pin="PB14" pad="35"/>
<connect gate="PB" pin="PB15" pad="36"/>
<connect gate="PB" pin="PB2" pad="28"/>
<connect gate="PB" pin="PB3" pad="55"/>
<connect gate="PB" pin="PB4" pad="56"/>
<connect gate="PB" pin="PB5" pad="57"/>
<connect gate="PB" pin="PB6" pad="58"/>
<connect gate="PB" pin="PB7" pad="59"/>
<connect gate="PB" pin="PB8" pad="61"/>
<connect gate="PB" pin="PB9" pad="62"/>
<connect gate="PC" pin="PC0-ADC_IN10" pad="8"/>
<connect gate="PC" pin="PC1-ADC_IN11" pad="9"/>
<connect gate="PC" pin="PC10" pad="51"/>
<connect gate="PC" pin="PC11" pad="52"/>
<connect gate="PC" pin="PC12" pad="53"/>
<connect gate="PC" pin="PC13" pad="2"/>
<connect gate="PC" pin="PC14-OSC32_IN" pad="3"/>
<connect gate="PC" pin="PC15-OSC32_OUT" pad="4"/>
<connect gate="PC" pin="PC2-ADC_IN12" pad="10"/>
<connect gate="PC" pin="PC3-ADC_IN13" pad="11"/>
<connect gate="PC" pin="PC4-ADC_IN14" pad="24"/>
<connect gate="PC" pin="PC5-ADC_IN15" pad="25"/>
<connect gate="PC" pin="PC6" pad="37"/>
<connect gate="PC" pin="PC7" pad="38"/>
<connect gate="PC" pin="PC8" pad="39"/>
<connect gate="PC" pin="PC9" pad="40"/>
<connect gate="PDF" pin="PD2" pad="54"/>
<connect gate="PDF" pin="PF4" pad="18"/>
<connect gate="PDF" pin="PF5" pad="19"/>
<connect gate="PDF" pin="PF6" pad="47"/>
<connect gate="PDF" pin="PF7" pad="48"/>
<connect gate="PWR" pin="VBAT" pad="1"/>
<connect gate="PWR" pin="VDD" pad="32 64"/>
<connect gate="PWR" pin="VDDA" pad="13"/>
<connect gate="PWR" pin="VSS" pad="31 63"/>
<connect gate="PWR" pin="VSSA" pad="12"/>
</connects>
<technologies>
<technology name="4">
<attribute name="FLASH" value="16K"/>
</technology>
<technology name="6">
<attribute name="FLASH" value="32K"/>
</technology>
<technology name="8">
<attribute name="FLASH" value="64K"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LCMXO2-256*" prefix="U">
<description>&lt;h3&gt; MachXO2-256 in csBGA132 or TQFP144 package.&lt;/h3&gt;

&lt;p&gt;Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf"&gt;Datasheet&lt;/a&gt; (DS1035)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="MACHXO2-PWR" symbol="MACHXO2-CSBGA132-PWR" x="-20.32" y="73.66"/>
<gate name="MACHXO2-ERB" symbol="MACHXO2-ERB" x="88.9" y="68.58"/>
<gate name="MACHXO2-CSBGA132-256-TOP" symbol="MACHXO2-CSBGA132-256-TOP" x="45.72" y="27.94"/>
<gate name="MACHXO2-CSBA132-256-LEFT" symbol="MACHXO2-CSBGA132-256-LEFT" x="-7.62" y="5.08"/>
<gate name="MACHXO2-CSBGA132-256-RIGHT" symbol="MACHXO2-CSBGA132-256-RIGHT" x="101.6" y="0"/>
<gate name="MACHXO2-CSBGA132-256-BOTTOM" symbol="MACHXO2-CSBGA132-256-BOTTOM" x="45.72" y="-27.94"/>
<gate name="MACHXO2-QNF32-256" symbol="MACHXO2-QFN32-256" x="45.72" y="0"/>
</gates>
<devices>
<device name="MG132" package="CSBGA132-MACHXO2">
<connects>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_2A/2A/2C/2A/4A" pad="C1"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_2B/2B/2D/2B/4B" pad="C3"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_2C/2C/3A/3A/6A" pad="C2"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_2D/2D/3B/3B/6B" pad="D1"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_3A/3A/3C/4A/7A" pad="E1"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_3B/3B/3D/4B/7B" pad="E2"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_3C/5A/5A/7C/10C" pad="G3"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_3D/5B/5B/7D/10D" pad="H2"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_5A/6A/8A/10A/14A" pad="J1"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_5B/6B/8B/10B/14B" pad="J2"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_6A/7C/10C/14A/20A" pad="M1"/>
<connect gate="MACHXO2-CSBA132-256-LEFT" pin="PL_6B/7D/10D/14B/20B" pad="M2"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7A/12A/15A/18A/21A" pad="P8"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7B/12B/15B/18B/21B" pad="M8"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7C/12C/18A/21A/24A" pad="M9"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7D/12D/18B/21B/24B" pad="N10"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2A/2A/2A/1A/2A" pad="B14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2B/2B/2B/1B/2B" pad="C13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3A/2C/3A/3A/5A" pad="E12"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3B/2D/3B/3B/5B" pad="E14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3C/3C/4C/5A/8A" pad="F13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3D/3D/4D/5B/8B" pad="F14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5C/6C/9A/11A/15A" pad="K13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5D/6D/9B/11B/15B" pad="K14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6A/7A/9C/12A/16A" pad="L14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6B/7B/9D/12B/16B" pad="M13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6C/7C/10C/14A/19A" pad="N13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6D/7D/10D/14B/19B" pad="N14"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6A/6A/9A/9A/9A" pad="A2"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6B/6B/9B/9B/9B" pad="B3"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8A/9A/12A/17A/18A" pad="A7"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8B/9B/12B/17B/18B" pad="B7"/>
<connect gate="MACHXO2-ERB" pin="CSSPIN/PB_2A..." pad="P3"/>
<connect gate="MACHXO2-ERB" pin="DONE/PT17D" pad="A13"/>
<connect gate="MACHXO2-ERB" pin="INITN/PT17C" pad="B13"/>
<connect gate="MACHXO2-ERB" pin="JTAGENB/PT15C" pad="B9"/>
<connect gate="MACHXO2-ERB" pin="MCLK/CCLK/PB6C" pad="M4"/>
<connect gate="MACHXO2-ERB" pin="PB_2B/4B/4D/5B/4B" pad="M3"/>
<connect gate="MACHXO2-ERB" pin="PROGRAMN/PT15D" pad="C10"/>
<connect gate="MACHXO2-ERB" pin="SCL/PT12C" pad="C8"/>
<connect gate="MACHXO2-ERB" pin="SDA/PT12D" pad="B8"/>
<connect gate="MACHXO2-ERB" pin="SISPI/PB20D" pad="P13"/>
<connect gate="MACHXO2-ERB" pin="SN/PB20C" pad="N12"/>
<connect gate="MACHXO2-ERB" pin="SPISO/PB6D" pad="N4"/>
<connect gate="MACHXO2-ERB" pin="TCK" pad="B6"/>
<connect gate="MACHXO2-ERB" pin="TDI" pad="B4"/>
<connect gate="MACHXO2-ERB" pin="TDO" pad="A4"/>
<connect gate="MACHXO2-ERB" pin="TMS" pad="A6"/>
<connect gate="MACHXO2-PWR" pin="GND@A5" pad="A5"/>
<connect gate="MACHXO2-PWR" pin="GND@B11" pad="B11"/>
<connect gate="MACHXO2-PWR" pin="GND@D13" pad="D13"/>
<connect gate="MACHXO2-PWR" pin="GND@D2" pad="D2"/>
<connect gate="MACHXO2-PWR" pin="GND@G2" pad="G2"/>
<connect gate="MACHXO2-PWR" pin="GND@H13" pad="H13"/>
<connect gate="MACHXO2-PWR" pin="GND@L13" pad="L13"/>
<connect gate="MACHXO2-PWR" pin="GND@L2" pad="L2"/>
<connect gate="MACHXO2-PWR" pin="GND@P10" pad="P10"/>
<connect gate="MACHXO2-PWR" pin="GND@P5" pad="P5"/>
<connect gate="MACHXO2-PWR" pin="VCC@A1" pad="A1"/>
<connect gate="MACHXO2-PWR" pin="VCC@A14" pad="A14"/>
<connect gate="MACHXO2-PWR" pin="VCC@N1" pad="N1"/>
<connect gate="MACHXO2-PWR" pin="VCC@P14" pad="P14"/>
<connect gate="MACHXO2-PWR" pin="VCCIO0@A8" pad="A8"/>
<connect gate="MACHXO2-PWR" pin="VCCIO0@B10" pad="B10"/>
<connect gate="MACHXO2-PWR" pin="VCCIO0@C5" pad="C5"/>
<connect gate="MACHXO2-PWR" pin="VCCIO1@D14" pad="D14"/>
<connect gate="MACHXO2-PWR" pin="VCCIO1@H14" pad="H14"/>
<connect gate="MACHXO2-PWR" pin="VCCIO1@L12" pad="L12"/>
<connect gate="MACHXO2-PWR" pin="VCCIO2@M6" pad="M6"/>
<connect gate="MACHXO2-PWR" pin="VCCIO2@N11" pad="N11"/>
<connect gate="MACHXO2-PWR" pin="VCCIO2@P1" pad="P1"/>
<connect gate="MACHXO2-PWR" pin="VCCIO3/5@D3" pad="D3"/>
<connect gate="MACHXO2-PWR" pin="VCCIO3@L1" pad="L1"/>
<connect gate="MACHXO2-PWR" pin="VCCIO4@G1" pad="G1"/>
<connect gate="MACHXO2-QNF32-256" pin="PB_4A/6C/9A/11A/13A" pad="N6"/>
<connect gate="MACHXO2-QNF32-256" pin="PB_4B/6D/9B/11B/13B" pad="P6"/>
<connect gate="MACHXO2-QNF32-256" pin="PB_4C/10C/11A/16A/20A" pad="M7"/>
<connect gate="MACHXO2-QNF32-256" pin="PB_4D/10D/11B/16B/20B" pad="N8"/>
<connect gate="MACHXO2-QNF32-256" pin="PL_5C/7A/9A/12A/17A" pad="K1"/>
<connect gate="MACHXO2-QNF32-256" pin="PL_5D/7B/9B/12B/17B" pad="K3"/>
<connect gate="MACHXO2-QNF32-256" pin="PR_5A/5C/5C/7A/10A" pad="G13"/>
<connect gate="MACHXO2-QNF32-256" pin="PR_5B/5D/5D/7B/10B" pad="H12"/>
</connects>
<technologies>
<technology name="HC-4"/>
<technology name="HC-5"/>
<technology name="HC-6"/>
<technology name="HE-4"/>
<technology name="HE-5"/>
<technology name="HE-6"/>
<technology name="ZE-1"/>
<technology name="ZE-2"/>
<technology name="ZE-3"/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LCMXO2-1200" prefix="U">
<description>&lt;h3&gt; MachXO2-1200 in csBGA132 or TQFP144 package.&lt;/h3&gt;

&lt;p&gt;Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf"&gt;Datasheet&lt;/a&gt; (DS1035)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="MACHXO2-CSBGA132-PWR" symbol="MACHXO2-CSBGA132-PWR" x="-43.18" y="55.88"/>
<gate name="MACHXO2-ERB" symbol="MACHXO2-ERB" x="86.36" y="55.88"/>
<gate name="MACHXO2-QFN32-256" symbol="MACHXO2-QFN32-256" x="35.56" y="-55.88"/>
<gate name="MACHXO2-CSBGA132-256-TOP" symbol="MACHXO2-CSBGA132-256-TOP" x="35.56" y="-12.7"/>
<gate name="MACHXO2-CSBGA132-256-LEFT" symbol="MACHXO2-CSBGA132-256-LEFT" x="-22.86" y="-30.48"/>
<gate name="MACHXO2-CSBGA132-256-RIGHT" symbol="MACHXO2-CSBGA132-256-RIGHT" x="83.82" y="-30.48"/>
<gate name="MACHXO2-CSBGA132-256-BOTTOM" symbol="MACHXO2-CSBGA132-256-BOTTOM" x="35.56" y="-86.36"/>
<gate name="MACHXO2-CSBGA132-640-TOP" symbol="MACHXO2-CSBGA132-640-TOP" x="35.56" y="5.08"/>
<gate name="MACHXO2-CSBGA132-640-LEFT" symbol="MACHXO2-CSBGA132-640-LEFT" x="-22.86" y="-66.04"/>
<gate name="MACHXO2-CSBGA132-640-RIGHT" symbol="MACHXO2-CSBGA132-640-RIGHT" x="86.36" y="-66.04"/>
<gate name="MACHXO2-CSBGA132-640-BOTTOM" symbol="MACHXO2-CSBGA132-640-BOTTOM" x="35.56" y="-106.68"/>
<gate name="MACHXO2-CSBGA132-1200-TOP" symbol="MACHXO2-CSBGA132-1200-TOP" x="35.56" y="30.48"/>
<gate name="MACHXO2-CSBGA132-1200-LEFT" symbol="MACHXO2-CSBGA132-1200-LEFT" x="-22.86" y="-86.36"/>
<gate name="MACHXO2-CSBGA132-1200-RIGHT" symbol="MACHXO2-CSBGA132-1200-RIGHT" x="83.82" y="-88.9"/>
<gate name="MACHXO2-CSBGA132-1200-BOTTOM" symbol="MACHXO2-CSBGA132-1200-BOTTOM" x="35.56" y="-132.08"/>
<gate name="MACHXO2-TQFP144" symbol="MACHXO2-TQFP144-1200" x="35.56" y="-35.56"/>
</gates>
<devices>
<device name="MG132" package="CSBGA132-MACHXO2">
<connects>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15C/19A/23A" pad="P9"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15D/19B/23B" pad="N9"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20A/24A/29A" pad="M11"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20B/24B/29B" pad="P12"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4A/3A/3A" pad="P2"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4B/3B/3B" pad="N2"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9C/9A/10A" pad="N5"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9D/9B/10B" pad="M5"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//10B/13B/19B" pad="L3"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2A/1A/3A" pad="B1"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2B/1B/3B" pad="B2"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4C/6A/9A" pad="F1"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4D/6B/9B" pad="F3"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10A/13A/18A" pad="M12"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10B/13B/18B" pad="M14"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2C/2A/3A" pad="C14"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2D/2B/3B" pad="D12"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8A/9A/13A" pad="J12"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8B/9B/13B" pad="J14"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11A/13A/14A" pad="B5"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11B/13B/14B" pad="C6"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16A/21A/24A" pad="A10"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16B/21B/24B" pad="C11"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17A/23A/27A" pad="C12"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17B/24B/27B" pad="A12"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7A/12A/15A/18A/21A" pad="P8"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7B/12B/15B/18B/21B" pad="M8"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7C/12C/18A/21A/24A" pad="M9"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7D/12D/18B/21B/24B" pad="N10"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2A/2A/2C/2A/4A" pad="C1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2B/2B/2D/2B/4B" pad="C3"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2C/2C/3A/3A/6A" pad="C2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2D/2D/3B/3B/6B" pad="D1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3A/3A/3C/4A/7A" pad="E1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3B/3B/3D/4B/7B" pad="E2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3C/5A/5A/7C/10C" pad="G3"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3D/5B/5B/7D/10D" pad="H2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5A/6A/8A/10A/14A" pad="J1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5B/6B/8B/10B/14B" pad="J2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6A/7C/10C/14A/20A" pad="M1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6B/7D/10D/14B/20B" pad="M2"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2A/2A/2A/1A/2A" pad="B14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2B/2B/2B/1B/2B" pad="C13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3A/2C/3A/3A/5A" pad="E12"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3B/2D/3B/3B/5B" pad="E14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3C/3C/4C/5A/8A" pad="F13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3D/3D/4D/5B/8B" pad="F14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5C/6C/9A/11A/15A" pad="K13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5D/6D/9B/11B/15B" pad="K14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6A/7A/9C/12A/16A" pad="L14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6B/7B/9D/12B/16B" pad="M13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6C/7C/10C/14A/19A" pad="N13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6D/7D/10D/14B/19B" pad="N14"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6A/6A/9A/9A/9A" pad="A2"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6B/6B/9B/9B/9B" pad="B3"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8A/9A/12A/17A/18A" pad="A7"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8B/9B/12B/17B/18B" pad="B7"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10A/11C/12A/15A" pad="P7"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10B/11D/12B/15B" pad="N7"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14A/18C/22A/27A" pad="M10"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14B/18D/22B/27B" pad="P11"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4C/6A/6A/7A" pad="N3"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4D/6B/6B/7B" pad="P4"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3C/4A/5A/8A" pad="E3"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3D/4B/5B/8B" pad="F2"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5C/5C/9A/13A" pad="H1"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5D/5D/9B/13B" pad="H3"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6C/8C/11A/16A" pad="J3"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6D/8D/11B/16B" pad="K2"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3A/4A/4A/6A" pad="E13"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3B/4B/4B/6B" pad="F12"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5A/5A/6A/9A" pad="G12"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5B/5B/6B/9B" pad="G14"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6A/8C/10A/14A" pad="J13"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6B/8D/10B/14B" pad="K12"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10A/15A/19A/21A" pad="C9"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10B/15B/19B/21B" pad="A9"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11A/16C/22A/25A" pad="A11"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11B/16D/22B/25B" pad="B12"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6C/10A/11A/11A" pad="A3"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6D/10B/11B/11B" pad="C4"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@A5" pad="A5"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@B11" pad="B11"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D13" pad="D13"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D2" pad="D2"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@G2" pad="G2"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@H13" pad="H13"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L13" pad="L13"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L2" pad="L2"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P10" pad="P10"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P5" pad="P5"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A1" pad="A1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A14" pad="A14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@N1" pad="N1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@P14" pad="P14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@A8" pad="A8"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@B10" pad="B10"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@C5" pad="C5"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@D14" pad="D14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@H14" pad="H14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@L12" pad="L12"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@M6" pad="M6"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@N11" pad="N11"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@P1" pad="P1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3/5@D3" pad="D3"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3@L1" pad="L1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO4@G1" pad="G1"/>
<connect gate="MACHXO2-ERB" pin="CSSPIN/PB_2A..." pad="P3"/>
<connect gate="MACHXO2-ERB" pin="DONE/PT17D" pad="A13"/>
<connect gate="MACHXO2-ERB" pin="INITN/PT17C" pad="B13"/>
<connect gate="MACHXO2-ERB" pin="JTAGENB/PT15C" pad="B9"/>
<connect gate="MACHXO2-ERB" pin="MCLK/CCLK/PB6C" pad="M4"/>
<connect gate="MACHXO2-ERB" pin="PB_2B/4B/4D/5B/4B" pad="M3"/>
<connect gate="MACHXO2-ERB" pin="PROGRAMN/PT15D" pad="C10"/>
<connect gate="MACHXO2-ERB" pin="SCL/PT12C" pad="C8"/>
<connect gate="MACHXO2-ERB" pin="SDA/PT12D" pad="B8"/>
<connect gate="MACHXO2-ERB" pin="SISPI/PB20D" pad="P13"/>
<connect gate="MACHXO2-ERB" pin="SN/PB20C" pad="N12"/>
<connect gate="MACHXO2-ERB" pin="SPISO/PB6D" pad="N4"/>
<connect gate="MACHXO2-ERB" pin="TCK" pad="B6"/>
<connect gate="MACHXO2-ERB" pin="TDI" pad="B4"/>
<connect gate="MACHXO2-ERB" pin="TDO" pad="A4"/>
<connect gate="MACHXO2-ERB" pin="TMS" pad="A6"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4A/6C/9A/11A/13A" pad="N6"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4B/6D/9B/11B/13B" pad="P6"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4C/10C/11A/16A/20A" pad="M7"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4D/10D/11B/16B/20B" pad="N8"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5C/7A/9A/12A/17A" pad="K1"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5D/7B/9B/12B/17B" pad="K3"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5A/5C/5C/7A/10A" pad="G13"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5B/5D/5D/7B/10B" pad="H12"/>
<connect gate="MACHXO2-TQFP144" pin="PL_//10A/13A/19A" pad="NC1"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9C/10A/10A" pad="NC2"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9D/10B/10B" pad="NC3"/>
</connects>
<technologies>
<technology name="HC-4"/>
<technology name="HC-5"/>
<technology name="HC-6"/>
<technology name="HE-4"/>
<technology name="HE-5"/>
<technology name="HE-6"/>
<technology name="ZE-1"/>
<technology name="ZE-2"/>
<technology name="ZE-3"/>
</technologies>
</device>
<device name="TG144" package="TQFP144">
<connects>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15C/19A/23A" pad="59"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15D/19B/23B" pad="60"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20A/24A/29A" pad="68"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20B/24B/29B" pad="69"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4A/3A/3A" pad="38"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4B/3B/3B" pad="39"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9C/9A/10A" pad="47"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9D/9B/10B" pad="48"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//10B/13B/19B" pad="33"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2A/1A/3A" pad="1"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2B/1B/3B" pad="2"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4C/6A/9A" pad="13"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4D/6B/9B" pad="14"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10A/13A/18A" pad="76"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10B/13B/18B" pad="75"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2C/2A/3A" pad="105"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2D/2B/3B" pad="104"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8A/9A/13A" pad="86"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8B/9B/13B" pad="85"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11A/13A/14A" pad="133"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11B/13B/14B" pad="132"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16A/21A/24A" pad="117"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16B/21B/24B" pad="115"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17A/23A/27A" pad="112"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17B/24B/27B" pad="111"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7A/12A/15A/18A/21A" pad="57"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7B/12B/15B/18B/21B" pad="58"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7C/12C/18A/21A/24A" pad="61"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7D/12D/18B/21B/24B" pad="62"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2A/2A/2C/2A/4A" pad="3"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2B/2B/2D/2B/4B" pad="4"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2C/2C/3A/3A/6A" pad="5"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2D/2D/3B/3B/6B" pad="6"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3A/3A/3C/4A/7A" pad="9"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3B/3B/3D/4B/7B" pad="10"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3C/5A/5A/7C/10C" pad="19"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3D/5B/5B/7D/10D" pad="20"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5A/6A/8A/10A/14A" pad="23"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5B/6B/8B/10B/14B" pad="24"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6A/7C/10C/14A/20A" pad="34"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6B/7D/10D/14B/20B" pad="35"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2A/2A/2A/1A/2A" pad="107"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2B/2B/2B/1B/2B" pad="106"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3A/2C/3A/3A/5A" pad="100"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3B/2D/3B/3B/5B" pad="99"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3C/3C/4C/5A/8A" pad="96"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3D/3D/4D/5B/8B" pad="95"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5C/6C/9A/11A/15A" pad="82"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5D/6D/9B/11B/15B" pad="81"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6A/7A/9C/12A/16A" pad="78"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6B/7B/9D/12B/16B" pad="77"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6C/7C/10C/14A/19A" pad="74"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6D/7D/10D/14B/19B" pad="73"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6A/6A/9A/9A/9A" pad="143"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6B/6B/9B/9B/9B" pad="142"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8A/9A/12A/17A/18A" pad="128"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8B/9B/12B/17B/18B" pad="127"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10A/11C/12A/15A" pad="52"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10B/11D/12B/15B" pad="54"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14A/18C/22A/27A" pad="65"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14B/18D/22B/27B" pad="67"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4C/6A/6A/7A" pad="42"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4D/6B/6B/7B" pad="43"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3C/4A/5A/8A" pad="11"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3D/4B/5B/8B" pad="12"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5C/5C/9A/13A" pad="21"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5D/5D/9B/13B" pad="22"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6C/8C/11A/16A" pad="25"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6D/8D/11B/16B" pad="26"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3A/4A/4A/6A" pad="98"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3B/4B/4B/6B" pad="97"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5A/5A/6A/9A" pad="94"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5B/5B/6B/9B" pad="93"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6A/8C/10A/14A" pad="84"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6B/8D/10B/14B" pad="83"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10A/15A/19A/21A" pad="122"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10B/15B/19B/21B" pad="121"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11A/16C/22A/25A" pad="114"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11B/16D/22B/25B" pad="113"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6C/10A/11A/11A" pad="139"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6D/10B/11B/11B" pad="138"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@A5" pad="46 116"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@B11" pad="134"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D13" pad="101"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D2" pad="8"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@G2" pad="18"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@H13" pad="80 90"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L13" pad="124"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L2" pad="29"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P10" pad="64"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P5" pad="53"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A1" pad="144"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A14" pad="72"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@N1" pad="36"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@P14" pad="108"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@A8" pad="135"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@B10" pad="123"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@C5" pad="118"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@D14" pad="88"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@H14" pad="102"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@L12" pad="79"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@M6" pad="51"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@N11" pad="66"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@P1" pad="37"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3/5@D3" pad="7"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3@L1" pad="30"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO4@G1" pad="16"/>
<connect gate="MACHXO2-ERB" pin="CSSPIN/PB_2A..." pad="40"/>
<connect gate="MACHXO2-ERB" pin="DONE/PT17D" pad="109"/>
<connect gate="MACHXO2-ERB" pin="INITN/PT17C" pad="110"/>
<connect gate="MACHXO2-ERB" pin="JTAGENB/PT15C" pad="120"/>
<connect gate="MACHXO2-ERB" pin="MCLK/CCLK/PB6C" pad="44"/>
<connect gate="MACHXO2-ERB" pin="PB_2B/4B/4D/5B/4B" pad="41"/>
<connect gate="MACHXO2-ERB" pin="PROGRAMN/PT15D" pad="119"/>
<connect gate="MACHXO2-ERB" pin="SCL/PT12C" pad="126"/>
<connect gate="MACHXO2-ERB" pin="SDA/PT12D" pad="125"/>
<connect gate="MACHXO2-ERB" pin="SISPI/PB20D" pad="71"/>
<connect gate="MACHXO2-ERB" pin="SN/PB20C" pad="70"/>
<connect gate="MACHXO2-ERB" pin="SPISO/PB6D" pad="45"/>
<connect gate="MACHXO2-ERB" pin="TCK" pad="131"/>
<connect gate="MACHXO2-ERB" pin="TDI" pad="136"/>
<connect gate="MACHXO2-ERB" pin="TDO" pad="137"/>
<connect gate="MACHXO2-ERB" pin="TMS" pad="130"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4A/6C/9A/11A/13A" pad="49"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4B/6D/9B/11B/13B" pad="50"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4C/10C/11A/16A/20A" pad="55"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4D/10D/11B/16B/20B" pad="56"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5C/7A/9A/12A/17A" pad="27"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5D/7B/9B/12B/17B" pad="28"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5A/5C/5C/7A/10A" pad="92"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5B/5D/5D/7B/10B" pad="91"/>
<connect gate="MACHXO2-TQFP144" pin="PL_//10A/13A/19A" pad="32"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9C/10A/10A" pad="141"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9D/10B/10B" pad="140"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LCMXO2-2000" prefix="U">
<description>&lt;h3&gt; MachXO2-2000 in csBGA132 or TQFP144 package.&lt;/h3&gt;

&lt;p&gt;Lattice MachXO2-series FPGA in a 132 ball chip size BGA or 144 lead TQFP package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf"&gt;Datasheet&lt;/a&gt; (DS1035)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="MACHXO2-CSBGA132-PWR" symbol="MACHXO2-CSBGA132-PWR" x="-43.18" y="55.88"/>
<gate name="MACHXO2-ERB" symbol="MACHXO2-ERB" x="86.36" y="55.88"/>
<gate name="MACHXO2-QFN32-256" symbol="MACHXO2-QFN32-256" x="35.56" y="-55.88"/>
<gate name="MACHXO2-CSBGA132-256-TOP" symbol="MACHXO2-CSBGA132-256-TOP" x="35.56" y="2.54"/>
<gate name="MACHXO2-CSBGA132-256-LEFT" symbol="MACHXO2-CSBGA132-256-LEFT" x="-22.86" y="-30.48"/>
<gate name="MACHXO2-CSBGA132-256-RIGHT" symbol="MACHXO2-CSBGA132-256-RIGHT" x="83.82" y="-30.48"/>
<gate name="MACHXO2-CSBGA132-256-BOTTOM" symbol="MACHXO2-CSBGA132-256-BOTTOM" x="35.56" y="-86.36"/>
<gate name="MACHXO2-CSBGA132-640-TOP" symbol="MACHXO2-CSBGA132-640-TOP" x="35.56" y="20.32"/>
<gate name="MACHXO2-CSBGA132-640-LEFT" symbol="MACHXO2-CSBGA132-640-LEFT" x="-22.86" y="-66.04"/>
<gate name="MACHXO2-CSBGA132-640-RIGHT" symbol="MACHXO2-CSBGA132-640-RIGHT" x="86.36" y="-66.04"/>
<gate name="MACHXO2-CSBGA132-640-BOTTOM" symbol="MACHXO2-CSBGA132-640-BOTTOM" x="35.56" y="-106.68"/>
<gate name="MACHXO2-CSBGA132-1200-TOP" symbol="MACHXO2-CSBGA132-1200-TOP" x="33.02" y="43.18"/>
<gate name="MACHXO2-CSBGA132-1200-LEFT" symbol="MACHXO2-CSBGA132-1200-LEFT" x="-22.86" y="-86.36"/>
<gate name="MACHXO2-CSBGA132-1200-RIGHT" symbol="MACHXO2-CSBGA132-1200-RIGHT" x="83.82" y="-88.9"/>
<gate name="MACHXO2-CSBGA132-1200-BOTTOM" symbol="MACHXO2-CSBGA132-1200-BOTTOM" x="35.56" y="-132.08"/>
<gate name="MACHXO2-TQFP144" symbol="MACHXO2-TQFP144-1200" x="35.56" y="-35.56"/>
<gate name="MACHXO2-TEFQ144-2000" symbol="MACHXO2-TQFP144-2000" x="35.56" y="-20.32"/>
</gates>
<devices>
<device name="MG132" package="CSBGA132-MACHXO2">
<connects>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15C/19A/23A" pad="P9"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15D/19B/23B" pad="N9"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20A/24A/29A" pad="M11"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20B/24B/29B" pad="P12"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4A/3A/3A" pad="P2"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4B/3B/3B" pad="N2"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9C/9A/10A" pad="N5"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9D/9B/10B" pad="M5"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//10B/13B/19B" pad="L3"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2A/1A/3A" pad="B1"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2B/1B/3B" pad="B2"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4C/6A/9A" pad="F1"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4D/6B/9B" pad="F3"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10A/13A/18A" pad="M12"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10B/13B/18B" pad="M14"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2C/2A/3A" pad="C14"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2D/2B/3B" pad="D12"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8A/9A/13A" pad="J12"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8B/9B/13B" pad="J14"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11A/13A/14A" pad="B5"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11B/13B/14B" pad="C6"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16A/21A/24A" pad="A10"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16B/21B/24B" pad="C11"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17A/23A/27A" pad="C12"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17B/24B/27B" pad="A12"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7A/12A/15A/18A/21A" pad="P8"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7B/12B/15B/18B/21B" pad="M8"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7C/12C/18A/21A/24A" pad="M9"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7D/12D/18B/21B/24B" pad="N10"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2A/2A/2C/2A/4A" pad="C1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2B/2B/2D/2B/4B" pad="C3"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2C/2C/3A/3A/6A" pad="C2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2D/2D/3B/3B/6B" pad="D1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3A/3A/3C/4A/7A" pad="E1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3B/3B/3D/4B/7B" pad="E2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3C/5A/5A/7C/10C" pad="G3"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3D/5B/5B/7D/10D" pad="H2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5A/6A/8A/10A/14A" pad="J1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5B/6B/8B/10B/14B" pad="J2"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6A/7C/10C/14A/20A" pad="M1"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6B/7D/10D/14B/20B" pad="M2"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2A/2A/2A/1A/2A" pad="B14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2B/2B/2B/1B/2B" pad="C13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3A/2C/3A/3A/5A" pad="E12"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3B/2D/3B/3B/5B" pad="E14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3C/3C/4C/5A/8A" pad="F13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3D/3D/4D/5B/8B" pad="F14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5C/6C/9A/11A/15A" pad="K13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5D/6D/9B/11B/15B" pad="K14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6A/7A/9C/12A/16A" pad="L14"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6B/7B/9D/12B/16B" pad="M13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6C/7C/10C/14A/19A" pad="N13"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6D/7D/10D/14B/19B" pad="N14"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6A/6A/9A/9A/9A" pad="A2"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6B/6B/9B/9B/9B" pad="B3"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8A/9A/12A/17A/18A" pad="A7"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8B/9B/12B/17B/18B" pad="B7"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10A/11C/12A/15A" pad="P7"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10B/11D/12B/15B" pad="N7"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14A/18C/22A/27A" pad="M10"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14B/18D/22B/27B" pad="P11"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4C/6A/6A/7A" pad="N3"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4D/6B/6B/7B" pad="P4"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3C/4A/5A/8A" pad="E3"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3D/4B/5B/8B" pad="F2"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5C/5C/9A/13A" pad="H1"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5D/5D/9B/13B" pad="H3"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6C/8C/11A/16A" pad="J3"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6D/8D/11B/16B" pad="K2"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3A/4A/4A/6A" pad="E13"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3B/4B/4B/6B" pad="F12"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5A/5A/6A/9A" pad="G12"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5B/5B/6B/9B" pad="G14"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6A/8C/10A/14A" pad="J13"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6B/8D/10B/14B" pad="K12"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10A/15A/19A/21A" pad="C9"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10B/15B/19B/21B" pad="A9"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11A/16C/22A/25A" pad="A11"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11B/16D/22B/25B" pad="B12"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6C/10A/11A/11A" pad="A3"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6D/10B/11B/11B" pad="C4"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@A5" pad="A5"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@B11" pad="B11"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D13" pad="D13"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D2" pad="D2"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@G2" pad="G2"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@H13" pad="H13"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L13" pad="L13"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L2" pad="L2"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P10" pad="P10"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P5" pad="P5"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A1" pad="A1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A14" pad="A14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@N1" pad="N1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@P14" pad="P14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@A8" pad="A8"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@B10" pad="B10"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@C5" pad="C5"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@D14" pad="D14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@H14" pad="H14"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@L12" pad="L12"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@M6" pad="M6"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@N11" pad="N11"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@P1" pad="P1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3/5@D3" pad="D3"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3@L1" pad="L1"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO4@G1" pad="G1"/>
<connect gate="MACHXO2-ERB" pin="CSSPIN/PB_2A..." pad="P3"/>
<connect gate="MACHXO2-ERB" pin="DONE/PT17D" pad="A13"/>
<connect gate="MACHXO2-ERB" pin="INITN/PT17C" pad="B13"/>
<connect gate="MACHXO2-ERB" pin="JTAGENB/PT15C" pad="B9"/>
<connect gate="MACHXO2-ERB" pin="MCLK/CCLK/PB6C" pad="M4"/>
<connect gate="MACHXO2-ERB" pin="PB_2B/4B/4D/5B/4B" pad="M3"/>
<connect gate="MACHXO2-ERB" pin="PROGRAMN/PT15D" pad="C10"/>
<connect gate="MACHXO2-ERB" pin="SCL/PT12C" pad="C8"/>
<connect gate="MACHXO2-ERB" pin="SDA/PT12D" pad="B8"/>
<connect gate="MACHXO2-ERB" pin="SISPI/PB20D" pad="P13"/>
<connect gate="MACHXO2-ERB" pin="SN/PB20C" pad="N12"/>
<connect gate="MACHXO2-ERB" pin="SPISO/PB6D" pad="N4"/>
<connect gate="MACHXO2-ERB" pin="TCK" pad="B6"/>
<connect gate="MACHXO2-ERB" pin="TDI" pad="B4"/>
<connect gate="MACHXO2-ERB" pin="TDO" pad="A4"/>
<connect gate="MACHXO2-ERB" pin="TMS" pad="A6"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4A/6C/9A/11A/13A" pad="N6"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4B/6D/9B/11B/13B" pad="P6"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4C/10C/11A/16A/20A" pad="M7"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4D/10D/11B/16B/20B" pad="N8"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5C/7A/9A/12A/17A" pad="K1"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5D/7B/9B/12B/17B" pad="K3"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5A/5C/5C/7A/10A" pad="G13"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5B/5D/5D/7B/10B" pad="H12"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PL_///7A/10A/10A" pad="NC4"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PL_///7B/10B/10B" pad="NC5"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PR_///7C/10C/15A" pad="NC6"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PR_///7D/10D/15B" pad="NC7"/>
<connect gate="MACHXO2-TQFP144" pin="PL_//10A/13A/19A" pad="NC1"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9C/10A/10A" pad="NC2"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9D/10B/10B" pad="NC3"/>
</connects>
<technologies>
<technology name="HC-4"/>
<technology name="HC-5"/>
<technology name="HC-6"/>
<technology name="HE-4"/>
<technology name="HE-5"/>
<technology name="HE-6"/>
<technology name="ZE-1"/>
<technology name="ZE-2"/>
<technology name="ZE-3"/>
</technologies>
</device>
<device name="TG144" package="TQFP144">
<connects>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15C/19A/23A" pad="59"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//15D/19B/23B" pad="60"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20A/24A/29A" pad="68"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//20B/24B/29B" pad="69"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4A/3A/3A" pad="38"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//4B/3B/3B" pad="39"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9C/9A/10A" pad="47"/>
<connect gate="MACHXO2-CSBGA132-1200-BOTTOM" pin="PB_//9D/9B/10B" pad="48"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//10B/13B/19B" pad="33"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2A/1A/3A" pad="1"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//2B/1B/3B" pad="2"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4C/6A/9A" pad="13"/>
<connect gate="MACHXO2-CSBGA132-1200-LEFT" pin="PL_//4D/6B/9B" pad="14"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10A/13A/18A" pad="76"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//10B/13B/18B" pad="75"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2C/2A/3A" pad="105"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//2D/2B/3B" pad="104"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8A/9A/13A" pad="86"/>
<connect gate="MACHXO2-CSBGA132-1200-RIGHT" pin="PR_//8B/9B/13B" pad="85"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11A/13A/14A" pad="133"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//11B/13B/14B" pad="132"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16A/21A/24A" pad="117"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//16B/21B/24B" pad="115"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17A/23A/27A" pad="112"/>
<connect gate="MACHXO2-CSBGA132-1200-TOP" pin="PT_//17B/24B/27B" pad="111"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7A/12A/15A/18A/21A" pad="57"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7B/12B/15B/18B/21B" pad="58"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7C/12C/18A/21A/24A" pad="61"/>
<connect gate="MACHXO2-CSBGA132-256-BOTTOM" pin="PB_7D/12D/18B/21B/24B" pad="62"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2A/2A/2C/2A/4A" pad="3"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2B/2B/2D/2B/4B" pad="4"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2C/2C/3A/3A/6A" pad="5"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_2D/2D/3B/3B/6B" pad="6"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3A/3A/3C/4A/7A" pad="9"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3B/3B/3D/4B/7B" pad="10"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3C/5A/5A/7C/10C" pad="19"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_3D/5B/5B/7D/10D" pad="20"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5A/6A/8A/10A/14A" pad="23"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_5B/6B/8B/10B/14B" pad="24"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6A/7C/10C/14A/20A" pad="34"/>
<connect gate="MACHXO2-CSBGA132-256-LEFT" pin="PL_6B/7D/10D/14B/20B" pad="35"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2A/2A/2A/1A/2A" pad="107"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_2B/2B/2B/1B/2B" pad="106"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3A/2C/3A/3A/5A" pad="100"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3B/2D/3B/3B/5B" pad="99"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3C/3C/4C/5A/8A" pad="96"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_3D/3D/4D/5B/8B" pad="95"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5C/6C/9A/11A/15A" pad="82"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_5D/6D/9B/11B/15B" pad="81"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6A/7A/9C/12A/16A" pad="78"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6B/7B/9D/12B/16B" pad="77"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6C/7C/10C/14A/19A" pad="74"/>
<connect gate="MACHXO2-CSBGA132-256-RIGHT" pin="PR_6D/7D/10D/14B/19B" pad="73"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6A/6A/9A/9A/9A" pad="143"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_6B/6B/9B/9B/9B" pad="142"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8A/9A/12A/17A/18A" pad="128"/>
<connect gate="MACHXO2-CSBGA132-256-TOP" pin="PT_8B/9B/12B/17B/18B" pad="127"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10A/11C/12A/15A" pad="52"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/10B/11D/12B/15B" pad="54"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14A/18C/22A/27A" pad="65"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/14B/18D/22B/27B" pad="67"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4C/6A/6A/7A" pad="42"/>
<connect gate="MACHXO2-CSBGA132-640-BOTTOM" pin="PB_/4D/6B/6B/7B" pad="43"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3C/4A/5A/8A" pad="11"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/3D/4B/5B/8B" pad="12"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5C/5C/9A/13A" pad="21"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/5D/5D/9B/13B" pad="22"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6C/8C/11A/16A" pad="25"/>
<connect gate="MACHXO2-CSBGA132-640-LEFT" pin="PL_/6D/8D/11B/16B" pad="26"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3A/4A/4A/6A" pad="98"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/3B/4B/4B/6B" pad="97"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5A/5A/6A/9A" pad="94"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/5B/5B/6B/9B" pad="93"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6A/8C/10A/14A" pad="84"/>
<connect gate="MACHXO2-CSBGA132-640-RIGHT" pin="PR_/6B/8D/10B/14B" pad="83"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10A/15A/19A/21A" pad="122"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/10B/15B/19B/21B" pad="121"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11A/16C/22A/25A" pad="114"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/11B/16D/22B/25B" pad="113"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6C/10A/11A/11A" pad="139"/>
<connect gate="MACHXO2-CSBGA132-640-TOP" pin="PT_/6D/10B/11B/11B" pad="138"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@A5" pad="46 116"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@B11" pad="134"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D13" pad="101"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@D2" pad="8"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@G2" pad="18"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@H13" pad="80 90"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L13" pad="124"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@L2" pad="29"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P10" pad="64"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="GND@P5" pad="53"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A1" pad="144"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@A14" pad="72"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@N1" pad="36"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCC@P14" pad="108"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@A8" pad="135"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@B10" pad="123"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO0@C5" pad="118"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@D14" pad="88"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@H14" pad="102"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO1@L12" pad="79"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@M6" pad="51"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@N11" pad="66"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO2@P1" pad="37"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3/5@D3" pad="7"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO3@L1" pad="30"/>
<connect gate="MACHXO2-CSBGA132-PWR" pin="VCCIO4@G1" pad="16"/>
<connect gate="MACHXO2-ERB" pin="CSSPIN/PB_2A..." pad="40"/>
<connect gate="MACHXO2-ERB" pin="DONE/PT17D" pad="109"/>
<connect gate="MACHXO2-ERB" pin="INITN/PT17C" pad="110"/>
<connect gate="MACHXO2-ERB" pin="JTAGENB/PT15C" pad="120"/>
<connect gate="MACHXO2-ERB" pin="MCLK/CCLK/PB6C" pad="44"/>
<connect gate="MACHXO2-ERB" pin="PB_2B/4B/4D/5B/4B" pad="41"/>
<connect gate="MACHXO2-ERB" pin="PROGRAMN/PT15D" pad="119"/>
<connect gate="MACHXO2-ERB" pin="SCL/PT12C" pad="126"/>
<connect gate="MACHXO2-ERB" pin="SDA/PT12D" pad="125"/>
<connect gate="MACHXO2-ERB" pin="SISPI/PB20D" pad="71"/>
<connect gate="MACHXO2-ERB" pin="SN/PB20C" pad="70"/>
<connect gate="MACHXO2-ERB" pin="SPISO/PB6D" pad="45"/>
<connect gate="MACHXO2-ERB" pin="TCK" pad="131"/>
<connect gate="MACHXO2-ERB" pin="TDI" pad="136"/>
<connect gate="MACHXO2-ERB" pin="TDO" pad="137"/>
<connect gate="MACHXO2-ERB" pin="TMS" pad="130"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4A/6C/9A/11A/13A" pad="49"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4B/6D/9B/11B/13B" pad="50"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4C/10C/11A/16A/20A" pad="55"/>
<connect gate="MACHXO2-QFN32-256" pin="PB_4D/10D/11B/16B/20B" pad="56"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5C/7A/9A/12A/17A" pad="27"/>
<connect gate="MACHXO2-QFN32-256" pin="PL_5D/7B/9B/12B/17B" pad="28"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5A/5C/5C/7A/10A" pad="92"/>
<connect gate="MACHXO2-QFN32-256" pin="PR_5B/5D/5D/7B/10B" pad="91"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PL_///7A/10A/10A" pad="15"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PL_///7B/10B/10B" pad="17"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PR_///7C/10C/15A" pad="87"/>
<connect gate="MACHXO2-TEFQ144-2000" pin="PR_///7D/10D/15B" pad="89"/>
<connect gate="MACHXO2-TQFP144" pin="PL_//10A/13A/19A" pad="32"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9C/10A/10A" pad="141"/>
<connect gate="MACHXO2-TQFP144" pin="PT_//9D/10B/10B" pad="140"/>
</connects>
<technologies>
<technology name="HC-4"/>
<technology name="HC-5"/>
<technology name="HC-6"/>
<technology name="HE-4"/>
<technology name="HE-5"/>
<technology name="HE-6"/>
<technology name="ZE-1"/>
<technology name="ZE-2"/>
<technology name="ZE-3"/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ELLI-STM32F4" prefix="U">
<description>&lt;h3&gt;STM32F427 / 429 ELL-i functions.&lt;/h3&gt;

&lt;p&gt;This device contains a number of pseudo-symbols, meant to be used with a real STM32F42x MCU.  The pseudo-symbols list the ELL-i project functions for the STM32F4 MCU pins.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;TBD (a link to the relevant design document)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="G$1" symbol="ELLI-STM32-PA" x="-38.1" y="25.4"/>
<gate name="G$2" symbol="ELLI-STM32-PB" x="0" y="25.4"/>
<gate name="G$3" symbol="ELLI-STM32-PC" x="38.1" y="25.4"/>
<gate name="G$4" symbol="ELLI-STM32-PD" x="66.04" y="25.4"/>
<gate name="G$5" symbol="ELLI-STM32-PF" x="-10.16" y="-20.32"/>
<gate name="G$6" symbol="ELLI-STM32-PG" x="27.94" y="-20.32"/>
<gate name="G$7" symbol="ELLI-STM32-PE" x="-48.26" y="-20.32"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ELLI-MACHXO2-2000" prefix="U">
<description>&lt;h3&gt;MachXO2 2000 ELL-i functions.&lt;/h3&gt;

&lt;p&gt;This device contains a number of pseudo-symbols, meant to be used with a real MachXO2-2000 FPGA.  The pseudo-symbols list the ELL-i project functions for the 132/144 pins FPGA package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;TBD (a link to the relevant design document)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="G$1" symbol="ELLI-MACHXO2-256-BOTTOM" x="48.26" y="-35.56"/>
<gate name="G$2" symbol="ELLI-MACHXO2-256-LEFT" x="5.08" y="10.16"/>
<gate name="G$3" symbol="ELLI-MACHXO2-256-QNF32" x="48.26" y="-10.16"/>
<gate name="G$4" symbol="ELLI-MACHXO2-256-RIGHT" x="88.9" y="10.16"/>
<gate name="G$5" symbol="ELLI-MACHXO2-256-TOP" x="48.26" y="43.18"/>
<gate name="G$6" symbol="ELLI-MACHXO2-640-BOTTOM" x="48.26" y="-53.34"/>
<gate name="G$7" symbol="ELLI-MACHXO2-640-LEFT" x="5.08" y="-25.4"/>
<gate name="G$8" symbol="ELLI-MACHXO2-640-RIGHT" x="88.9" y="-25.4"/>
<gate name="G$9" symbol="ELLI-MACHXO2-640-TOP" x="48.26" y="60.96"/>
<gate name="G$10" symbol="ELLI-MACHXO2-1200-BOTTOM" x="48.26" y="-81.28"/>
<gate name="G$11" symbol="ELLI-MACHXO2-1200-LEFT" x="5.08" y="-45.72"/>
<gate name="G$12" symbol="ELLI-MACHXO2-1200-RIGHT" x="88.9" y="-48.26"/>
<gate name="G$13" symbol="ELLI-MACHXO2-1200-TOP" x="48.26" y="83.82"/>
<gate name="G$14" symbol="ELLI-MACHXO2-1200-TQFP144" x="48.26" y="10.16"/>
<gate name="G$15" symbol="ELLI-MACHXO2-2000-TQFP144" x="48.26" y="25.4"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LCMXO2-256*SG32" prefix="U">
<description>&lt;h3&gt;MachXO2-256 in 32-pin QFN package.&lt;/h3&gt;

&lt;p&gt;Lattice MachXO2-series FPGA in a 32-pin QFN package, 0.5 mm pitch.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;&lt;a href="http://www.latticesemi.com/~/media/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf"&gt;Datasheet&lt;/a&gt; (DS1035)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="IO" symbol="MACHXO2-QFN32-256" x="0" y="0"/>
<gate name="ERB" symbol="MACHXO2-ERB" x="22.86" y="45.72"/>
<gate name="PWR" symbol="MACHXO2-QFN32-PWR" x="30.48" y="5.08"/>
</gates>
<devices>
<device name="" package="QFN-32">
<connects>
<connect gate="ERB" pin="CSSPIN/PB_2A..." pad="8"/>
<connect gate="ERB" pin="DONE/PT17D" pad="23"/>
<connect gate="ERB" pin="INITN/PT17C" pad="NC1"/>
<connect gate="ERB" pin="JTAGENB/PT15C" pad="26"/>
<connect gate="ERB" pin="MCLK/CCLK/PB6C" pad="9"/>
<connect gate="ERB" pin="PB_2B/4B/4D/5B/4B" pad="NC2"/>
<connect gate="ERB" pin="PROGRAMN/PT15D" pad="25"/>
<connect gate="ERB" pin="SCL/PT12C" pad="28"/>
<connect gate="ERB" pin="SDA/PT12D" pad="27"/>
<connect gate="ERB" pin="SISPI/PB20D" pad="17"/>
<connect gate="ERB" pin="SN/PB20C" pad="16"/>
<connect gate="ERB" pin="SPISO/PB6D" pad="10"/>
<connect gate="ERB" pin="TCK" pad="30"/>
<connect gate="ERB" pin="TDI" pad="32"/>
<connect gate="ERB" pin="TDO" pad="1"/>
<connect gate="ERB" pin="TMS" pad="29"/>
<connect gate="IO" pin="PB_4A/6C/9A/11A/13A" pad="11"/>
<connect gate="IO" pin="PB_4B/6D/9B/11B/13B" pad="12"/>
<connect gate="IO" pin="PB_4C/10C/11A/16A/20A" pad="13"/>
<connect gate="IO" pin="PB_4D/10D/11B/16B/20B" pad="14"/>
<connect gate="IO" pin="PL_5C/7A/9A/12A/17A" pad="4"/>
<connect gate="IO" pin="PL_5D/7B/9B/12B/17B" pad="5"/>
<connect gate="IO" pin="PR_5A/5C/5C/7A/10A" pad="21"/>
<connect gate="IO" pin="PR_5B/5D/5D/7B/10B" pad="20"/>
<connect gate="PWR" pin="GND" pad="3 22"/>
<connect gate="PWR" pin="VCC" pad="2 18"/>
<connect gate="PWR" pin="VCCIO0" pad="24 31"/>
<connect gate="PWR" pin="VCCIO1" pad="19"/>
<connect gate="PWR" pin="VCCIO2" pad="7 15"/>
<connect gate="PWR" pin="VCCIO3" pad="6"/>
</connects>
<technologies>
<technology name="HC-4"/>
<technology name="HC-5"/>
<technology name="HC-6"/>
<technology name="HE-4"/>
<technology name="HE-5"/>
<technology name="HE-6"/>
<technology name="ZE-1"/>
<technology name="ZE-2"/>
<technology name="ZE-3"/>
</technologies>
</device>
<device name="-V" package="QFN-32-PAD-VIAS">
<connects>
<connect gate="ERB" pin="CSSPIN/PB_2A..." pad="8"/>
<connect gate="ERB" pin="DONE/PT17D" pad="23"/>
<connect gate="ERB" pin="INITN/PT17C" pad="NC1"/>
<connect gate="ERB" pin="JTAGENB/PT15C" pad="26"/>
<connect gate="ERB" pin="MCLK/CCLK/PB6C" pad="9"/>
<connect gate="ERB" pin="PB_2B/4B/4D/5B/4B" pad="NC2"/>
<connect gate="ERB" pin="PROGRAMN/PT15D" pad="25"/>
<connect gate="ERB" pin="SCL/PT12C" pad="28"/>
<connect gate="ERB" pin="SDA/PT12D" pad="27"/>
<connect gate="ERB" pin="SISPI/PB20D" pad="17"/>
<connect gate="ERB" pin="SN/PB20C" pad="16"/>
<connect gate="ERB" pin="SPISO/PB6D" pad="10"/>
<connect gate="ERB" pin="TCK" pad="30"/>
<connect gate="ERB" pin="TDI" pad="32"/>
<connect gate="ERB" pin="TDO" pad="1"/>
<connect gate="ERB" pin="TMS" pad="29"/>
<connect gate="IO" pin="PB_4A/6C/9A/11A/13A" pad="11"/>
<connect gate="IO" pin="PB_4B/6D/9B/11B/13B" pad="12"/>
<connect gate="IO" pin="PB_4C/10C/11A/16A/20A" pad="13"/>
<connect gate="IO" pin="PB_4D/10D/11B/16B/20B" pad="14"/>
<connect gate="IO" pin="PL_5C/7A/9A/12A/17A" pad="4"/>
<connect gate="IO" pin="PL_5D/7B/9B/12B/17B" pad="5"/>
<connect gate="IO" pin="PR_5A/5C/5C/7A/10A" pad="21"/>
<connect gate="IO" pin="PR_5B/5D/5D/7B/10B" pad="20"/>
<connect gate="PWR" pin="GND" pad="3 22 EP VIA1 VIA2 VIA3 VIA4"/>
<connect gate="PWR" pin="VCC" pad="2 18"/>
<connect gate="PWR" pin="VCCIO0" pad="24 31"/>
<connect gate="PWR" pin="VCCIO1" pad="19"/>
<connect gate="PWR" pin="VCCIO2" pad="7 15"/>
<connect gate="PWR" pin="VCCIO3" pad="6"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ELLI-STM32F0" prefix="U">
<description>&lt;h3&gt;STM32F051/030 ELL-i functions.&lt;/h3&gt;

&lt;p&gt;This device contains a number of pseudo-symbols, meant to be used with a real STM32F0 MCU.  The pseudo-symbols list the ELL-i project functions for the STM32F0 MCU pins in a 64-pin package.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;TBD (a link to the relevant design document)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="G$1" symbol="ELLI-SMALL-STM32-PA" x="2.54" y="30.48"/>
<gate name="G$2" symbol="ELLI-SMALL-STM32-PB" x="40.64" y="30.48"/>
<gate name="G$3" symbol="ELLI-SMALL-STM32-PC" x="2.54" y="-17.78"/>
<gate name="PDF" symbol="ELLI-SMALL-STM32-PDF-LQFP64" x="30.48" y="-5.08"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ENC624J600-I/PT" prefix="U">
<description>Stand-Alone 10/100 Ethernet Controller</description>
<gates>
<gate name="A" symbol="ENC624J600-I/PT" x="0" y="0"/>
</gates>
<devices>
<device name="" package="QFP50P1200X1200X120-64N">
<connects>
<connect gate="A" pin="A0" pad="57"/>
<connect gate="A" pin="A1" pad="58"/>
<connect gate="A" pin="A10" pad="19"/>
<connect gate="A" pin="A11" pad="20"/>
<connect gate="A" pin="A12" pad="43"/>
<connect gate="A" pin="A13" pad="44"/>
<connect gate="A" pin="A14/PSPCFG1" pad="45"/>
<connect gate="A" pin="A2" pad="59"/>
<connect gate="A" pin="A3" pad="60"/>
<connect gate="A" pin="A4" pad="61"/>
<connect gate="A" pin="A5" pad="9"/>
<connect gate="A" pin="A6" pad="10"/>
<connect gate="A" pin="A7" pad="11"/>
<connect gate="A" pin="A8" pad="12"/>
<connect gate="A" pin="A9" pad="13"/>
<connect gate="A" pin="AD0" pad="53"/>
<connect gate="A" pin="AD1" pad="54"/>
<connect gate="A" pin="AD10" pad="37"/>
<connect gate="A" pin="AD11" pad="38"/>
<connect gate="A" pin="AD12" pad="39"/>
<connect gate="A" pin="AD13" pad="40"/>
<connect gate="A" pin="AD14" pad="41"/>
<connect gate="A" pin="AD15" pad="42"/>
<connect gate="A" pin="AD2" pad="55"/>
<connect gate="A" pin="AD3" pad="56"/>
<connect gate="A" pin="AD4" pad="5"/>
<connect gate="A" pin="AD5" pad="6"/>
<connect gate="A" pin="AD6" pad="7"/>
<connect gate="A" pin="AD7" pad="8"/>
<connect gate="A" pin="AD8" pad="35"/>
<connect gate="A" pin="AD9" pad="36"/>
<connect gate="A" pin="CLKOUT" pad="33"/>
<connect gate="A" pin="LEDA" pad="15"/>
<connect gate="A" pin="LEDB" pad="14"/>
<connect gate="A" pin="OSC1" pad="3"/>
<connect gate="A" pin="OSC2" pad="2"/>
<connect gate="A" pin="PSPCFG2" pad="17"/>
<connect gate="A" pin="PSPCFG3" pad="18"/>
<connect gate="A" pin="RBIAS" pad="16"/>
<connect gate="A" pin="SCK/AL/PSPCFG4" pad="52"/>
<connect gate="A" pin="SI/RD/R~W" pad="51"/>
<connect gate="A" pin="SO/WR/WRL/EN/BOSEL" pad="50"/>
<connect gate="A" pin="TPIN+" pad="26"/>
<connect gate="A" pin="TPIN-" pad="27"/>
<connect gate="A" pin="TPOUT+" pad="30"/>
<connect gate="A" pin="TPOUT-" pad="31"/>
<connect gate="A" pin="VCAP" pad="63"/>
<connect gate="A" pin="VDD" pad="64"/>
<connect gate="A" pin="VDDOSC" pad="4"/>
<connect gate="A" pin="VDDPLL" pad="22"/>
<connect gate="A" pin="VDDRX" pad="25"/>
<connect gate="A" pin="VDDTX" pad="28"/>
<connect gate="A" pin="VDD_2" pad="21"/>
<connect gate="A" pin="VDD_3" pad="47"/>
<connect gate="A" pin="VSS" pad="62"/>
<connect gate="A" pin="VSSOSC" pad="1"/>
<connect gate="A" pin="VSSPLL" pad="23"/>
<connect gate="A" pin="VSSRX" pad="24"/>
<connect gate="A" pin="VSSTX" pad="32"/>
<connect gate="A" pin="VSSTX1" pad="29"/>
<connect gate="A" pin="VSS_2" pad="46"/>
<connect gate="A" pin="WRH/B1SEL" pad="48"/>
<connect gate="A" pin="~CS/CS" pad="49"/>
<connect gate="A" pin="~INT/SPISEL" pad="34"/>
</connects>
<technologies>
<technology name="">
<attribute name="DESCRIPTION" value="Stand-Alone 10/100 Ethernet Controller" constant="no"/>
<attribute name="MPN" value="enc624j600-I/pt" constant="no"/>
<attribute name="OC_FARNELL" value="1740227" constant="no"/>
<attribute name="OC_NEWARK" value="07P9123" constant="no"/>
<attribute name="PACKAGE" value="TQFP-64" constant="no"/>
<attribute name="SUPPLIER" value="Microchip" constant="no"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ELLI-MACHXO2-256" prefix="U">
<description>&lt;h3&gt;MachXO2 256 QFN32 ELL-i functions.&lt;/h3&gt;

&lt;p&gt;This device contains a pseudo-symbols, meant to be used with a corresponding MachXO2-256 FPGA device.  The pseudo-symbols list the ELL-i project extra functions for the 32 pins FPGA package. Most of the functions in the QFN32 package are predefined by Lattice, though overrideable by a user design.&lt;/p&gt;

&lt;ul&gt;
   &lt;li&gt;TBD (a link to the relevant design document)&lt;/li&gt;.
&lt;/ul&gt;</description>
<gates>
<gate name="G$1" symbol="ELLI-SMALL-MACHXO2-ALL" x="33.02" y="0"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="FST3257" prefix="U">
<description>&lt;p&gt;
Quad 2:1 Multiplexer / Demultiplexer Bus Switch
&lt;/p&gt;</description>
<gates>
<gate name="G$1" symbol="FST3257" x="0" y="0"/>
</gates>
<devices>
<device name="" package="SOIC-16-NARROW">
<connects>
<connect gate="G$1" pin="!EN" pad="15"/>
<connect gate="G$1" pin="1A" pad="4"/>
<connect gate="G$1" pin="1A0" pad="2"/>
<connect gate="G$1" pin="1A1" pad="3"/>
<connect gate="G$1" pin="2B" pad="7"/>
<connect gate="G$1" pin="2B0" pad="5"/>
<connect gate="G$1" pin="2B1" pad="6"/>
<connect gate="G$1" pin="3C" pad="9"/>
<connect gate="G$1" pin="3C0" pad="11"/>
<connect gate="G$1" pin="3C1" pad="10"/>
<connect gate="G$1" pin="4D" pad="12"/>
<connect gate="G$1" pin="4D0" pad="14"/>
<connect gate="G$1" pin="4D1" pad="13"/>
<connect gate="G$1" pin="GND" pad="8"/>
<connect gate="G$1" pin="S" pad="1"/>
<connect gate="G$1" pin="VCC" pad="16"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32-M-64-LQFP" prefix="U">
<description>STM32F103 Medium Density 64pin LQFP
&lt;br&gt;&lt;br&gt;
&lt;a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf"&gt;Datasheet&lt;/a&gt;</description>
<gates>
<gate name="G$1" symbol="STM32-M-64-LQFP" x="0" y="0"/>
</gates>
<devices>
<device name="" package="LQFP64">
<connects>
<connect gate="G$1" pin="BOOT0" pad="60"/>
<connect gate="G$1" pin="NRST" pad="7"/>
<connect gate="G$1" pin="PA0-WKUP/USART2CTS/ADC0/TIM2CH1ETR" pad="14"/>
<connect gate="G$1" pin="PA1-USART2RTS/ADC1/TIM2CH2" pad="15"/>
<connect gate="G$1" pin="PA10-USART1RX/TIM1CH3" pad="43"/>
<connect gate="G$1" pin="PA11-USART1CTS/CANRX/USBDM/TIM1CH4" pad="44"/>
<connect gate="G$1" pin="PA12-USART1RTS/CANTX/USBDP/TIM1ETR" pad="45"/>
<connect gate="G$1" pin="PA13/JTMS/SWDIO" pad="46"/>
<connect gate="G$1" pin="PA14/JTCK/SWCLK" pad="49"/>
<connect gate="G$1" pin="PA15/JTDI-TIM2CH1ETR/SPI1NSS" pad="50"/>
<connect gate="G$1" pin="PA2-USART2TX/ADC2/TIM2CH3" pad="16"/>
<connect gate="G$1" pin="PA3-USART2RX/ADC3/TIM2CH4" pad="17"/>
<connect gate="G$1" pin="PA4-SPI1NSS/ADC4/USART2CK" pad="20"/>
<connect gate="G$1" pin="PA5-SPI1SCK/ADC5" pad="21"/>
<connect gate="G$1" pin="PA6-SPI1MISO/ADC6/TIM3CH1-TIM1BKIN" pad="22"/>
<connect gate="G$1" pin="PA7-SPI1MOSI/ADC7/TIM3CH2-TIM1CH1N" pad="23"/>
<connect gate="G$1" pin="PA8-USART1CK/MCO/TIM1CH1" pad="41"/>
<connect gate="G$1" pin="PA9-USART1TX/TIM1CH2" pad="42"/>
<connect gate="G$1" pin="PB0-ADC8/TIM3CH3-TIM1CH2N" pad="26"/>
<connect gate="G$1" pin="PB1-ADC9/TIM3CH4-TIM1CH3N" pad="27"/>
<connect gate="G$1" pin="PB10-I2C2SCL/USART3TX-TIM2CH3" pad="29"/>
<connect gate="G$1" pin="PB11-I2C2SDA/USART3RX-TIM2CH4" pad="30"/>
<connect gate="G$1" pin="PB12-SPI2NSS/I2C2SMBAI/USART3CK/TIM1BKIN" pad="33"/>
<connect gate="G$1" pin="PB13-SPI2SCK/USART3CTS/TIM1CH1N" pad="34"/>
<connect gate="G$1" pin="PB14-SPI2MISO/USART3RTS/TIM1CH2N" pad="35"/>
<connect gate="G$1" pin="PB15-SPI2MOSI/TIM1CH3N" pad="36"/>
<connect gate="G$1" pin="PB2/BOOT1" pad="28"/>
<connect gate="G$1" pin="PB3/JTDO--TIM2CH2/TRACESWO/SPI1SCK" pad="55"/>
<connect gate="G$1" pin="PB4/JNTRST--TIM3CH1/SPI1MISO" pad="56"/>
<connect gate="G$1" pin="PB5-I2C1SMBAI-TIM3CH2/SPI1MOSI" pad="57"/>
<connect gate="G$1" pin="PB6-I2C1SCL/TIM4CH1-USART1TX" pad="58"/>
<connect gate="G$1" pin="PB7-I2C1SDA/TIM4CH2-USART1RX" pad="59"/>
<connect gate="G$1" pin="PB8-TIM4CH3-I2C1SCL/CANRX" pad="61"/>
<connect gate="G$1" pin="PB9-TIM4CH4-I2C1SDA/CANTX" pad="62"/>
<connect gate="G$1" pin="PC0-ADC10" pad="8"/>
<connect gate="G$1" pin="PC1-ADC11" pad="9"/>
<connect gate="G$1" pin="PC10--USART3TX" pad="51"/>
<connect gate="G$1" pin="PC11--USART3RX" pad="52"/>
<connect gate="G$1" pin="PC12--USART3CK" pad="53"/>
<connect gate="G$1" pin="PC13-TAMPER-RTC" pad="2"/>
<connect gate="G$1" pin="PC14-OSC32_IN" pad="3"/>
<connect gate="G$1" pin="PC15-OSC32_OUT" pad="4"/>
<connect gate="G$1" pin="PC2-ADC12" pad="10"/>
<connect gate="G$1" pin="PC3-ADC13" pad="11"/>
<connect gate="G$1" pin="PC4-ADC14" pad="24"/>
<connect gate="G$1" pin="PC5-ADC15" pad="25"/>
<connect gate="G$1" pin="PC6-TIM3CH1" pad="37"/>
<connect gate="G$1" pin="PC7-TIM3CH2" pad="38"/>
<connect gate="G$1" pin="PC8-TIM3CH3" pad="39"/>
<connect gate="G$1" pin="PC9-TIM3CH4" pad="40"/>
<connect gate="G$1" pin="PD0-OSC_IN-CANRX" pad="5"/>
<connect gate="G$1" pin="PD1-OSC_OUT-CANTX" pad="6"/>
<connect gate="G$1" pin="PD2-TIM3ETR" pad="54"/>
<connect gate="G$1" pin="VBAT" pad="1"/>
<connect gate="G$1" pin="VDD1" pad="32"/>
<connect gate="G$1" pin="VDD2" pad="48"/>
<connect gate="G$1" pin="VDD3" pad="64"/>
<connect gate="G$1" pin="VDD4" pad="19"/>
<connect gate="G$1" pin="VDDA" pad="13"/>
<connect gate="G$1" pin="VSS1" pad="31"/>
<connect gate="G$1" pin="VSS2" pad="47"/>
<connect gate="G$1" pin="VSS3" pad="63"/>
<connect gate="G$1" pin="VSS4" pad="18"/>
<connect gate="G$1" pin="VSSA" pad="12"/>
</connects>
<technologies>
<technology name="">
<attribute name="PARTNO" value="STM32F103RB" constant="no"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F103R" prefix="U">
<description>STM32F103 Medium Density 64pin LQFP
&lt;br&gt;&lt;br&gt;
&lt;a href="http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00161566.pdf"&gt;Datasheet&lt;/a&gt;</description>
<gates>
<gate name="PA" symbol="STM32-PA" x="-35.56" y="15.24"/>
<gate name="PB" symbol="STM32-PB" x="-2.54" y="15.24"/>
<gate name="PC" symbol="STM32-PC" x="30.48" y="15.24"/>
<gate name="PD_CTL" symbol="STM32F1XX-PD-CTL" x="-25.4" y="-25.4"/>
<gate name="PWR" symbol="STM32F1XX-PWR" x="12.7" y="-33.02"/>
</gates>
<devices>
<device name="T" package="LQFP64">
<connects>
<connect gate="PA" pin="PA0-ADC_IN0" pad="14"/>
<connect gate="PA" pin="PA1-ADC_IN1" pad="15"/>
<connect gate="PA" pin="PA10" pad="43"/>
<connect gate="PA" pin="PA11" pad="44"/>
<connect gate="PA" pin="PA12" pad="45"/>
<connect gate="PA" pin="PA13-SWDIO" pad="46"/>
<connect gate="PA" pin="PA14-SWCLK" pad="49"/>
<connect gate="PA" pin="PA15" pad="50"/>
<connect gate="PA" pin="PA2-ADC_IN2" pad="16"/>
<connect gate="PA" pin="PA3-ADC_IN3" pad="17"/>
<connect gate="PA" pin="PA4-ADC_IN4" pad="20"/>
<connect gate="PA" pin="PA5-ADC_IN5" pad="21"/>
<connect gate="PA" pin="PA6-ADC_IN6" pad="22"/>
<connect gate="PA" pin="PA7-ADC_IN7" pad="23"/>
<connect gate="PA" pin="PA8" pad="41"/>
<connect gate="PA" pin="PA9" pad="42"/>
<connect gate="PB" pin="PB0-ADC_IN8" pad="26"/>
<connect gate="PB" pin="PB1-ADC_IN9" pad="27"/>
<connect gate="PB" pin="PB10" pad="29"/>
<connect gate="PB" pin="PB11" pad="30"/>
<connect gate="PB" pin="PB12" pad="33"/>
<connect gate="PB" pin="PB13" pad="34"/>
<connect gate="PB" pin="PB14" pad="35"/>
<connect gate="PB" pin="PB15" pad="36"/>
<connect gate="PB" pin="PB2" pad="28"/>
<connect gate="PB" pin="PB3" pad="55"/>
<connect gate="PB" pin="PB4" pad="56"/>
<connect gate="PB" pin="PB5" pad="57"/>
<connect gate="PB" pin="PB6" pad="58"/>
<connect gate="PB" pin="PB7" pad="59"/>
<connect gate="PB" pin="PB8" pad="61"/>
<connect gate="PB" pin="PB9" pad="62"/>
<connect gate="PC" pin="PC0-ADC_IN10" pad="8"/>
<connect gate="PC" pin="PC1-ADC_IN11" pad="9"/>
<connect gate="PC" pin="PC10" pad="51"/>
<connect gate="PC" pin="PC11" pad="52"/>
<connect gate="PC" pin="PC12" pad="53"/>
<connect gate="PC" pin="PC13" pad="2"/>
<connect gate="PC" pin="PC14-OSC32_IN" pad="3"/>
<connect gate="PC" pin="PC15-OSC32_OUT" pad="4"/>
<connect gate="PC" pin="PC2-ADC_IN12" pad="10"/>
<connect gate="PC" pin="PC3-ADC_IN13" pad="11"/>
<connect gate="PC" pin="PC4-ADC_IN14" pad="24"/>
<connect gate="PC" pin="PC5-ADC_IN15" pad="25"/>
<connect gate="PC" pin="PC6" pad="37"/>
<connect gate="PC" pin="PC7" pad="38"/>
<connect gate="PC" pin="PC8" pad="39"/>
<connect gate="PC" pin="PC9" pad="40"/>
<connect gate="PD_CTL" pin="BOOT0" pad="60"/>
<connect gate="PD_CTL" pin="NRST" pad="7"/>
<connect gate="PD_CTL" pin="PD0" pad="5"/>
<connect gate="PD_CTL" pin="PD1" pad="6"/>
<connect gate="PD_CTL" pin="PD2" pad="54"/>
<connect gate="PWR" pin="VBAT" pad="1"/>
<connect gate="PWR" pin="VDD1" pad="32"/>
<connect gate="PWR" pin="VDD2" pad="48"/>
<connect gate="PWR" pin="VDD3" pad="64"/>
<connect gate="PWR" pin="VDD4" pad="19"/>
<connect gate="PWR" pin="VDDA" pad="13"/>
<connect gate="PWR" pin="VSS1" pad="31"/>
<connect gate="PWR" pin="VSS2" pad="47"/>
<connect gate="PWR" pin="VSS3" pad="63"/>
<connect gate="PWR" pin="VSS4" pad="18"/>
<connect gate="PWR" pin="VSSA" pad="12"/>
</connects>
<technologies>
<technology name="8">
<attribute name="FLASH" value="64K"/>
</technology>
<technology name="B">
<attribute name="FLASH" value="128K" constant="no"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ENC424J600" prefix="U">
<description>&lt;h3&gt;ENC424J600&lt;/h3&gt;
&lt;p&gt;
The ENC424J600 and ENC624J600 are stand-alone,
Fast Ethernet controllers with an industry standard
Serial Peripheral Interface (SPI) or a flexible parallel
interface. They are designed to serve as an Ethernet
network interface for any microcontroller equipped with
SPI or a standard parallel port
&lt;/p&gt;
&lt;p&gt; Not reviewed. &lt;a href ="http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf"&gt;Datasheet&lt;/a&gt;
&lt;/p&gt;</description>
<gates>
<gate name="ENC424J600" symbol="ENC424J600" x="0" y="0"/>
</gates>
<devices>
<device name="" package="TQFP44-0.8MM">
<connects>
<connect gate="ENC424J600" pin="!CS!/CS" pad="34"/>
<connect gate="ENC424J600" pin="!INT!/SPISEL" pad="24"/>
<connect gate="ENC424J600" pin="AD0" pad="38"/>
<connect gate="ENC424J600" pin="AD1" pad="39"/>
<connect gate="ENC424J600" pin="AD10" pad="27"/>
<connect gate="ENC424J600" pin="AD11" pad="28"/>
<connect gate="ENC424J600" pin="AD12" pad="29"/>
<connect gate="ENC424J600" pin="AD13" pad="30"/>
<connect gate="ENC424J600" pin="AD14" pad="31"/>
<connect gate="ENC424J600" pin="AD2" pad="40"/>
<connect gate="ENC424J600" pin="AD3" pad="41"/>
<connect gate="ENC424J600" pin="AD4" pad="5"/>
<connect gate="ENC424J600" pin="AD5" pad="6"/>
<connect gate="ENC424J600" pin="AD6" pad="7"/>
<connect gate="ENC424J600" pin="AD7" pad="8"/>
<connect gate="ENC424J600" pin="AD8" pad="25"/>
<connect gate="ENC424J600" pin="AD9" pad="26"/>
<connect gate="ENC424J600" pin="CLKOUT" pad="23"/>
<connect gate="ENC424J600" pin="LEDA" pad="10"/>
<connect gate="ENC424J600" pin="LEDB" pad="9"/>
<connect gate="ENC424J600" pin="OSC1" pad="3"/>
<connect gate="ENC424J600" pin="OSC2" pad="2"/>
<connect gate="ENC424J600" pin="PSPCFG0" pad="32"/>
<connect gate="ENC424J600" pin="RBIAS" pad="11"/>
<connect gate="ENC424J600" pin="SCK/AL" pad="37"/>
<connect gate="ENC424J600" pin="SI/RD/!RW" pad="36"/>
<connect gate="ENC424J600" pin="SO/WR/EN" pad="35"/>
<connect gate="ENC424J600" pin="TPIN+" pad="16"/>
<connect gate="ENC424J600" pin="TPIN-" pad="17"/>
<connect gate="ENC424J600" pin="TPOUT+" pad="20"/>
<connect gate="ENC424J600" pin="TPOUT-" pad="21"/>
<connect gate="ENC424J600" pin="VCAP" pad="43"/>
<connect gate="ENC424J600" pin="VDD" pad="44"/>
<connect gate="ENC424J600" pin="VDDOSC" pad="4"/>
<connect gate="ENC424J600" pin="VDDPLL" pad="12"/>
<connect gate="ENC424J600" pin="VDDRX" pad="15"/>
<connect gate="ENC424J600" pin="VDDTX" pad="18"/>
<connect gate="ENC424J600" pin="VSS1" pad="33"/>
<connect gate="ENC424J600" pin="VSS2" pad="42"/>
<connect gate="ENC424J600" pin="VSSOSC" pad="1"/>
<connect gate="ENC424J600" pin="VSSPLL" pad="13"/>
<connect gate="ENC424J600" pin="VSSRX" pad="14"/>
<connect gate="ENC424J600" pin="VSSTX1" pad="19"/>
<connect gate="ENC424J600" pin="VSSTX2" pad="22"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
<compatibility>
<note version="6.3" minversion="6.2.2" severity="warning">
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.
</note>
</compatibility>
</eagle>