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/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.0.99.2 */
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/* Module Version: 5.4 */
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/* Tue Jan 30 17:35:12 2018 */
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/* parameterized module instance */
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codeROM __ (.Address( ), .OutClock( ), .OutClockEn( ), .Reset( ), .Q( ));
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