Apple-2-HW/micro-sci-a2-controller
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Use netclasses for uniformity.

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This commit is contained in:
Christopher RYU 2023-08-26 18:09:45 +09:00
parent c155501112
commit 83f64eddc5
2 changed files with 3714 additions and 3857 deletions
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7494
MicroSci Floppy Controller.kicad_pcb
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77
MicroSci Floppy Controller.kicad_pro
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@ -430,6 +430,40 @@
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1778,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Logic signal",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2032,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1778,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.762,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
@ -437,7 +471,40 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "Logic signal",
"pattern": "Q*"
},
{
"netclass": "Logic signal",
"pattern": "[AD][0-8]"
},
{
"netclass": "Logic signal",
"pattern": "CLOCK_[01]"
},
{
"netclass": "Logic signal",
"pattern": "Net-(U*"
},
{
"netclass": "Logic signal",
"pattern": "R*"
},
{
"netclass": "Logic signal",
"pattern": "FLOPPY*"
},
{
"netclass": "Power",
"pattern": "+5V"
},
{
"netclass": "Power",
"pattern": "+12V"
}
]
},
"pcbnew": {
"last_paths": {
@ -474,6 +541,14 @@
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,