Apple-2-HW/micro-sci-a2-controller
1
0
Fork 0
mirror of https://codeberg.org/cryu/micro-sci-a2-controller synced 2024-11-28 11:51:11 +00:00
Code Issues Packages Projects Releases Wiki Activity
61dc141610
micro-sci-a2-controller/apple2-bus.pretty/Male_Card-Edge_50_pin__100_mil.kicad_mod
Christopher RYU 59aa7096e0 Initial commit.
2023-07-10 05:40:39 +09:00

114 lines
6.9 KiB
Plaintext
Executable File
Raw Blame History

(module Male_Card-Edge_50_pin__100_mil (layer F.Cu) (tedit 5BA10E74)
(descr A2_BUS)
(fp_text reference Ref** (at 0 -5.08) (layer F.SilkS) hide
(effects (font (size 1.016 0.762) (thickness 0.127)))
)
(fp_text value Val** (at 0 5.08) (layer F.SilkS) hide
(effects (font (size 1.016 0.762) (thickness 0.127)))
)
(fp_poly (pts (xy -32.893 -3.81) (xy -31.75 -3.81) (xy -31.75 3.81) (xy -32.893 3.81)) (layer B.Mask) (width 0.001))
(fp_poly (pts (xy -32.893 -3.81) (xy -31.75 -3.81) (xy -31.75 3.81) (xy -32.893 3.81)) (layer F.Mask) (width 0.001))
(fp_poly (pts (xy 32.893 -3.81) (xy 31.75 -3.81) (xy 31.75 3.81) (xy 32.893 3.81)) (layer B.Mask) (width 0.001))
(fp_poly (pts (xy 32.893 -3.81) (xy 31.75 -3.81) (xy 31.75 3.81) (xy 32.893 3.81)) (layer F.Mask) (width 0.001))
(pad 25 smd rect (at 30.48 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 24 smd rect (at 27.94 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 23 smd rect (at 25.4 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 22 smd rect (at 22.86 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 21 smd rect (at 20.32 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 20 smd rect (at 17.78 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 19 smd rect (at 15.24 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 18 smd rect (at 12.7 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 17 smd rect (at 10.16 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 16 smd rect (at 7.62 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 15 smd rect (at 5.08 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 14 smd rect (at 2.54 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 13 smd rect (at 0 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 12 smd rect (at -2.54 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 11 smd rect (at -5.08 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 10 smd rect (at -7.62 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 9 smd rect (at -10.16 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 8 smd rect (at -12.7 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 7 smd rect (at -15.24 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 6 smd rect (at -17.78 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 5 smd rect (at -20.32 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 4 smd rect (at -22.86 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 3 smd rect (at -25.4 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 2 smd rect (at -27.94 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 1 smd rect (at -30.48 0 270) (size 6.35 1.524) (layers F.Cu F.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 26 smd rect (at 30.48 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 27 smd rect (at 27.94 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 28 smd rect (at 25.4 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 29 smd rect (at 22.86 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 30 smd rect (at 20.32 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 31 smd rect (at 17.78 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 32 smd rect (at 15.24 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 33 smd rect (at 12.7 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 34 smd rect (at 10.16 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 35 smd rect (at 7.62 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 36 smd rect (at 5.08 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 37 smd rect (at 2.54 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 38 smd rect (at 0 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 39 smd rect (at -2.54 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 40 smd rect (at -5.08 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 41 smd rect (at -7.62 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 42 smd rect (at -10.16 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 43 smd rect (at -12.7 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 44 smd rect (at -15.24 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 45 smd rect (at -17.78 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 46 smd rect (at -20.32 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 47 smd rect (at -22.86 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 48 smd rect (at -25.4 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 49 smd rect (at -27.94 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
(pad 50 smd rect (at -30.48 0 270) (size 6.35 1.524) (layers B.Cu B.Mask)
(solder_mask_margin 0.65) (clearance 0.254))
)
Reference in New Issue View Git Blame Copy Permalink