Apple-2-HW/unified_retro_keyboard
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unified_retro_keyboard/hardware/interface-ascii-atmega2560/interface-ascii-2560.kicad_pcb

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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(kicad_pcb (version 20171130) (host pcbnew "(5.1.5-0-10_14)")
(general
(thickness 1.6)
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
(drawings 34)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(tracks 1000)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(zones 0)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(modules 49)
(nets 175)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(page B)
(title_block
(title "Unified Retro Keyboard ASCII Interface (2560)")
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(date 2020-04-16)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(rev 3.2)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.254)
(user_trace_width 0.254)
(user_trace_width 0.508)
(user_trace_width 1.27)
(trace_clearance 0.1524)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8128)
(via_drill 0.4064)
(via_min_size 0.4)
(via_min_drill 0.3)
(user_via 1.27 0.7112)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(user_via 1.5748 0.8128)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(uvia_size 0.3048)
(uvia_drill 0.1016)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 3.9878 3.9878)
(pad_drill 3.9878)
(pad_to_mask_clearance 0)
(aux_axis_origin 61.4172 179.1081)
(grid_origin 209.4 88.8)
(visible_elements 7FFFEFFF)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "outputs"))
)
(net 0 "")
(net 1 GND)
(net 2 /Row3)
(net 3 /Row0)
(net 4 /Row1)
(net 5 /Row4)
(net 6 /Row5)
(net 7 /Row7)
(net 8 /D7)
(net 9 /D1)
(net 10 /D2)
(net 11 /D3)
(net 12 /D4)
(net 13 /D5)
(net 14 /D6)
(net 15 /Col0)
(net 16 /Col1)
(net 17 /Col2)
(net 18 /Col3)
(net 19 /Col4)
(net 20 /Col5)
(net 21 /Col6)
(net 22 /Col7)
(net 23 /Row6)
(net 24 /Row2)
(net 25 /D0)
(net 26 /~STROBE)
(net 27 /Row10)
(net 28 /Row9)
(net 29 /Row8)
(net 30 /Row15)
(net 31 /Row14)
(net 32 /Row13)
(net 33 /Row12)
(net 34 /Row11)
(net 35 /Tx)
(net 36 /Rx)
(net 37 "Net-(D11-Pad1)")
(net 38 "Net-(D12-Pad1)")
(net 39 "Net-(D13-Pad1)")
(net 40 "Net-(D14-Pad1)")
(net 41 "Net-(D15-Pad1)")
(net 42 "Net-(D16-Pad1)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 43 "Net-(D20-Pad1)")
(net 44 "Net-(D24-Pad1)")
(net 45 "Net-(D25-Pad1)")
(net 46 "Net-(D26-Pad1)")
(net 47 "Net-(D4-Pad1)")
(net 48 "Net-(D5-Pad1)")
(net 49 "Net-(D6-Pad1)")
(net 50 "Net-(D7-Pad1)")
(net 51 "Net-(D8-Pad1)")
(net 52 "Net-(D9-Pad1)")
(net 53 "Net-(D10-Pad1)")
(net 54 "Net-(D27-Pad1)")
(net 55 /LED1)
(net 56 /OUT1)
(net 57 /OUT2)
(net 58 /OUT3)
(net 59 /LED3)
(net 60 /LED2)
(net 61 "Net-(C1-Pad1)")
(net 62 "Net-(C2-Pad1)")
(net 63 "Net-(D21-Pad1)")
(net 64 "Net-(D22-Pad1)")
(net 65 "Net-(D23-Pad1)")
(net 66 "Net-(J1-Pad9)")
(net 67 "Net-(J1-Pad4)")
(net 68 "Net-(J1-Pad14)")
(net 69 "Net-(J1-Pad15)")
(net 70 "Net-(J1-Pad16)")
(net 71 "Net-(J2-Pad10)")
(net 72 "Net-(J2-Pad11)")
(net 73 "Net-(J2-Pad13)")
(net 74 "Net-(U1-Pad98)")
(net 75 "Net-(U1-Pad97)")
(net 76 "Net-(U1-Pad96)")
(net 77 "Net-(U1-Pad95)")
(net 78 "Net-(U1-Pad94)")
(net 79 "Net-(U1-Pad89)")
(net 80 "Net-(U1-Pad88)")
(net 81 "Net-(U1-Pad87)")
(net 82 "Net-(U1-Pad86)")
(net 83 "Net-(U1-Pad85)")
(net 84 "Net-(U1-Pad84)")
(net 85 "Net-(U1-Pad83)")
(net 86 "Net-(U1-Pad82)")
(net 87 "Net-(U1-Pad70)")
(net 88 "Net-(U1-Pad52)")
(net 89 "Net-(U1-Pad51)")
(net 90 "Net-(U1-Pad47)")
(net 91 "Net-(U1-Pad46)")
(net 92 "Net-(U1-Pad45)")
(net 93 "Net-(U1-Pad44)")
(net 94 "Net-(U1-Pad43)")
(net 95 "Net-(U1-Pad42)")
(net 96 "Net-(U1-Pad41)")
(net 97 "Net-(U1-Pad40)")
(net 98 "Net-(U1-Pad39)")
(net 99 "Net-(U1-Pad38)")
(net 100 "Net-(U1-Pad37)")
(net 101 "Net-(U1-Pad36)")
(net 102 "Net-(U1-Pad35)")
(net 103 "Net-(U1-Pad29)")
(net 104 "Net-(U1-Pad28)")
(net 105 "Net-(U1-Pad19)")
(net 106 "Net-(U1-Pad9)")
(net 107 "Net-(U1-Pad8)")
(net 108 "Net-(U1-Pad7)")
(net 109 "Net-(U1-Pad6)")
(net 110 "Net-(U1-Pad5)")
(net 111 "Net-(U1-Pad4)")
(net 112 "Net-(U1-Pad1)")
(net 113 VCC)
(net 114 "Net-(J8-Pad1)")
(net 115 "Net-(J8-Pad9)")
(net 116 "Net-(J8-Pad2)")
(net 117 "Net-(J8-Pad10)")
(net 118 "Net-(J8-Pad3)")
(net 119 "Net-(J8-Pad11)")
(net 120 "Net-(J8-Pad4)")
(net 121 "Net-(J8-Pad12)")
(net 122 "Net-(J8-Pad5)")
(net 123 "Net-(J8-Pad13)")
(net 124 "Net-(J8-Pad6)")
(net 125 "Net-(J8-Pad14)")
(net 126 "Net-(J8-Pad7)")
(net 127 "Net-(J8-Pad15)")
(net 128 "Net-(J8-Pad8)")
(net 129 "Net-(J8-Pad16)")
(net 130 /TDI)
(net 131 "Net-(J6-Pad8)")
(net 132 "Net-(J6-Pad7)")
(net 133 /~RESET)
(net 134 /TMS)
(net 135 /TDO)
(net 136 /TCK)
(net 137 "Net-(U1-Pad22)")
(net 138 "Net-(U1-Pad21)")
(net 139 "Net-(U1-Pad20)")
(net 140 "Net-(D1-Pad1)")
(net 141 "Net-(D2-Pad1)")
(net 142 "Net-(D3-Pad1)")
(net 143 "Net-(D17-Pad2)")
(net 144 "Net-(D18-Pad2)")
(net 145 "Net-(D19-Pad2)")
(net 146 "Net-(J7-Pad1)")
(net 147 "Net-(J7-Pad9)")
(net 148 "Net-(J7-Pad2)")
(net 149 "Net-(J7-Pad10)")
(net 150 "Net-(J7-Pad3)")
(net 151 "Net-(J7-Pad11)")
(net 152 "Net-(J7-Pad4)")
(net 153 "Net-(J7-Pad12)")
(net 154 "Net-(J7-Pad5)")
(net 155 "Net-(J7-Pad13)")
(net 156 "Net-(J7-Pad6)")
(net 157 "Net-(J7-Pad14)")
(net 158 "Net-(J7-Pad7)")
(net 159 "Net-(J7-Pad15)")
(net 160 "Net-(J7-Pad8)")
(net 161 "Net-(J7-Pad16)")
(net 162 "Net-(J10-Pad32)")
(net 163 "Net-(J10-Pad30)")
(net 164 "Net-(J10-Pad28)")
(net 165 "Net-(J10-Pad26)")
(net 166 "Net-(J8-Pad25)")
(net 167 "Net-(J8-Pad24)")
(net 168 "Net-(J8-Pad23)")
(net 169 "Net-(J8-Pad22)")
(net 170 "Net-(J8-Pad21)")
(net 171 "Net-(J8-Pad20)")
(net 172 "Net-(J8-Pad19)")
(net 173 "Net-(J8-Pad18)")
(net 174 "Net-(J8-Pad17)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(net_class Default "This is the default net class."
(clearance 0.1524)
(trace_width 0.254)
(via_dia 0.8128)
(via_drill 0.4064)
(uvia_dia 0.3048)
(uvia_drill 0.1016)
(diff_pair_width 0.2032)
(diff_pair_gap 0.254)
(add_net /Col1)
(add_net /Col2)
(add_net /Col3)
(add_net /Col4)
(add_net /Col5)
(add_net /Col6)
(add_net /Col7)
(add_net /D0)
(add_net /D1)
(add_net /D2)
(add_net /D3)
(add_net /D4)
(add_net /D5)
(add_net /D6)
(add_net /D7)
(add_net /LED1)
(add_net /LED2)
(add_net /LED3)
(add_net /OUT1)
(add_net /OUT2)
(add_net /OUT3)
(add_net /Row0)
(add_net /Row1)
(add_net /Row10)
(add_net /Row11)
(add_net /Row12)
(add_net /Row13)
(add_net /Row14)
(add_net /Row15)
(add_net /Row2)
(add_net /Row3)
(add_net /Row4)
(add_net /Row5)
(add_net /Row6)
(add_net /Row7)
(add_net /Row8)
(add_net /Row9)
(add_net /Rx)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net /TCK)
(add_net /TDI)
(add_net /TDO)
(add_net /TMS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net /Tx)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net /~RESET)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net /~STROBE)
(add_net "Net-(C1-Pad1)")
(add_net "Net-(C2-Pad1)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(D1-Pad1)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net "Net-(D10-Pad1)")
(add_net "Net-(D11-Pad1)")
(add_net "Net-(D12-Pad1)")
(add_net "Net-(D13-Pad1)")
(add_net "Net-(D14-Pad1)")
(add_net "Net-(D15-Pad1)")
(add_net "Net-(D16-Pad1)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(D17-Pad2)")
(add_net "Net-(D18-Pad2)")
(add_net "Net-(D19-Pad2)")
(add_net "Net-(D2-Pad1)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net "Net-(D20-Pad1)")
(add_net "Net-(D21-Pad1)")
(add_net "Net-(D22-Pad1)")
(add_net "Net-(D23-Pad1)")
(add_net "Net-(D24-Pad1)")
(add_net "Net-(D25-Pad1)")
(add_net "Net-(D26-Pad1)")
(add_net "Net-(D27-Pad1)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(D3-Pad1)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net "Net-(D4-Pad1)")
(add_net "Net-(D5-Pad1)")
(add_net "Net-(D6-Pad1)")
(add_net "Net-(D7-Pad1)")
(add_net "Net-(D8-Pad1)")
(add_net "Net-(D9-Pad1)")
(add_net "Net-(J1-Pad14)")
(add_net "Net-(J1-Pad15)")
(add_net "Net-(J1-Pad16)")
(add_net "Net-(J1-Pad4)")
(add_net "Net-(J1-Pad9)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(J10-Pad26)")
(add_net "Net-(J10-Pad28)")
(add_net "Net-(J10-Pad30)")
(add_net "Net-(J10-Pad32)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net "Net-(J2-Pad10)")
(add_net "Net-(J2-Pad11)")
(add_net "Net-(J2-Pad13)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(J6-Pad7)")
(add_net "Net-(J6-Pad8)")
(add_net "Net-(J7-Pad1)")
(add_net "Net-(J7-Pad10)")
(add_net "Net-(J7-Pad11)")
(add_net "Net-(J7-Pad12)")
(add_net "Net-(J7-Pad13)")
(add_net "Net-(J7-Pad14)")
(add_net "Net-(J7-Pad15)")
(add_net "Net-(J7-Pad16)")
(add_net "Net-(J7-Pad2)")
(add_net "Net-(J7-Pad3)")
(add_net "Net-(J7-Pad4)")
(add_net "Net-(J7-Pad5)")
(add_net "Net-(J7-Pad6)")
(add_net "Net-(J7-Pad7)")
(add_net "Net-(J7-Pad8)")
(add_net "Net-(J7-Pad9)")
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(add_net "Net-(J8-Pad1)")
(add_net "Net-(J8-Pad10)")
(add_net "Net-(J8-Pad11)")
(add_net "Net-(J8-Pad12)")
(add_net "Net-(J8-Pad13)")
(add_net "Net-(J8-Pad14)")
(add_net "Net-(J8-Pad15)")
(add_net "Net-(J8-Pad16)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(J8-Pad17)")
(add_net "Net-(J8-Pad18)")
(add_net "Net-(J8-Pad19)")
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(add_net "Net-(J8-Pad2)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(J8-Pad20)")
(add_net "Net-(J8-Pad21)")
(add_net "Net-(J8-Pad22)")
(add_net "Net-(J8-Pad23)")
(add_net "Net-(J8-Pad24)")
(add_net "Net-(J8-Pad25)")
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(add_net "Net-(J8-Pad3)")
(add_net "Net-(J8-Pad4)")
(add_net "Net-(J8-Pad5)")
(add_net "Net-(J8-Pad6)")
(add_net "Net-(J8-Pad7)")
(add_net "Net-(J8-Pad8)")
(add_net "Net-(J8-Pad9)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net "Net-(U1-Pad1)")
(add_net "Net-(U1-Pad19)")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(add_net "Net-(U1-Pad20)")
(add_net "Net-(U1-Pad21)")
(add_net "Net-(U1-Pad22)")
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(add_net "Net-(U1-Pad28)")
(add_net "Net-(U1-Pad29)")
(add_net "Net-(U1-Pad35)")
(add_net "Net-(U1-Pad36)")
(add_net "Net-(U1-Pad37)")
(add_net "Net-(U1-Pad38)")
(add_net "Net-(U1-Pad39)")
(add_net "Net-(U1-Pad4)")
(add_net "Net-(U1-Pad40)")
(add_net "Net-(U1-Pad41)")
(add_net "Net-(U1-Pad42)")
(add_net "Net-(U1-Pad43)")
(add_net "Net-(U1-Pad44)")
(add_net "Net-(U1-Pad45)")
(add_net "Net-(U1-Pad46)")
(add_net "Net-(U1-Pad47)")
(add_net "Net-(U1-Pad5)")
(add_net "Net-(U1-Pad51)")
(add_net "Net-(U1-Pad52)")
(add_net "Net-(U1-Pad6)")
(add_net "Net-(U1-Pad7)")
(add_net "Net-(U1-Pad70)")
(add_net "Net-(U1-Pad8)")
(add_net "Net-(U1-Pad82)")
(add_net "Net-(U1-Pad83)")
(add_net "Net-(U1-Pad84)")
(add_net "Net-(U1-Pad85)")
(add_net "Net-(U1-Pad86)")
(add_net "Net-(U1-Pad87)")
(add_net "Net-(U1-Pad88)")
(add_net "Net-(U1-Pad89)")
(add_net "Net-(U1-Pad9)")
(add_net "Net-(U1-Pad94)")
(add_net "Net-(U1-Pad95)")
(add_net "Net-(U1-Pad96)")
(add_net "Net-(U1-Pad97)")
(add_net "Net-(U1-Pad98)")
(add_net VCC)
)
(net_class power1 ""
(clearance 0.1524)
(trace_width 1.27)
(via_dia 1.27)
(via_drill 0.7112)
(uvia_dia 0.3048)
(uvia_drill 0.1016)
(diff_pair_width 0.2032)
(diff_pair_gap 0.254)
(add_net GND)
)
(net_class signal ""
(clearance 0.1524)
(trace_width 0.254)
(via_dia 0.8128)
(via_drill 0.4064)
(uvia_dia 0.3048)
(uvia_drill 0.1016)
(diff_pair_width 0.2032)
(diff_pair_gap 0.254)
(add_net /Col0)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E914798)
(at 227.33 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5F1EFEF1)
(fp_text reference D15 (at 3.81 -2.12 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 41 "Net-(D15-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 /Row12))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E914625)
(at 229.87 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5F1EFEEB)
(fp_text reference D6 (at 3.81 -2.12 90) (layer F.SilkS)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 "Net-(D6-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 /Row11))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E914779)
(at 232.41 160.0724 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(path /5F1EFEE5)
(fp_text reference D14 (at 3.81 -2.12 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 40 "Net-(D14-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 27 /Row10))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E914606)
(at 234.95 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5F1EFEDF)
(fp_text reference D5 (at 3.81 -2.12 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(D5-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 /Row9))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E91475A)
(at 237.49 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5F1EFED9)
(fp_text reference D13 (at 3.81 -2.12 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 "Net-(D13-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E92C263)
(at 242.57 160.0724 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(path /5F1EFF03)
(fp_text reference D8 (at 3.81 -2.12 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 51 "Net-(D8-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 /Row15))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E914644)
(at 224.79 160.0724 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(path /5F1EFEF7)
(fp_text reference D7 (at 3.81 -2.12 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 50 "Net-(D7-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 /Row13))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5E9147B7)
(at 222.25 160.0724 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(path /5F1EFEFD)
(fp_text reference D16 (at 3.81 -2.12 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 42 "Net-(D16-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /Row14))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:ExpansionHeader_1x25_P2.54 (layer F.Cu) (tedit 5EB486EF) (tstamp 5EB55E58)
(at 168.252 107.596)
(descr "Through hole straight pin header, 1x15, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x15 2.54mm single row")
(path /5F355459)
(fp_text reference J8 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x25 (at 0 64.77) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 43 (at 2.54 43.18 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 17.78 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 43.18 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.81 62.23) (end -1.27 62.23) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 62.29) (end 3.87 62.29) (layer F.SilkS) (width 0.12))
(fp_line (start 0 40.64) (end 2.54 40.64) (layer F.Cu) (width 0.254))
(fp_line (start 0 43.18) (end 2.54 43.18) (layer F.Cu) (width 0.254))
(fp_line (start 0 38.1) (end 2.54 38.1) (layer F.Cu) (width 0.254))
(fp_line (start 0 48.26) (end 2.54 48.26) (layer F.Cu) (width 0.254))
(fp_line (start 0 45.72) (end 2.54 45.72) (layer F.Cu) (width 0.254))
(fp_line (start 0 53.34) (end 2.54 53.34) (layer F.Cu) (width 0.254))
(fp_line (start 0 55.88) (end 2.54 55.88) (layer F.Cu) (width 0.254))
(fp_line (start 0 50.8) (end 2.54 50.8) (layer F.Cu) (width 0.254))
(fp_line (start 0 60.96) (end 2.54 60.96) (layer F.Cu) (width 0.254))
(fp_line (start 0 58.42) (end 2.54 58.42) (layer F.Cu) (width 0.254))
(fp_line (start 0 33.02) (end 2.54 33.02) (layer F.Cu) (width 0.254))
(fp_line (start 0 35.56) (end 2.54 35.56) (layer F.Cu) (width 0.254))
(fp_line (start 0 25.4) (end 2.54 25.4) (layer F.Cu) (width 0.254))
(fp_line (start 0 30.48) (end 2.54 30.48) (layer F.Cu) (width 0.254))
(fp_line (start 0 27.94) (end 2.54 27.94) (layer F.Cu) (width 0.254))
(fp_line (start 0 20.32) (end 2.54 20.32) (layer F.Cu) (width 0.254))
(fp_line (start 0 22.86) (end 2.54 22.86) (layer F.Cu) (width 0.254))
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(module Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Horizontal (layer F.Cu) (tedit 59FED5CB) (tstamp 5EB30A7F)
(at 177.142 97.182 180)
(descr "Through hole angled pin header, 2x05, 2.54mm pitch, 6mm pin length, double rows")
(tags "Through hole angled pin header THT 2x05 2.54mm double row")
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value Conn_01x10 (at 5.655 12.43) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user %R (at 5.31 5.08 90) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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(pad 10 thru_hole oval (at 2.54 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(pad 9 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 130 /TDI))
(pad 8 thru_hole oval (at 2.54 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 131 "Net-(J6-Pad8)"))
(pad 7 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 132 "Net-(J6-Pad7)"))
(pad 6 thru_hole oval (at 2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 133 /~RESET))
(pad 5 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 134 /TMS))
(pad 4 thru_hole oval (at 2.54 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 113 VCC))
(pad 3 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 135 /TDO))
(pad 2 thru_hole oval (at 2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 136 /TCK))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x05_P2.54mm_Horizontal.wrl
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module "" (layer F.Cu) (tedit 0) (tstamp 0)
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value "" (at 225.275 102.77) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user "Apple 1" (at 228.323 102.77 90) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
)
(module unikbd:DIP-16_W7.62mm_Proto (layer F.Cu) (tedit 5E98D090) (tstamp 5E99C2BE)
(at 225.275 102.77 90)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket")
(path /5E9AC1D6)
(fp_text reference J7 (at 8.255 -3.175 180) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value "Custom Connector 1 / Proto" (at 3.81 20.11 90) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_line (start 10.16 17.78) (end 7.62 17.78) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 15.24) (end 7.62 15.24) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 12.7) (end 7.62 12.7) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 10.16) (end 7.62 10.16) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 7.62) (end 7.62 7.62) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 5.08) (end 7.62 5.08) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 2.54) (end 7.62 2.54) (layer F.Cu) (width 1.27))
(fp_line (start 10.16 0) (end 7.62 0) (layer F.Cu) (width 1.27))
(fp_line (start 0 0) (end -2.54 0) (layer F.Cu) (width 1.27))
(fp_line (start 0 2.54) (end -2.54 2.54) (layer F.Cu) (width 1.27))
(fp_line (start 0 5.08) (end -2.54 5.08) (layer F.Cu) (width 1.27))
(fp_line (start 0 7.62) (end -2.54 7.62) (layer F.Cu) (width 1.27))
(fp_line (start 0 10.16) (end -2.54 10.16) (layer F.Cu) (width 1.27))
(fp_line (start 0 12.7) (end -2.54 12.7) (layer F.Cu) (width 1.27))
(fp_line (start 0 15.24) (end -2.54 15.24) (layer F.Cu) (width 1.27))
(fp_line (start 0 17.78) (end -2.54 17.78) (layer F.Cu) (width 1.27))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 19.11) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 19.11) (end 8.89 19.11) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 19.11) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 19.17) (end 8.95 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start 8.95 19.17) (end 8.95 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 8.95 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.55 -1.6) (end -1.55 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 19.4) (end 9.15 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 19.4) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(pad 46 thru_hole oval (at 10.16 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 45 thru_hole oval (at -2.54 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 42 thru_hole oval (at 10.16 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 41 thru_hole oval (at -2.54 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 38 thru_hole oval (at 10.16 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 37 thru_hole oval (at -2.54 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 34 thru_hole oval (at 10.16 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 33 thru_hole oval (at -2.54 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 30 thru_hole oval (at 10.16 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 29 thru_hole oval (at -2.54 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 26 thru_hole oval (at 10.16 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 25 thru_hole oval (at -2.54 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 22 thru_hole oval (at 10.16 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 21 thru_hole oval (at -2.54 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 18 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 17 thru_hole oval (at -2.54 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 146 "Net-(J7-Pad1)"))
(pad 9 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 147 "Net-(J7-Pad9)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 148 "Net-(J7-Pad2)"))
(pad 10 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 149 "Net-(J7-Pad10)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 150 "Net-(J7-Pad3)"))
(pad 11 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 151 "Net-(J7-Pad11)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 152 "Net-(J7-Pad4)"))
(pad 12 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 153 "Net-(J7-Pad12)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 154 "Net-(J7-Pad5)"))
(pad 13 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 155 "Net-(J7-Pad13)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 156 "Net-(J7-Pad6)"))
(pad 14 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 157 "Net-(J7-Pad14)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 158 "Net-(J7-Pad7)"))
(pad 15 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 159 "Net-(J7-Pad15)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 160 "Net-(J7-Pad8)"))
(pad 16 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 161 "Net-(J7-Pad16)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm_Socket.wrl
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1B415)
(at 240.03 160.0724 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(path /5E316F0B)
(fp_text reference D4 (at 3.81 -2.12 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 47 "Net-(D4-Pad1)"))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 /Row7))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module Package_QFP:TQFP-100_14x14mm_P0.5mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 5E914DAB)
(at 207.876 116.74 270)
(descr "TQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py")
(tags "TQFP QFP")
(path /5EC4527C)
(clearance 0.0508)
(attr smd)
(fp_text reference U1 (at 0 -9.35 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value ATmega2560-16AU (at 0 9.35 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.65 6.4) (end 8.65 0) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.25 6.4) (end 8.65 6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.25 7.25) (end 7.25 6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.4 7.25) (end 7.25 7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.4 8.65) (end 6.4 7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 8.65) (end 6.4 8.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -8.65 6.4) (end -8.65 0) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.25 6.4) (end -8.65 6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.25 7.25) (end -7.25 6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.4 7.25) (end -7.25 7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.4 8.65) (end -6.4 7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 8.65) (end -6.4 8.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.65 -6.4) (end 8.65 0) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.25 -6.4) (end 8.65 -6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.25 -7.25) (end 7.25 -6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.4 -7.25) (end 7.25 -7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.4 -8.65) (end 6.4 -7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -8.65) (end 6.4 -8.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -8.65 -6.4) (end -8.65 0) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.25 -6.4) (end -8.65 -6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.25 -7.25) (end -7.25 -6.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.4 -7.25) (end -7.25 -7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.4 -8.65) (end -6.4 -7.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -8.65) (end -6.4 -8.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -7 -6) (end -6 -7) (layer F.Fab) (width 0.1))
(fp_line (start -7 7) (end -7 -6) (layer F.Fab) (width 0.1))
(fp_line (start 7 7) (end -7 7) (layer F.Fab) (width 0.1))
(fp_line (start 7 -7) (end 7 7) (layer F.Fab) (width 0.1))
(fp_line (start -6 -7) (end 7 -7) (layer F.Fab) (width 0.1))
(fp_line (start -7.11 -6.41) (end -8.4 -6.41) (layer F.SilkS) (width 0.12))
(fp_line (start -7.11 -7.11) (end -7.11 -6.41) (layer F.SilkS) (width 0.12))
(fp_line (start -6.41 -7.11) (end -7.11 -7.11) (layer F.SilkS) (width 0.12))
(fp_line (start 7.11 -7.11) (end 7.11 -6.41) (layer F.SilkS) (width 0.12))
(fp_line (start 6.41 -7.11) (end 7.11 -7.11) (layer F.SilkS) (width 0.12))
(fp_line (start -7.11 7.11) (end -7.11 6.41) (layer F.SilkS) (width 0.12))
(fp_line (start -6.41 7.11) (end -7.11 7.11) (layer F.SilkS) (width 0.12))
(fp_line (start 7.11 7.11) (end 7.11 6.41) (layer F.SilkS) (width 0.12))
(fp_line (start 6.41 7.11) (end 7.11 7.11) (layer F.SilkS) (width 0.12))
(pad 100 smd roundrect (at -6 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 113 VCC))
(pad 99 smd roundrect (at -5.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 GND))
(pad 98 smd roundrect (at -5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 74 "Net-(U1-Pad98)"))
(pad 97 smd roundrect (at -4.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 75 "Net-(U1-Pad97)"))
(pad 96 smd roundrect (at -4 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 76 "Net-(U1-Pad96)"))
(pad 95 smd roundrect (at -3.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 77 "Net-(U1-Pad95)"))
(pad 94 smd roundrect (at -3 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 78 "Net-(U1-Pad94)"))
(pad 93 smd roundrect (at -2.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 136 /TCK))
(pad 92 smd roundrect (at -2 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 134 /TMS))
(pad 91 smd roundrect (at -1.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 135 /TDO))
(pad 90 smd roundrect (at -1 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 130 /TDI))
(pad 89 smd roundrect (at -0.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 79 "Net-(U1-Pad89)"))
(pad 88 smd roundrect (at 0 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 80 "Net-(U1-Pad88)"))
(pad 87 smd roundrect (at 0.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 81 "Net-(U1-Pad87)"))
(pad 86 smd roundrect (at 1 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 82 "Net-(U1-Pad86)"))
(pad 85 smd roundrect (at 1.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 83 "Net-(U1-Pad85)"))
(pad 84 smd roundrect (at 2 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 84 "Net-(U1-Pad84)"))
(pad 83 smd roundrect (at 2.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 85 "Net-(U1-Pad83)"))
(pad 82 smd roundrect (at 3 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 86 "Net-(U1-Pad82)"))
(pad 81 smd roundrect (at 3.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 GND))
(pad 80 smd roundrect (at 4 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 113 VCC))
(pad 79 smd roundrect (at 4.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 47 "Net-(D4-Pad1)"))
(pad 78 smd roundrect (at 5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 39 "Net-(D13-Pad1)"))
(pad 77 smd roundrect (at 5.5 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 48 "Net-(D5-Pad1)"))
(pad 76 smd roundrect (at 6 -7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 40 "Net-(D14-Pad1)"))
(pad 75 smd roundrect (at 7.6625 -6 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 49 "Net-(D6-Pad1)"))
(pad 74 smd roundrect (at 7.6625 -5.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 41 "Net-(D15-Pad1)"))
(pad 73 smd roundrect (at 7.6625 -5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 50 "Net-(D7-Pad1)"))
(pad 72 smd roundrect (at 7.6625 -4.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 42 "Net-(D16-Pad1)"))
(pad 71 smd roundrect (at 7.6625 -4 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 51 "Net-(D8-Pad1)"))
(pad 70 smd roundrect (at 7.6625 -3.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 87 "Net-(U1-Pad70)"))
(pad 69 smd roundrect (at 7.6625 -3 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 38 "Net-(D12-Pad1)"))
(pad 68 smd roundrect (at 7.6625 -2.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 142 "Net-(D3-Pad1)"))
(pad 67 smd roundrect (at 7.6625 -2 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 37 "Net-(D11-Pad1)"))
(pad 66 smd roundrect (at 7.6625 -1.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 141 "Net-(D2-Pad1)"))
(pad 65 smd roundrect (at 7.6625 -1 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 53 "Net-(D10-Pad1)"))
(pad 64 smd roundrect (at 7.6625 -0.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 140 "Net-(D1-Pad1)"))
(pad 63 smd roundrect (at 7.6625 0 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 52 "Net-(D9-Pad1)"))
(pad 62 smd roundrect (at 7.6625 0.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 GND))
(pad 61 smd roundrect (at 7.6625 1 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 113 VCC))
(pad 60 smd roundrect (at 7.6625 1.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 22 /Col7))
(pad 59 smd roundrect (at 7.6625 2 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 21 /Col6))
(pad 58 smd roundrect (at 7.6625 2.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 20 /Col5))
(pad 57 smd roundrect (at 7.6625 3 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 19 /Col4))
(pad 56 smd roundrect (at 7.6625 3.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 18 /Col3))
(pad 55 smd roundrect (at 7.6625 4 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 17 /Col2))
(pad 54 smd roundrect (at 7.6625 4.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 16 /Col1))
(pad 53 smd roundrect (at 7.6625 5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 15 /Col0))
(pad 52 smd roundrect (at 7.6625 5.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 88 "Net-(U1-Pad52)"))
(pad 51 smd roundrect (at 7.6625 6 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 89 "Net-(U1-Pad51)"))
(pad 50 smd roundrect (at 6 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 59 /LED3))
(pad 49 smd roundrect (at 5.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 60 /LED2))
(pad 48 smd roundrect (at 5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 55 /LED1))
(pad 47 smd roundrect (at 4.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 90 "Net-(U1-Pad47)"))
(pad 46 smd roundrect (at 4 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 91 "Net-(U1-Pad46)"))
(pad 45 smd roundrect (at 3.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 92 "Net-(U1-Pad45)"))
(pad 44 smd roundrect (at 3 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 93 "Net-(U1-Pad44)"))
(pad 43 smd roundrect (at 2.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 94 "Net-(U1-Pad43)"))
(pad 42 smd roundrect (at 2 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 95 "Net-(U1-Pad42)"))
(pad 41 smd roundrect (at 1.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 96 "Net-(U1-Pad41)"))
(pad 40 smd roundrect (at 1 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 97 "Net-(U1-Pad40)"))
(pad 39 smd roundrect (at 0.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 98 "Net-(U1-Pad39)"))
(pad 38 smd roundrect (at 0 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 99 "Net-(U1-Pad38)"))
(pad 37 smd roundrect (at -0.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 100 "Net-(U1-Pad37)"))
(pad 36 smd roundrect (at -1 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 101 "Net-(U1-Pad36)"))
(pad 35 smd roundrect (at -1.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 102 "Net-(U1-Pad35)"))
(pad 34 smd roundrect (at -2 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 61 "Net-(C1-Pad1)"))
(pad 33 smd roundrect (at -2.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 62 "Net-(C2-Pad1)"))
(pad 32 smd roundrect (at -3 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 GND))
(pad 31 smd roundrect (at -3.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 113 VCC))
(pad 30 smd roundrect (at -4 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 133 /~RESET))
(pad 29 smd roundrect (at -4.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 103 "Net-(U1-Pad29)"))
(pad 28 smd roundrect (at -5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 104 "Net-(U1-Pad28)"))
(pad 27 smd roundrect (at -5.5 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 8 /D7))
(pad 26 smd roundrect (at -6 7.6625 270) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 58 /OUT3))
(pad 25 smd roundrect (at -7.6625 6 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 57 /OUT2))
(pad 24 smd roundrect (at -7.6625 5.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 56 /OUT1))
(pad 23 smd roundrect (at -7.6625 5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 26 /~STROBE))
(pad 22 smd roundrect (at -7.6625 4.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 137 "Net-(U1-Pad22)"))
(pad 21 smd roundrect (at -7.6625 4 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 138 "Net-(U1-Pad21)"))
(pad 20 smd roundrect (at -7.6625 3.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 139 "Net-(U1-Pad20)"))
(pad 19 smd roundrect (at -7.6625 3 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 105 "Net-(U1-Pad19)"))
(pad 18 smd roundrect (at -7.6625 2.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 14 /D6))
(pad 17 smd roundrect (at -7.6625 2 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 13 /D5))
(pad 16 smd roundrect (at -7.6625 1.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 12 /D4))
(pad 15 smd roundrect (at -7.6625 1 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 11 /D3))
(pad 14 smd roundrect (at -7.6625 0.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 10 /D2))
(pad 13 smd roundrect (at -7.6625 0 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 9 /D1))
(pad 12 smd roundrect (at -7.6625 -0.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 25 /D0))
(pad 11 smd roundrect (at -7.6625 -1 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 GND))
(pad 10 smd roundrect (at -7.6625 -1.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 113 VCC))
(pad 9 smd roundrect (at -7.6625 -2 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 106 "Net-(U1-Pad9)"))
(pad 8 smd roundrect (at -7.6625 -2.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 107 "Net-(U1-Pad8)"))
(pad 7 smd roundrect (at -7.6625 -3 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 108 "Net-(U1-Pad7)"))
(pad 6 smd roundrect (at -7.6625 -3.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 109 "Net-(U1-Pad6)"))
(pad 5 smd roundrect (at -7.6625 -4 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 110 "Net-(U1-Pad5)"))
(pad 4 smd roundrect (at -7.6625 -4.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 111 "Net-(U1-Pad4)"))
(pad 3 smd roundrect (at -7.6625 -5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 35 /Tx))
(pad 2 smd roundrect (at -7.6625 -5.5 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 36 /Rx))
(pad 1 smd roundrect (at -7.6625 -6 270) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 112 "Net-(U1-Pad1)"))
(model ${KISYS3DMOD}/Package_QFP.3dshapes/TQFP-100_14x14mm_P0.5mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Crystal:Crystal_SMD_HC49-SD_HandSoldering (layer F.Cu) (tedit 5A1AD52C) (tstamp 5E9204E5)
(at 187.81 115.47 270)
(descr "SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, hand-soldering, 11.4x4.7mm^2 package")
(tags "SMD SMT crystal hand-soldering")
(path /5EA2E720)
(attr smd)
(fp_text reference Y1 (at 0 -3.55 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "16.000 MHz" (at 0 3.55 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.015 0) (end 3.015 -2.115) (angle 180) (layer F.Fab) (width 0.1))
(fp_arc (start -3.015 0) (end -3.015 -2.115) (angle -180) (layer F.Fab) (width 0.1))
(fp_line (start 10.2 -2.6) (end -10.2 -2.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.2 2.6) (end 10.2 -2.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -10.2 2.6) (end 10.2 2.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -10.2 -2.6) (end -10.2 2.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -10.075 2.55) (end 5.9 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start -10.075 -2.55) (end -10.075 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 5.9 -2.55) (end -10.075 -2.55) (layer F.SilkS) (width 0.12))
(fp_line (start -3.015 2.115) (end 3.015 2.115) (layer F.Fab) (width 0.1))
(fp_line (start -3.015 -2.115) (end 3.015 -2.115) (layer F.Fab) (width 0.1))
(fp_line (start 5.7 -2.35) (end -5.7 -2.35) (layer F.Fab) (width 0.1))
(fp_line (start 5.7 2.35) (end 5.7 -2.35) (layer F.Fab) (width 0.1))
(fp_line (start -5.7 2.35) (end 5.7 2.35) (layer F.Fab) (width 0.1))
(fp_line (start -5.7 -2.35) (end -5.7 2.35) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 0.508 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 smd rect (at 5.9375 0 270) (size 7.875 2) (layers F.Cu F.Paste F.Mask)
(net 61 "Net-(C1-Pad1)"))
(pad 1 smd rect (at -5.9375 0 270) (size 7.875 2) (layers F.Cu F.Paste F.Mask)
(net 62 "Net-(C2-Pad1)"))
(model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_HC49-SD.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5EB33341)
(at 198.0335 98.833 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /5E9E37FE)
(fp_text reference R1 (at 9.3345 2.286) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text value 10k (at 5.08 2.37) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text user %R (at 5.08 0) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.21 1.5) (end 11.21 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.12 0) (end 8.35 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 -1.37) (end 1.81 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 8.35 1.37) (end 8.35 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 1.37) (end 8.35 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 1.81 -1.37) (end 1.81 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 133 /~RESET))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 113 VCC))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5E91453E)
(at 211.305 104.421 180)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5DF5B37D)
(fp_text reference C6 (at 1.25 -2.05) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0.1 uF" (at 1.25 2.05) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5E91452D)
(at 193.398 114.16 90)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5EA526AF)
(fp_text reference C2 (at 1.25 -2.05 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 36pf (at 1.25 2.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 62 "Net-(C2-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5EB31138)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at 219.433 121.2485 90)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5DD6A5C6)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference C5 (at -2.032 -70.2945 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0.1 uF" (at 1.25 2.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5E91450B)
(at 193.398 118.137 270)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5EA513C7)
(fp_text reference C1 (at 1.25 -2.05 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 36pf (at 1.25 2.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 61 "Net-(C1-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5E929625)
(at 208.0665 130.583 90)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5BFE9D13)
(fp_text reference C4 (at 1.25 -2.05 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0.1 uF" (at 1.25 2.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:PinHeader_2x20_P2.54mm_Vertical locked (layer F.Cu) (tedit 5DEFFCEB) (tstamp 5D215268)
(at 185.397 175.5918 90)
(descr "Through hole straight pin header, 2x20, 2.54mm pitch, double rows")
(tags "Through hole pin header THT 2x20 2.54mm double row")
(path /5D1EDC84)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference J10 (at -2.8702 24.7015 180) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Keyboard (at -2.8702 29.9085 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at -1.27 24.13) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.7846 -1.9778) (end 4.3654 -1.9778) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7846 49.8722) (end -1.7846 -1.9778) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.3654 49.8722) (end -1.7846 49.8722) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.3654 -1.9778) (end 4.3654 49.8722) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.8954 -1.5078) (end 2.5654 -1.5078) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8954 -0.1778) (end 3.8954 -1.5078) (layer F.SilkS) (width 0.12))
(fp_line (start 1.2954 -1.5078) (end -1.3046 -1.5078) (layer F.SilkS) (width 0.12))
(fp_line (start 1.2954 1.0922) (end 1.2954 -1.5078) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8954 1.0922) (end 1.2954 1.0922) (layer F.SilkS) (width 0.12))
(fp_line (start -1.3046 -1.5078) (end -1.3046 49.4122) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8954 1.0922) (end 3.8954 49.4122) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8954 49.4122) (end -1.3046 49.4122) (layer F.SilkS) (width 0.12))
(fp_line (start 3.8354 -0.1778) (end 2.5654 -1.4478) (layer F.Fab) (width 0.1))
(fp_line (start 3.8354 49.3522) (end 3.8354 -0.1778) (layer F.Fab) (width 0.1))
(fp_line (start -1.2446 49.3522) (end 3.8354 49.3522) (layer F.Fab) (width 0.1))
(fp_line (start -1.2446 -1.4478) (end -1.2446 49.3522) (layer F.Fab) (width 0.1))
(fp_line (start 2.5654 -1.4478) (end -1.2446 -1.4478) (layer F.Fab) (width 0.1))
(pad 40 thru_hole oval (at 0.0254 48.0822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 34 /Row11))
(pad 39 thru_hole oval (at 2.5654 48.0822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 33 /Row12))
(pad 38 thru_hole oval (at 0.0254 45.5422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 27 /Row10))
(pad 37 thru_hole oval (at 2.5654 45.5422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 32 /Row13))
(pad 36 thru_hole oval (at 0.0254 43.0022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 28 /Row9))
(pad 35 thru_hole oval (at 2.5654 43.0022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 /Row14))
(pad 34 thru_hole oval (at 0.0254 40.4622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 33 thru_hole oval (at 2.5654 40.4622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 30 /Row15))
(pad 32 thru_hole oval (at 0.0254 37.9222 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 162 "Net-(J10-Pad32)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 31 thru_hole oval (at 2.5654 37.9222 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 /Row0))
(pad 30 thru_hole oval (at 0.0254 35.3822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 163 "Net-(J10-Pad30)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 29 thru_hole oval (at 2.5654 35.3822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 /Row1))
(pad 28 thru_hole oval (at 0.0254 32.8422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 164 "Net-(J10-Pad28)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 27 thru_hole oval (at 2.5654 32.8422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 24 /Row2))
(pad 26 thru_hole oval (at 0.0254 30.3022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 165 "Net-(J10-Pad26)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 25 thru_hole oval (at 2.5654 30.3022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 2 /Row3))
(pad 24 thru_hole oval (at 0.0254 27.7622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 59 /LED3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 23 thru_hole oval (at 2.5654 27.7622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 /Row4))
(pad 22 thru_hole oval (at 0.0254 25.2222 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 21 thru_hole oval (at 2.5654 25.2222 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 /Row5))
(pad 20 thru_hole oval (at 0.0254 22.6822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 145 "Net-(D19-Pad2)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 19 thru_hole oval (at 2.5654 22.6822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 /Row6))
(pad 18 thru_hole oval (at 0.0254 20.1422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 /Col0))
(pad 17 thru_hole oval (at 2.5654 20.1422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 /Row7))
(pad 16 thru_hole oval (at 0.0254 17.6022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 60 /LED2))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 15 thru_hole oval (at 2.5654 17.6022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 /Col0))
(pad 14 thru_hole oval (at 0.0254 15.0622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 13 thru_hole oval (at 2.5654 15.0622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 16 /Col1))
(pad 12 thru_hole oval (at 0.0254 12.5222 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 144 "Net-(D18-Pad2)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 11 thru_hole oval (at 2.5654 12.5222 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 /Col2))
(pad 10 thru_hole oval (at 0.0254 9.9822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 /Col0))
(pad 9 thru_hole oval (at 2.5654 9.9822 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 18 /Col3))
(pad 8 thru_hole oval (at 0.0254 7.4422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 55 /LED1))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 7 thru_hole oval (at 2.5654 7.4422 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 19 /Col4))
(pad 6 thru_hole oval (at 0.0254 4.9022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 5 thru_hole oval (at 2.5654 4.9022 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 20 /Col5))
(pad 4 thru_hole oval (at 0.0254 2.3622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 143 "Net-(D17-Pad2)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 3 thru_hole oval (at 2.5654 2.3622 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 /Col6))
(pad 2 thru_hole oval (at 0.0254 -0.1778 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 /Col0))
(pad 1 thru_hole rect (at 2.5654 -0.1778 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 22 /Col7))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x20_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module unikbd:SOL20-header-vertical (layer F.Cu) (tedit 5E1E2018) (tstamp 5EB479E3)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at 212.8798 59.8948 90)
(descr "Through hole straight pin header, 2x10, 2.54mm pitch, double rows")
(tags "Through hole pin header THT 2x10 2.54mm double row")
(path /5E5FA80F)
(fp_text reference J5 (at 1.27 -2.33 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SOL-20 (at 5.1308 17.5514 180) (layer F.SilkS)
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
(effects (font (size 1.27 1.27) (thickness 0.1524)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(fp_text user %R (at 1.27 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.35 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.35 24.65) (end 4.35 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 24.65) (end 4.35 24.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.33) (end 3.87 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 1.27) (end 1.27 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 3.87 -1.33) (end 3.87 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 24.19) (end 3.87 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 24.13) (end -1.27 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.81 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 3.81 -1.27) (end 3.81 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0 -1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1))
(pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(pad 19 thru_hole oval (at 2.54 20.32 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 18 thru_hole oval (at 2.54 17.78 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 /D7))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 /D3))
(pad 17 thru_hole oval (at 2.54 15.24 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 14 /D6))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 /D2))
(pad 16 thru_hole oval (at 2.54 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 13 /D5))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 /D1))
(pad 15 thru_hole oval (at 2.54 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 /D4))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 25 /D0))
(pad 14 thru_hole oval (at 2.54 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 56 /OUT1))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 57 /OUT2))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 13 thru_hole oval (at 2.54 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 58 /OUT3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 26 /~STROBE))
(pad 12 thru_hole oval (at 2.54 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 11 thru_hole oval (at 2.54 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x10_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Horizontal (layer F.Cu) (tedit 59FED5CB) (tstamp 5E0F18C9)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(at 166.855 62.765 90)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Through hole angled pin header, 1x05, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x05 2.54mm single row")
(path /5E83DEBE)
(fp_text reference J4 (at 4.385 -2.27 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x05 (at 4.385 12.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.77 5.08) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 10.55 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.55 11.95) (end 10.55 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 11.95) (end 10.55 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.27 -1.27) (end 0 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 10.54) (end 1.44 10.54) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 9.78) (end 1.44 9.78) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 10.54) (end 4.1 10.54) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 9.78) (end 10.1 10.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 9.78) (end 10.1 9.78) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 8.89) (end 4.1 8.89) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 8) (end 1.44 8) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 7.24) (end 1.44 7.24) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 8) (end 4.1 8) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 7.24) (end 10.1 8) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 7.24) (end 10.1 7.24) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 6.35) (end 4.1 6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 5.46) (end 1.44 5.46) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 4.7) (end 1.44 4.7) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 5.46) (end 4.1 5.46) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 4.7) (end 10.1 5.46) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 4.7) (end 10.1 4.7) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 3.81) (end 4.1 3.81) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 2.92) (end 1.44 2.92) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 2.16) (end 1.44 2.16) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 2.92) (end 4.1 2.92) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 2.16) (end 10.1 2.92) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 2.16) (end 10.1 2.16) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 1.27) (end 4.1 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.11 0.38) (end 1.44 0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 1.11 -0.38) (end 1.44 -0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 0.28) (end 10.1 0.28) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 0.16) (end 10.1 0.16) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 0.04) (end 10.1 0.04) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.08) (end 10.1 -0.08) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.2) (end 10.1 -0.2) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.32) (end 10.1 -0.32) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 0.38) (end 4.1 0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 -0.38) (end 10.1 0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.38) (end 10.1 -0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -1.33) (end 1.44 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 11.49) (end 4.1 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 11.49) (end 4.1 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 -1.33) (end 1.44 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start 4.04 10.48) (end 10.04 10.48) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 9.84) (end 10.04 10.48) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 9.84) (end 10.04 9.84) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 10.48) (end 1.5 10.48) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 9.84) (end -0.32 10.48) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 9.84) (end 1.5 9.84) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 7.94) (end 10.04 7.94) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 7.3) (end 10.04 7.94) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 7.3) (end 10.04 7.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 7.94) (end 1.5 7.94) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 7.3) (end -0.32 7.94) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 7.3) (end 1.5 7.3) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 5.4) (end 10.04 5.4) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 4.76) (end 10.04 5.4) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 4.76) (end 10.04 4.76) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 5.4) (end 1.5 5.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 4.76) (end -0.32 5.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 4.76) (end 1.5 4.76) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 2.86) (end 10.04 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 2.22) (end 10.04 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 2.22) (end 10.04 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 2.86) (end 1.5 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 2.22) (end -0.32 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 2.22) (end 1.5 2.22) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 0.32) (end 10.04 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 -0.32) (end 10.04 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end 1.5 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end -0.32 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end 1.5 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start 1.5 -0.635) (end 2.135 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.5 11.43) (end 1.5 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 11.43) (end 1.5 11.43) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 -1.27) (end 4.04 11.43) (layer F.Fab) (width 0.1))
(fp_line (start 2.135 -1.27) (end 4.04 -1.27) (layer F.Fab) (width 0.1))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 56 /OUT1))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 57 /OUT2))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 58 /OUT3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x05_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5EB361B7)
(at 167.744 81.307)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5E4F4413)
(fp_text reference C7 (at 4.572 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0.1 uF" (at 3.556 2.05) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 0.6 0.6) (thickness 0.09)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1E67C)
(at 212.4988 144.807 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E32CB02)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D12 (at 3.9878 -4.4958 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 38 "Net-(D12-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /Row6))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1DB9C)
(at 209.55 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E37FC86)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D11 (at 3.81 -2.12 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 37 "Net-(D11-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 /Row4))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1DBF6)
(at 214.63 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E3942E4)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D10 (at 3.81 -2.12 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 53 "Net-(D10-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 /Row2))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1DC50)
(at 219.71 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E301C34)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D9 (at 3.81 -2.12 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 52 "Net-(D9-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 /Row0))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1E6D6)
(at 215.0642 144.7816 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E34160D)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D3 (at 4.0132 -3.3528 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 142 "Net-(D3-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 /Row5))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1DD04)
(at 212.09 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E357678)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D2 (at 3.81 -2.12 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 1.828561 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 141 "Net-(D2-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 /Row3))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module unikbd:D_DO-35_SOD27_P7.62mm_Horizontal_bypassed (layer F.Cu) (tedit 5DF278C4) (tstamp 5DF1DD5E)
(at 217.17 160.0724 270)
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5E36B862)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D1 (at 3.81 -2.12 90) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_poly (pts (xy 7.239 0.127) (xy 0.381 0.127) (xy 0.381 0) (xy 7.239 0)) (layer F.Cu) (width 0.0508))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 140 "Net-(D1-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 /Row1))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5DF1DF89) (tstamp 5E0532C3)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(at 194.414 158.015 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5EB56F93)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D19 (at -2.7305 0.0762 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 145 "Net-(D19-Pad2)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 /Row1))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Horizontal (layer F.Cu) (tedit 59FED5CB) (tstamp 5E93C54E)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(at 242.62828 62.765 90)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Through hole angled pin header, 1x04, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x04 2.54mm single row")
(path /5E4CDDD4)
(fp_text reference J3 (at 1.76276 -2.74828 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value UART (at 6.96976 -2.62128 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.77 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 10.55 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.55 9.4) (end 10.55 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end 10.55 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.27 -1.27) (end 0 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 8) (end 1.44 8) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 7.24) (end 1.44 7.24) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 8) (end 4.1 8) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 7.24) (end 10.1 8) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 7.24) (end 10.1 7.24) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 6.35) (end 4.1 6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 5.46) (end 1.44 5.46) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 4.7) (end 1.44 4.7) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 5.46) (end 4.1 5.46) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 4.7) (end 10.1 5.46) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 4.7) (end 10.1 4.7) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 3.81) (end 4.1 3.81) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 2.92) (end 1.44 2.92) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 2.16) (end 1.44 2.16) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 2.92) (end 4.1 2.92) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 2.16) (end 10.1 2.92) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 2.16) (end 10.1 2.16) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 1.27) (end 4.1 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.11 0.38) (end 1.44 0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 1.11 -0.38) (end 1.44 -0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 0.28) (end 10.1 0.28) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 0.16) (end 10.1 0.16) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 0.04) (end 10.1 0.04) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.08) (end 10.1 -0.08) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.2) (end 10.1 -0.2) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.32) (end 10.1 -0.32) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 0.38) (end 4.1 0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 -0.38) (end 10.1 0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -0.38) (end 10.1 -0.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 -1.33) (end 1.44 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 8.95) (end 4.1 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 8.95) (end 4.1 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 -1.33) (end 1.44 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 4.04 7.94) (end 10.04 7.94) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 7.3) (end 10.04 7.94) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 7.3) (end 10.04 7.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 7.94) (end 1.5 7.94) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 7.3) (end -0.32 7.94) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 7.3) (end 1.5 7.3) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 5.4) (end 10.04 5.4) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 4.76) (end 10.04 5.4) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 4.76) (end 10.04 4.76) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 5.4) (end 1.5 5.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 4.76) (end -0.32 5.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 4.76) (end 1.5 4.76) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 2.86) (end 10.04 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 2.22) (end 10.04 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 2.22) (end 10.04 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 2.86) (end 1.5 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 2.22) (end -0.32 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 2.22) (end 1.5 2.22) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 0.32) (end 10.04 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 10.04 -0.32) (end 10.04 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end 1.5 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end -0.32 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end 1.5 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start 1.5 -0.635) (end 2.135 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.5 8.89) (end 1.5 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 8.89) (end 1.5 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 -1.27) (end 4.04 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 2.135 -1.27) (end 4.04 -1.27) (layer F.Fab) (width 0.1))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 GND))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 36 /Rx))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 35 /Tx))
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Button_Switch_THT:SW_DIP_SPSTx08_Piano_CTS_Series194-8MSTN_W7.62mm_P2.54mm (layer F.Cu) (tedit 5A4E1407) (tstamp 5DF03359)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 248.262 132.361 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "8x-dip-switch SPST CTS_Series194-8MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)")
(tags "DIP Switch SPST Piano 7.62mm 300mil")
(path /5DF0476A)
(fp_text reference SW1 (at 8.7122 -3.6068) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Options (at -3.3782 -5.4864 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.08 -2.36) (end 8.7 -2.36) (layer F.Fab) (width 0.1))
(fp_line (start 8.7 -2.36) (end 8.7 20.14) (layer F.Fab) (width 0.1))
(fp_line (start 8.7 20.14) (end -1.08 20.14) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 20.14) (end -1.08 -1.36) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 -1.36) (end -0.08 -2.36) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 -0.76) (end -1.08 0.76) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 0.76) (end -2.22 0.76) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 0.76) (end -2.22 -0.76) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 -0.76) (end -1.08 -0.76) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 1.78) (end -1.08 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 3.3) (end -2.22 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 3.3) (end -2.22 1.78) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 1.78) (end -1.08 1.78) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 4.32) (end -1.08 5.84) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 5.84) (end -2.22 5.84) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 5.84) (end -2.22 4.32) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 4.32) (end -1.08 4.32) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 6.86) (end -1.08 8.38) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 8.38) (end -2.22 8.38) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 8.38) (end -2.22 6.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 6.86) (end -1.08 6.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 9.4) (end -1.08 10.92) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 10.92) (end -2.22 10.92) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 10.92) (end -2.22 9.4) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 9.4) (end -1.08 9.4) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 11.94) (end -1.08 13.46) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 13.46) (end -2.22 13.46) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 13.46) (end -2.22 11.94) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 11.94) (end -1.08 11.94) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 14.48) (end -1.08 16) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 16) (end -2.22 16) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 16) (end -2.22 14.48) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 14.48) (end -1.08 14.48) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 17.02) (end -1.08 18.54) (layer F.Fab) (width 0.1))
(fp_line (start -1.08 18.54) (end -2.22 18.54) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 18.54) (end -2.22 17.02) (layer F.Fab) (width 0.1))
(fp_line (start -2.22 17.02) (end -1.08 17.02) (layer F.Fab) (width 0.1))
(fp_line (start -1.14 -2.42) (end 8.76 -2.42) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 20.201) (end 8.76 20.201) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 -2.42) (end -1.14 20.201) (layer F.SilkS) (width 0.12))
(fp_line (start 8.76 -2.42) (end 8.76 20.201) (layer F.SilkS) (width 0.12))
(fp_line (start -1.38 -2.66) (end 0.004 -2.66) (layer F.SilkS) (width 0.12))
(fp_line (start -1.38 -2.66) (end -1.38 -1.277) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 -0.82) (end -1.14 -0.82) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 0.82) (end -1.14 0.82) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 -0.82) (end -2.34 0.82) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 -0.82) (end -1.14 0.82) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 1.72) (end -1.14 1.72) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 3.361) (end -1.14 3.361) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 1.72) (end -2.34 3.361) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 1.72) (end -1.14 3.361) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 4.261) (end -1.14 4.261) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 5.9) (end -1.14 5.9) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 4.261) (end -2.34 5.9) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 4.261) (end -1.14 5.9) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 6.801) (end -1.14 6.801) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 8.441) (end -1.14 8.441) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 6.801) (end -2.34 8.441) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 6.801) (end -1.14 8.441) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 9.34) (end -1.14 9.34) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 10.98) (end -1.14 10.98) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 9.34) (end -2.34 10.98) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 9.34) (end -1.14 10.98) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 11.88) (end -1.14 11.88) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 13.52) (end -1.14 13.52) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 11.88) (end -2.34 13.52) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 11.88) (end -1.14 13.52) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 14.42) (end -1.14 14.42) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 16.06) (end -1.14 16.06) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 14.42) (end -2.34 16.06) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 14.42) (end -1.14 16.06) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 16.96) (end -1.14 16.96) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 18.6) (end -1.14 18.6) (layer F.SilkS) (width 0.12))
(fp_line (start -2.34 16.96) (end -2.34 18.6) (layer F.SilkS) (width 0.12))
(fp_line (start -1.14 16.96) (end -1.14 18.6) (layer F.SilkS) (width 0.12))
(fp_line (start -2.5 -2.7) (end -2.5 20.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.5 20.5) (end 8.95 20.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.95 20.5) (end 8.95 -2.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.95 -2.7) (end -2.5 -2.7) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 54 "Net-(D27-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 65 "Net-(D23-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 46 "Net-(D26-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 64 "Net-(D22-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 45 "Net-(D25-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 63 "Net-(D21-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 44 "Net-(D24-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /Row8))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 43 "Net-(D20-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Button_Switch_THT.3dshapes/SW_DIP_SPSTx08_Piano_CTS_Series194-8MSTN_W7.62mm_P2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5DEFD6A3)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 114.5556 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DFACD33)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D27 (at 3.556 2.3368) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 /Col7))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 54 "Net-(D27-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5E052A72)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 119.6356 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF9A8E3)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D26 (at 3.81 -2.12) (layer F.Fab)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab) hide
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 /Col5))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 46 "Net-(D26-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5DEFC8EA)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 124.7156 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF87A8E)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D25 (at -2.09296 0.46736) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 /Col3))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 45 "Net-(D25-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5DEFCB9D)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 129.7956 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF29274)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D24 (at -2.19456 0.34036) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 /Col1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 44 "Net-(D24-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5DEFC99E)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 117.0956 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF6B891)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D23 (at 3.81 -2.12) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 /Col6))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 65 "Net-(D23-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5E0517BC)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 122.1756 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF5903F)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D22 (at 3.81 -2.12) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 /Col4))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 64 "Net-(D22-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5DEFC890)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 127.2556 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF31D18)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D21 (at -2.19456 0.18796) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 /Col2))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 63 "Net-(D21-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5E05204E)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(at 236.0446 132.3356 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5DF45137)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D20 (at 7.9756 20.1676) (layer F.SilkS) hide
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Silk screen cleanups
2020-04-14 05:29:19 +00:00
(fp_text value 1N4148 (at 6.0706 19.9136) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 /Col0))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 43 "Net-(D20-Pad1)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5E0F80EB)
(at 196.7 111.66 270)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5BFE9C80)
(fp_text reference C3 (at 4.699 0 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0.1 uF" (at 2.921 1.905 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at -1.75006 2.11836 180) (layer F.SilkS) hide
(effects (font (size 0.9 0.9) (thickness 0.135)))
)
(fp_line (start 3.55 -1.05) (end -1.05 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.05) (end -1.05 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.621 0.92) (end 1.879 0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 0.621 -0.92) (end 1.879 -0.92) (layer F.SilkS) (width 0.12))
(fp_line (start 2.75 -0.8) (end -0.25 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 2.75 0.8) (end 2.75 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 0.8) (end 2.75 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -0.25 -0.8) (end -0.25 0.8) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
(module Package_DIP:DIP-16_W7.62mm_Socket (layer F.Cu) (tedit 5A02E8C5) (tstamp 5E98D813)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(at 216.561832 77.37 90)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket")
(path /5D9AB54A)
(fp_text reference J1 (at 8.509 -2.335832 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
(fp_text value "Apple 2" (at 10.16 18.238168) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 19.4) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 19.4) (end 9.15 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.95 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 8.95 19.17) (end 8.95 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 19.17) (end 8.95 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 19.11) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 19.11) (end 8.89 19.11) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 19.11) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 9 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 66 "Net-(J1-Pad9)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 /~STROBE))
(pad 10 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 /D2))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 58 /OUT3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 11 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 /D3))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 67 "Net-(J1-Pad4)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 12 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 /D0))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 /D5))
(pad 13 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 /D1))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 /D4))
(pad 14 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 68 "Net-(J1-Pad14)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 /D6))
(pad 15 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 69 "Net-(J1-Pad15)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 16 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 70 "Net-(J1-Pad16)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5D9C8C4F)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(at 191.62 158.015 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5D9C0280)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D18 (at -2.7305 0.127 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.81 2.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 144 "Net-(D18-Pad2)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 /Row7))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE50CD5) (tstamp 5EB4FFD3)
(at 197.335 158.015 270)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /5D9CCE74)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(fp_text reference D17 (at -2.7305 0 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1N4148 (at 3.683 7.7724 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.25) (end -1.05 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.25) (end 8.67 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.25) (end 8.67 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.25) (end -1.05 -1.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.11 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_text user K (at 0 -1.8 90) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 143 "Net-(D17-Pad2)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 /Row0))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(module Resistor_THT:R_Array_SIP9 (layer F.Cu) (tedit 5A14249F) (tstamp 5EB4BEEB)
(at 204.32 144.68 180)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(descr "9-pin Resistor SIP pack")
(tags R)
(path /5C0319BC)
(fp_text reference RN1 (at 18.3388 -2.667) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(fp_text value 4.7k (at 13.7668 -2.667) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 22.05 -1.65) (end -1.7 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 22.05 1.65) (end 22.05 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 1.65) (end 22.05 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1.65) (end -1.7 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.4) (end 1.27 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 21.76 -1.4) (end -1.44 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 21.76 1.4) (end 21.76 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 1.4) (end 21.76 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.4) (end -1.44 1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.25) (end 1.27 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.61 -1.25) (end -1.29 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.61 1.25) (end 21.61 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 1.25) (end 21.61 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.29 -1.25) (end -1.29 1.25) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 2 thru_hole oval (at 2.54 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 /Col0))
(pad 3 thru_hole oval (at 5.08 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 /Col1))
(pad 4 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 /Col2))
(pad 5 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 /Col3))
(pad 6 thru_hole oval (at 12.7 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 /Col4))
(pad 7 thru_hole oval (at 15.24 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 /Col5))
(pad 8 thru_hole oval (at 17.78 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 /Col6))
(pad 9 thru_hole oval (at 20.32 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 /Col7))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Array_SIP9.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-16_W7.62mm_Socket (layer F.Cu) (tedit 5A02E8C5) (tstamp 5D0D78AD)
(at 184.390166 77.37 90)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket")
(path /5BCB9E1D)
(fp_text reference J2 (at 8.255 -2.549166 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "Apple 1" (at 10.795 8.372834 180) (layer F.SilkS)
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
(effects (font (size 1.27 1.27) (thickness 0.1524)))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
(fp_text user %R (at 9.50214 -0.78486 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 19.4) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 19.4) (end 9.15 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.95 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 8.95 19.17) (end 8.95 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 19.17) (end 8.95 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 19.11) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 19.11) (end 8.89 19.11) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 19.11) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 58 /OUT3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 9 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 GND))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 /D3))
(pad 10 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 71 "Net-(J2-Pad10)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 /D2))
(pad 11 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 72 "Net-(J2-Pad11)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 /D1))
(pad 12 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 56 /OUT1))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 /D0))
(pad 13 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 73 "Net-(J2-Pad13)"))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 /D4))
(pad 14 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 /~STROBE))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 /D5))
(pad 15 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 /D6))
(pad 16 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(net 113 VCC))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text "Unified Kbd ASCII Interface (2560) Rev 3.2\n" (at 165.3564 144.4006 270) (layer B.SilkS) (tstamp 5EBB3E80)
(effects (font (size 1.524 1.524) (thickness 0.254)) (justify mirror))
)
Clean up connector labels on ATmel-2560 ASCII interface PCB
2020-04-16 22:02:28 +00:00
(gr_text "Custom Connector" (at 234.165 90.07) (layer F.SilkS) (tstamp 5E98D8C1)
(effects (font (size 1.27 1.27) (thickness 0.1524)))
)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(gr_circle (center 216.131 108.2945) (end 216.385 108.2945) (layer F.SilkS) (width 0.508))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text O2 (at 171.935 66.194 90) (layer F.SilkS) (tstamp 5E0FBE25)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
(gr_text 1N4148 (at 244.706 171.0452) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
(gr_text "D14-D27\n" (at 245.2902 169.6736) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 7 (at 251.9704 114.581 90) (layer F.SilkS) (tstamp 5E9A8BF1)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 6 (at 251.9704 117.121 90) (layer F.SilkS) (tstamp 5E9A8BEE)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 5 (at 251.9704 119.661 90) (layer F.SilkS) (tstamp 5E9A8BEB)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 4 (at 251.9704 122.201 90) (layer F.SilkS) (tstamp 5E9A8BE8)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 3 (at 251.9704 124.741 90) (layer F.SilkS) (tstamp 5E9A8BE5)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 2 (at 251.9704 127.281 90) (layer F.SilkS) (tstamp 5E9A8BE2)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 1 (at 251.9704 129.821 90) (layer F.SilkS) (tstamp 5E9A8BDF)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_text 0 (at 251.9704 132.361 90) (layer F.SilkS) (tstamp 5E9A8BDC)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
(gr_text +5V (at 242.674 78.87368 90) (layer F.SilkS) (tstamp 5DEB324E)
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
(gr_text GND (at 250.294 78.87368 90) (layer F.SilkS) (tstamp 5E0F7D5F)
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
(gr_text RX (at 247.6778 78.317299 90) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text "OSIWeb.org 2019" (at 195.8618 53.9004) (layer B.SilkS) (tstamp 5EB92390)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.524 1.524) (thickness 0.254)) (justify mirror))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text "OSIWeb.org 2019" (at 195.9888 53.7734) (layer F.SilkS) (tstamp 5EB92393)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.524 1.524) (thickness 0.254)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text "Unified Kbd ASCII Interface (2560) Rev 3.2\n" (at 165.204 130.964 270) (layer F.SilkS) (tstamp 5DEFAA7D)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.524 1.524) (thickness 0.254)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text +5V (at 177.142 66.575 90) (layer F.SilkS) (tstamp 5DA61091)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text O1/CLR (at 174.602 67.972 90) (layer F.SilkS) (tstamp 5DA61091)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text O3/~RESET (at 169.522 69.115 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(gr_text GND (at 166.728 66.575 90) (layer F.SilkS)
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(effects (font (size 1.016 1.016) (thickness 0.127)))
)
(gr_circle (center 233.506 84.1248) (end 235.0935 84.1248) (layer Edge.Cuts) (width 0.1) (tstamp 5D21542F))
(gr_circle (center 185.246 84.1248) (end 186.8335 84.1248) (layer Edge.Cuts) (width 0.1) (tstamp 5DF18072))
(gr_circle (center 174.2224 178.1048) (end 175.8099 178.1048) (layer Edge.Cuts) (width 0.1) (tstamp 5D2152E9))
(gr_circle (center 242.6754 178.1048) (end 244.2629 178.1048) (layer Edge.Cuts) (width 0.1) (tstamp 5D2152E6))
(gr_line (start 163.83 50.8) (end 252.73 50.8) (layer Edge.Cuts) (width 0.1) (tstamp 5E1EE823))
Move DIP switch number label
2020-04-18 05:20:23 +00:00
(gr_line (start 252.73 50.8) (end 252.73 182.88) (layer Edge.Cuts) (width 0.1) (tstamp 5E9A8BD9))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(gr_line (start 252.73 182.88) (end 163.83 182.88) (layer Edge.Cuts) (width 0.1))
(gr_line (start 163.83 182.88) (end 163.83 50.8) (layer Edge.Cuts) (width 0.1) (tstamp 5D2152EC))
(gr_text "Pin 1 of keyboard connector must be at least 3.5\" from\npin 1 of interface connector in order for interface connector\nto be accessible with keyboard assembled." (at 170.4213 202.3745) (layer Cmts.User)
(effects (font (size 1.524 1.524) (thickness 0.15)) (justify left))
)
(gr_text "Mounting holes:\n0.125\" Non-plated\n2.5\" square spacing\nPin 1 of connector 0.31\", 0\" (x,y) relative to center of left lower hole." (at 170.4213 188.6458) (layer Cmts.User)
(effects (font (size 1.524 1.524) (thickness 0.2032)) (justify left))
)
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 231.371 111.66) (end 231.371 111.914) (width 0.254) (layer B.Cu) (net 0))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 207.376 127.3925) (end 208.0665 128.083) (width 0.254) (layer F.Cu) (net 1))
(segment (start 207.376 124.4025) (end 207.376 127.3925) (width 0.254) (layer F.Cu) (net 1))
(segment (start 197.12 113.74) (end 196.7 114.16) (width 0.254) (layer F.Cu) (net 1))
(segment (start 200.2135 113.74) (end 197.12 113.74) (width 0.254) (layer F.Cu) (net 1))
(segment (start 212.8798 59.8948) (end 212.8798 57.3548) (width 1.27) (layer F.Cu) (net 1))
(segment (start 217.9415 120.24) (end 219.433 118.7485) (width 0.254) (layer F.Cu) (net 1))
(segment (start 215.5385 120.24) (end 217.9415 120.24) (width 0.254) (layer F.Cu) (net 1))
(segment (start 208.876 104.492) (end 208.805 104.421) (width 0.254) (layer F.Cu) (net 1))
(segment (start 208.876 109.0775) (end 208.876 104.492) (width 0.254) (layer F.Cu) (net 1))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(via (at 218.29 111.787) (size 1.27) (drill 0.7112) (layers F.Cu B.Cu) (net 1))
(segment (start 215.5385 111.24) (end 217.743 111.24) (width 0.254) (layer F.Cu) (net 1))
(segment (start 217.743 111.24) (end 218.29 111.787) (width 0.254) (layer F.Cu) (net 1))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 215.6992 171.3246) (end 212.1432 167.7686) (width 0.254) (layer B.Cu) (net 2))
(segment (start 215.6992 173.0264) (end 215.6992 171.3246) (width 0.254) (layer B.Cu) (net 2))
(segment (start 223.346 173.6092) (end 223.346 173.0756) (width 0.254) (layer B.Cu) (net 3))
(segment (start 223.3192 171.4008) (end 219.687 167.7686) (width 0.254) (layer B.Cu) (net 3))
(segment (start 223.3192 173.0264) (end 223.3192 171.4008) (width 0.254) (layer B.Cu) (net 3))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 193.144 156.491) (end 193.652 155.983) (width 0.254) (layer F.Cu) (net 3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 219.71 167.6924) (end 217.4494 169.953) (width 0.254) (layer F.Cu) (net 3))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 193.144 158.777) (end 193.144 156.491) (width 0.254) (layer F.Cu) (net 3))
(segment (start 204.32 169.953) (end 193.144 158.777) (width 0.254) (layer F.Cu) (net 3))
(segment (start 196.357 155.983) (end 197.335 156.961) (width 0.254) (layer F.Cu) (net 3))
(segment (start 193.652 155.983) (end 196.357 155.983) (width 0.254) (layer F.Cu) (net 3))
(segment (start 217.4494 169.953) (end 204.32 169.953) (width 0.254) (layer F.Cu) (net 3))
(segment (start 197.335 156.961) (end 197.335 158.015) (width 0.254) (layer F.Cu) (net 3))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 220.7792 171.35) (end 220.7792 173.0264) (width 0.254) (layer B.Cu) (net 4))
(segment (start 217.1978 167.7686) (end 220.7792 171.35) (width 0.254) (layer B.Cu) (net 4))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 205.89799 169.49899) (end 194.414 158.015) (width 0.254) (layer F.Cu) (net 4))
(segment (start 215.36341 169.49899) (end 205.89799 169.49899) (width 0.254) (layer F.Cu) (net 4))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 217.17 167.6924) (end 215.36341 169.49899) (width 0.254) (layer F.Cu) (net 4))
(segment (start 210.428599 168.568599) (end 210.428599 168.593999) (width 0.254) (layer B.Cu) (net 5))
(segment (start 209.6286 167.7686) (end 210.428599 168.568599) (width 0.254) (layer B.Cu) (net 5))
(segment (start 213.1592 171.3246) (end 213.1592 173.0264) (width 0.254) (layer B.Cu) (net 5))
(segment (start 210.428599 168.593999) (end 213.1592 171.3246) (width 0.254) (layer B.Cu) (net 5))
(segment (start 209.769201 172.176401) (end 210.6192 173.0264) (width 0.254) (layer B.Cu) (net 6))
(segment (start 207.622 155.094) (end 207.622 170.0292) (width 0.254) (layer B.Cu) (net 6))
(segment (start 213.6418 153.824) (end 208.892 153.824) (width 0.254) (layer B.Cu) (net 6))
(segment (start 207.622 170.0292) (end 209.769201 172.176401) (width 0.254) (layer B.Cu) (net 6))
(segment (start 208.892 153.824) (end 207.622 155.094) (width 0.254) (layer B.Cu) (net 6))
(segment (start 215.0642 152.4016) (end 213.6418 153.824) (width 0.254) (layer B.Cu) (net 6))
(segment (start 239.230001 168.492399) (end 240.03 167.6924) (width 0.254) (layer F.Cu) (net 7))
(segment (start 237.315389 170.407011) (end 239.230001 168.492399) (width 0.254) (layer F.Cu) (net 7))
(segment (start 217.637459 170.407011) (end 237.315389 170.407011) (width 0.254) (layer F.Cu) (net 7))
(segment (start 208.158589 170.407011) (end 217.637459 170.407011) (width 0.254) (layer F.Cu) (net 7))
(segment (start 205.5392 173.0264) (end 208.158589 170.407011) (width 0.254) (layer F.Cu) (net 7))
(segment (start 204.689201 172.176401) (end 205.5392 173.0264) (width 0.254) (layer F.Cu) (net 7))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 204.689201 170.957201) (end 204.689201 172.176401) (width 0.254) (layer F.Cu) (net 7))
(segment (start 191.747 158.015) (end 204.689201 170.957201) (width 0.254) (layer F.Cu) (net 7))
(segment (start 191.62 158.015) (end 191.747 158.015) (width 0.254) (layer F.Cu) (net 7))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(via (at 209.753328 70.693375) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 8))
(segment (start 200.2135 111.24) (end 198.947 111.24) (width 0.254) (layer F.Cu) (net 8))
(segment (start 198.947 111.24) (end 198.986 111.201) (width 0.254) (layer F.Cu) (net 8))
(via (at 198.986 104.802) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 8))
(segment (start 198.986 111.201) (end 198.986 104.802) (width 0.254) (layer F.Cu) (net 8))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 210.328064 70.693375) (end 209.753328 70.693375) (width 0.254) (layer F.Cu) (net 8))
(segment (start 213.303439 67.718) (end 210.328064 70.693375) (width 0.254) (layer F.Cu) (net 8))
(segment (start 230.6598 57.3548) (end 231.836801 58.531801) (width 0.254) (layer F.Cu) (net 8))
(segment (start 229.9105 67.718) (end 213.303439 67.718) (width 0.254) (layer F.Cu) (net 8))
(segment (start 231.836801 65.791699) (end 229.9105 67.718) (width 0.254) (layer F.Cu) (net 8))
(segment (start 231.836801 58.531801) (end 231.836801 65.791699) (width 0.254) (layer F.Cu) (net 8))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 198.986 104.802) (end 198.986 102.135) (width 0.254) (layer B.Cu) (net 8))
(segment (start 201.500601 99.620399) (end 209.755601 99.620399) (width 0.254) (layer B.Cu) (net 8))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(via (at 211.432 97.944) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 8))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 198.986 102.135) (end 201.500601 99.620399) (width 0.254) (layer B.Cu) (net 8))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 211.025601 98.350399) (end 211.432 97.944) (width 0.254) (layer B.Cu) (net 8))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 209.755601 99.620399) (end 211.025601 98.350399) (width 0.254) (layer B.Cu) (net 8))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 209.958603 81.586401) (end 209.753328 81.381126) (width 0.254) (layer B.Cu) (net 8))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 220.3474 89.281586) (end 212.091385 97.537601) (width 0.254) (layer F.Cu) (net 8))
(segment (start 212.091385 97.537601) (end 211.838399 97.537601) (width 0.254) (layer F.Cu) (net 8))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 220.3474 81.9928) (end 219.941001 81.586401) (width 0.254) (layer B.Cu) (net 8))
(segment (start 219.941001 81.586401) (end 209.958603 81.586401) (width 0.254) (layer B.Cu) (net 8))
(segment (start 209.753328 81.381126) (end 209.753328 71.268111) (width 0.254) (layer B.Cu) (net 8))
(segment (start 209.753328 71.268111) (end 209.753328 70.693375) (width 0.254) (layer B.Cu) (net 8))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 211.838399 97.537601) (end 211.432 97.944) (width 0.254) (layer F.Cu) (net 8))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 220.3728 81.9674) (end 220.3474 81.9928) (width 0.254) (layer F.Cu) (net 8))
(segment (start 220.3474 81.9928) (end 220.3474 89.281586) (width 0.254) (layer F.Cu) (net 8))
(via (at 220.3474 81.9928) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 8))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(via (at 206.4028 66.3718) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 9))
(segment (start 192.010166 77.37) (end 196.048766 73.3314) (width 0.254) (layer B.Cu) (net 9))
(segment (start 196.048766 73.3314) (end 205.8694 73.3314) (width 0.254) (layer B.Cu) (net 9))
(segment (start 205.593199 67.181401) (end 206.4028 66.3718) (width 0.254) (layer B.Cu) (net 9))
(segment (start 205.593199 67.892233) (end 205.593199 67.181401) (width 0.254) (layer B.Cu) (net 9))
(segment (start 205.8694 73.3314) (end 205.8694 68.168434) (width 0.254) (layer B.Cu) (net 9))
(segment (start 205.8694 68.168434) (end 205.593199 67.892233) (width 0.254) (layer B.Cu) (net 9))
(segment (start 206.809199 65.965401) (end 206.4028 66.3718) (width 0.254) (layer F.Cu) (net 9))
(segment (start 207.088655 65.685945) (end 206.809199 65.965401) (width 0.254) (layer F.Cu) (net 9))
(segment (start 224.259055 65.685945) (end 207.088655 65.685945) (width 0.254) (layer F.Cu) (net 9))
(segment (start 225.5798 64.3652) (end 224.259055 65.685945) (width 0.254) (layer F.Cu) (net 9))
(segment (start 225.5798 59.8948) (end 225.5798 64.3652) (width 0.254) (layer F.Cu) (net 9))
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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(segment (start 211.076399 66.930644) (end 210.67 67.337043) (width 0.254) (layer F.Cu) (net 14))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 205.376 109.0775) (end 205.376 107.334754) (width 0.254) (layer F.Cu) (net 14))
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(segment (start 205.056601 97.588399) (end 205.463 97.182) (width 0.254) (layer F.Cu) (net 14))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 205.463 97.182) (end 205.404093 97.123093) (width 0.254) (layer B.Cu) (net 14))
(segment (start 204.065947 98.579053) (end 205.056601 97.588399) (width 0.254) (layer F.Cu) (net 14))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(via (at 205.463 97.182) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 14))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(via (at 203.939 93.118) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 14))
(segment (start 205.463 97.182) (end 203.939 95.658) (width 0.254) (layer B.Cu) (net 14))
(segment (start 203.939 95.658) (end 203.939 93.118) (width 0.254) (layer B.Cu) (net 14))
(segment (start 185.2192 175.5664) (end 186.9718 177.319) (width 0.254) (layer B.Cu) (net 15))
(segment (start 203.7866 177.319) (end 205.5392 175.5664) (width 0.254) (layer B.Cu) (net 15))
(segment (start 195.3792 177.2682) (end 195.3792 175.5664) (width 0.254) (layer B.Cu) (net 15))
(segment (start 186.9718 177.319) (end 195.43 177.319) (width 0.254) (layer B.Cu) (net 15))
(segment (start 195.43 177.319) (end 195.3792 177.2682) (width 0.254) (layer B.Cu) (net 15))
(segment (start 195.43 177.319) (end 203.7866 177.319) (width 0.254) (layer B.Cu) (net 15))
(segment (start 202.9992 173.0264) (end 205.5392 175.5664) (width 0.254) (layer B.Cu) (net 15))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 201.78 171.8072) (end 202.9992 173.0264) (width 0.254) (layer B.Cu) (net 15))
(segment (start 201.78 144.68) (end 201.78 171.8072) (width 0.254) (layer B.Cu) (net 15))
(via (at 202.160992 133.377) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 15))
(segment (start 227.3832 133.377) (end 202.160992 133.377) (width 0.254) (layer B.Cu) (net 15))
(segment (start 201.78 133.757992) (end 202.160992 133.377) (width 0.254) (layer F.Cu) (net 15))
(segment (start 201.78 144.68) (end 201.78 133.757992) (width 0.254) (layer F.Cu) (net 15))
(segment (start 228.4246 132.3356) (end 227.3832 133.377) (width 0.254) (layer B.Cu) (net 15))
(segment (start 202.288 133.249992) (end 202.160992 133.377) (width 0.254) (layer F.Cu) (net 15))
(segment (start 202.288 126.519) (end 202.288 133.249992) (width 0.254) (layer F.Cu) (net 15))
(segment (start 202.876 125.931) (end 202.288 126.519) (width 0.254) (layer F.Cu) (net 15))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 202.876 124.4025) (end 202.876 125.931) (width 0.254) (layer F.Cu) (net 15))
(via (at 199.112998 128.297) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 16))
(segment (start 199.1638 128.347802) (end 199.112998 128.297) (width 0.254) (layer F.Cu) (net 16))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 199.112998 144.552998) (end 199.24 144.68) (width 0.254) (layer F.Cu) (net 16))
(segment (start 199.112998 128.297) (end 199.112998 144.552998) (width 0.254) (layer F.Cu) (net 16))
(segment (start 199.189198 145.862172) (end 199.24 145.81137) (width 0.254) (layer B.Cu) (net 16))
(segment (start 200.4592 173.0264) (end 199.189198 171.756398) (width 0.254) (layer B.Cu) (net 16))
(segment (start 199.24 145.81137) (end 199.24 144.68) (width 0.254) (layer B.Cu) (net 16))
(segment (start 199.189198 171.756398) (end 199.189198 145.862172) (width 0.254) (layer B.Cu) (net 16))
(segment (start 204.447 126.519) (end 203.456399 127.509601) (width 0.254) (layer B.Cu) (net 16))
(segment (start 225.148 126.519) (end 204.447 126.519) (width 0.254) (layer B.Cu) (net 16))
(segment (start 228.4246 129.7956) (end 225.148 126.519) (width 0.254) (layer B.Cu) (net 16))
(segment (start 203.376 124.4025) (end 203.376 127.59) (width 0.254) (layer F.Cu) (net 16))
(segment (start 203.456399 127.509601) (end 203.05 127.916) (width 0.254) (layer B.Cu) (net 16))
(segment (start 202.669 128.297) (end 203.05 127.916) (width 0.254) (layer B.Cu) (net 16))
(segment (start 203.376 127.59) (end 203.05 127.916) (width 0.254) (layer F.Cu) (net 16))
(segment (start 199.112998 128.297) (end 202.669 128.297) (width 0.254) (layer B.Cu) (net 16))
(via (at 203.05 127.916) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 16))
(segment (start 196.065 145.315) (end 196.7 144.68) (width 0.254) (layer B.Cu) (net 17))
(segment (start 196.065 171.1722) (end 196.065 145.315) (width 0.254) (layer B.Cu) (net 17))
(segment (start 197.9192 173.0264) (end 196.065 171.1722) (width 0.254) (layer B.Cu) (net 17))
(via (at 195.938 135.663) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 17))
(segment (start 196.7 136.425) (end 195.938 135.663) (width 0.254) (layer F.Cu) (net 17))
(segment (start 196.7 144.68) (end 196.7 136.425) (width 0.254) (layer F.Cu) (net 17))
(via (at 202.8595 134.774) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 17))
(segment (start 203.876 133.7575) (end 202.8595 134.774) (width 0.254) (layer F.Cu) (net 17))
(segment (start 195.938 135.663) (end 201.9705 135.663) (width 0.254) (layer B.Cu) (net 17))
(segment (start 203.876 124.4025) (end 203.876 133.7575) (width 0.254) (layer F.Cu) (net 17))
(segment (start 201.9705 135.663) (end 202.8595 134.774) (width 0.254) (layer B.Cu) (net 17))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 230.228 129.059) (end 228.4246 127.2556) (width 0.254) (layer B.Cu) (net 17))
(segment (start 230.228 132.996) (end 230.228 129.059) (width 0.254) (layer B.Cu) (net 17))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 228.856399 134.367601) (end 230.228 132.996) (width 0.254) (layer B.Cu) (net 17))
(segment (start 203.265899 134.367601) (end 228.856399 134.367601) (width 0.254) (layer B.Cu) (net 17))
(segment (start 202.8595 134.774) (end 203.265899 134.367601) (width 0.254) (layer B.Cu) (net 17))
(segment (start 231.498 127.789) (end 231.498 135.028014) (width 0.254) (layer F.Cu) (net 18))
(segment (start 231.853601 135.383615) (end 232.26 135.790014) (width 0.254) (layer F.Cu) (net 18))
(via (at 232.26 135.790014) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 18))
(segment (start 231.498 135.028014) (end 231.853601 135.383615) (width 0.254) (layer F.Cu) (net 18))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 228.4246 124.7156) (end 231.498 127.789) (width 0.254) (layer F.Cu) (net 18))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 194.0838 145.88757) (end 194.16 145.81137) (width 0.254) (layer B.Cu) (net 18))
(segment (start 195.658589 171.54493) (end 195.658589 149.988589) (width 0.254) (layer B.Cu) (net 18))
(segment (start 194.0838 148.4138) (end 194.0838 145.88757) (width 0.254) (layer B.Cu) (net 18))
(segment (start 195.658589 149.988589) (end 194.0838 148.4138) (width 0.254) (layer B.Cu) (net 18))
(segment (start 195.3792 171.824319) (end 195.658589 171.54493) (width 0.254) (layer B.Cu) (net 18))
(segment (start 194.16 145.81137) (end 194.16 144.68) (width 0.254) (layer B.Cu) (net 18))
(segment (start 195.3792 173.0264) (end 195.3792 171.824319) (width 0.254) (layer B.Cu) (net 18))
(via (at 194.16 136.679) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 18))
(segment (start 194.16 144.68) (end 194.16 136.679) (width 0.254) (layer F.Cu) (net 18))
(segment (start 204.376 134.972002) (end 202.669 136.679002) (width 0.254) (layer F.Cu) (net 18))
(segment (start 194.16 136.679) (end 202.668998 136.679) (width 0.254) (layer B.Cu) (net 18))
(via (at 202.669 136.679002) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 18))
(segment (start 204.376 124.4025) (end 204.376 134.972002) (width 0.254) (layer F.Cu) (net 18))
(segment (start 202.668998 136.679) (end 202.669 136.679002) (width 0.254) (layer B.Cu) (net 18))
(segment (start 203.243736 136.679002) (end 202.669 136.679002) (width 0.254) (layer B.Cu) (net 18))
(segment (start 232.26 135.790014) (end 231.320213 136.729801) (width 0.254) (layer B.Cu) (net 18))
(segment (start 203.294535 136.729801) (end 203.243736 136.679002) (width 0.254) (layer B.Cu) (net 18))
(segment (start 231.320213 136.729801) (end 203.294535 136.729801) (width 0.254) (layer B.Cu) (net 18))
(via (at 234.164972 137.695) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 19))
(segment (start 231.95519 125.70619) (end 231.95519 134.275436) (width 0.254) (layer F.Cu) (net 19))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 228.4246 122.1756) (end 231.95519 125.70619) (width 0.254) (layer F.Cu) (net 19))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 231.95519 134.275436) (end 234.164972 136.485218) (width 0.254) (layer F.Cu) (net 19))
(segment (start 234.164972 136.485218) (end 234.164972 137.120264) (width 0.254) (layer F.Cu) (net 19))
(segment (start 234.164972 137.120264) (end 234.164972 137.695) (width 0.254) (layer F.Cu) (net 19))
(via (at 191.62 137.695) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 19))
(segment (start 191.62 144.68) (end 191.62 137.695) (width 0.254) (layer F.Cu) (net 19))
(segment (start 192.419999 145.479999) (end 191.62 144.68) (width 0.254) (layer B.Cu) (net 19))
(segment (start 193.105812 146.165812) (end 192.419999 145.479999) (width 0.254) (layer B.Cu) (net 19))
(segment (start 193.105812 172.759788) (end 193.105812 146.165812) (width 0.254) (layer B.Cu) (net 19))
(segment (start 192.8392 173.0264) (end 193.105812 172.759788) (width 0.254) (layer B.Cu) (net 19))
(via (at 203.558 137.821994) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 19))
(segment (start 204.876 136.503994) (end 203.964399 137.415595) (width 0.254) (layer F.Cu) (net 19))
(segment (start 203.431006 137.695) (end 203.558 137.821994) (width 0.254) (layer B.Cu) (net 19))
(segment (start 191.62 137.695) (end 203.431006 137.695) (width 0.254) (layer B.Cu) (net 19))
(segment (start 203.684994 137.695) (end 203.558 137.821994) (width 0.254) (layer B.Cu) (net 19))
(segment (start 234.164972 137.695) (end 203.684994 137.695) (width 0.254) (layer B.Cu) (net 19))
(segment (start 204.876 124.4025) (end 204.876 136.503994) (width 0.254) (layer F.Cu) (net 19))
(segment (start 203.964399 137.415595) (end 203.558 137.821994) (width 0.254) (layer F.Cu) (net 19))
(segment (start 235.206399 136.891663) (end 235.206399 138.558601) (width 0.254) (layer F.Cu) (net 20))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 228.4246 119.6356) (end 232.387 123.598) (width 0.254) (layer F.Cu) (net 20))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(via (at 234.8 138.965) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 20))
(segment (start 232.387 123.598) (end 232.387 134.072264) (width 0.254) (layer F.Cu) (net 20))
(segment (start 232.387 134.072264) (end 235.206399 136.891663) (width 0.254) (layer F.Cu) (net 20))
(segment (start 235.206399 138.558601) (end 234.8 138.965) (width 0.254) (layer F.Cu) (net 20))
(segment (start 234.225264 138.965) (end 203.05 138.965) (width 0.254) (layer B.Cu) (net 20))
(segment (start 234.8 138.965) (end 234.225264 138.965) (width 0.254) (layer B.Cu) (net 20))
(via (at 203.05 138.965) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 20))
(segment (start 203.05 138.965) (end 202.475264 138.965) (width 0.254) (layer B.Cu) (net 20))
(segment (start 202.475264 138.965) (end 189.08 138.965) (width 0.254) (layer B.Cu) (net 20))
(via (at 189.08 138.965) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 20))
(segment (start 189.08 142.4956) (end 189.08 144.68) (width 0.254) (layer F.Cu) (net 20))
(segment (start 189.08 138.965) (end 189.08 142.4956) (width 0.254) (layer F.Cu) (net 20))
(segment (start 189.449201 172.176401) (end 190.2992 173.0264) (width 0.254) (layer B.Cu) (net 20))
(segment (start 189.0038 152.756188) (end 189.0038 171.731) (width 0.254) (layer B.Cu) (net 20))
(segment (start 189.879999 151.879989) (end 189.0038 152.756188) (width 0.254) (layer B.Cu) (net 20))
(segment (start 189.0038 171.731) (end 189.449201 172.176401) (width 0.254) (layer B.Cu) (net 20))
(segment (start 189.08 144.68) (end 189.879999 145.479999) (width 0.254) (layer B.Cu) (net 20))
(segment (start 189.879999 145.479999) (end 189.879999 151.879989) (width 0.254) (layer B.Cu) (net 20))
(segment (start 203.624736 138.965) (end 203.05 138.965) (width 0.254) (layer F.Cu) (net 20))
(segment (start 205.376 137.213736) (end 203.624736 138.965) (width 0.254) (layer F.Cu) (net 20))
(segment (start 205.376 124.4025) (end 205.376 137.213736) (width 0.254) (layer F.Cu) (net 20))
(via (at 186.539976 140.235) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 21))
(via (at 204.32 140.235) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 21))
(segment (start 186.539976 140.235) (end 204.32 140.235) (width 0.254) (layer B.Cu) (net 21))
(via (at 236.705 139.6) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 21))
(segment (start 204.32 140.235) (end 236.07 140.235) (width 0.254) (layer B.Cu) (net 21))
(segment (start 232.869589 133.600099) (end 236.705 137.43551) (width 0.254) (layer F.Cu) (net 21))
(segment (start 228.4246 117.0956) (end 232.869589 121.540589) (width 0.254) (layer F.Cu) (net 21))
(segment (start 236.705 137.43551) (end 236.705 139.025264) (width 0.254) (layer F.Cu) (net 21))
(segment (start 232.869589 121.540589) (end 232.869589 133.600099) (width 0.254) (layer F.Cu) (net 21))
(segment (start 236.705 139.025264) (end 236.705 139.6) (width 0.254) (layer F.Cu) (net 21))
(segment (start 236.07 140.235) (end 236.705 139.6) (width 0.254) (layer B.Cu) (net 21))
(segment (start 205.876 138.679) (end 204.32 140.235) (width 0.254) (layer F.Cu) (net 21))
(segment (start 205.876 124.4025) (end 205.876 138.679) (width 0.254) (layer F.Cu) (net 21))
(segment (start 186.4765 140.298476) (end 186.539976 140.235) (width 0.254) (layer F.Cu) (net 21))
(segment (start 186.4765 144.6165) (end 186.4765 140.298476) (width 0.254) (layer F.Cu) (net 21))
(segment (start 186.54 144.68) (end 186.4765 144.6165) (width 0.254) (layer F.Cu) (net 21))
(segment (start 186.4638 144.7562) (end 186.54 144.68) (width 0.254) (layer B.Cu) (net 21))
(segment (start 186.4638 171.731) (end 186.4638 144.7562) (width 0.254) (layer B.Cu) (net 21))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 187.7592 173.0264) (end 186.4638 171.731) (width 0.254) (layer B.Cu) (net 21))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 239.245 140.930264) (end 239.245 141.505) (width 0.254) (layer F.Cu) (net 22))
(segment (start 239.245 139.400759) (end 239.245 140.930264) (width 0.254) (layer F.Cu) (net 22))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 228.4246 114.5556) (end 233.276 119.407) (width 0.254) (layer F.Cu) (net 22))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 233.276 119.407) (end 233.276 133.431759) (width 0.254) (layer F.Cu) (net 22))
(segment (start 233.276 133.431759) (end 239.245 139.400759) (width 0.254) (layer F.Cu) (net 22))
(via (at 239.245 141.505) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 22))
(segment (start 238.432202 141.505) (end 238.838601 141.911399) (width 0.254) (layer B.Cu) (net 22))
(segment (start 238.838601 141.911399) (end 239.245 141.505) (width 0.254) (layer B.Cu) (net 22))
(segment (start 206.376 141.354) (end 206.225 141.505) (width 0.254) (layer F.Cu) (net 22))
(via (at 206.225 141.505) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 22))
(segment (start 206.376 124.4025) (end 206.376 141.354) (width 0.254) (layer F.Cu) (net 22))
(segment (start 206.225 141.505) (end 238.432202 141.505) (width 0.254) (layer B.Cu) (net 22))
(segment (start 187.175 141.505) (end 206.225 141.505) (width 0.254) (layer B.Cu) (net 22))
(segment (start 183.9238 144.7562) (end 184 144.68) (width 0.254) (layer B.Cu) (net 22))
(segment (start 183.9238 171.731) (end 183.9238 144.7562) (width 0.254) (layer B.Cu) (net 22))
(segment (start 185.2192 173.0264) (end 183.9238 171.731) (width 0.254) (layer B.Cu) (net 22))
(segment (start 187.175 141.505) (end 184 141.505) (width 0.254) (layer B.Cu) (net 22))
(via (at 184 141.505) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 22))
(segment (start 184 144.68) (end 184 141.505) (width 0.254) (layer F.Cu) (net 22))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 207.215589 154.92566) (end 207.215589 172.162789) (width 0.254) (layer B.Cu) (net 23))
(segment (start 207.215589 172.162789) (end 207.229201 172.176401) (width 0.254) (layer B.Cu) (net 23))
(segment (start 209.714249 152.427) (end 207.215589 154.92566) (width 0.254) (layer B.Cu) (net 23))
(segment (start 212.4988 152.427) (end 209.714249 152.427) (width 0.254) (layer B.Cu) (net 23))
(segment (start 207.229201 172.176401) (end 208.0792 173.0264) (width 0.254) (layer B.Cu) (net 23))
(segment (start 218.2392 171.35) (end 218.2392 173.0264) (width 0.254) (layer B.Cu) (net 24))
(segment (start 214.6578 167.7686) (end 218.2392 171.35) (width 0.254) (layer B.Cu) (net 24))
(segment (start 194.550166 77.37) (end 197.099742 79.919576) (width 0.254) (layer B.Cu) (net 25))
(segment (start 197.099742 79.919576) (end 207.733176 79.919576) (width 0.254) (layer B.Cu) (net 25))
(segment (start 207.733176 79.919576) (end 207.733176 69.638824) (width 0.254) (layer B.Cu) (net 25))
(segment (start 207.733176 69.638824) (end 208.2443 69.1277) (width 0.254) (layer B.Cu) (net 25))
(via (at 208.2443 69.1277) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 25))
(segment (start 207.669564 69.1277) (end 208.2443 69.1277) (width 0.254) (layer F.Cu) (net 25))
(segment (start 204.9804 67.4894) (end 206.6187 69.1277) (width 0.254) (layer F.Cu) (net 25))
(segment (start 204.9804 66.024915) (end 204.9804 67.4894) (width 0.254) (layer F.Cu) (net 25))
(segment (start 206.132192 64.873123) (end 204.9804 66.024915) (width 0.254) (layer F.Cu) (net 25))
(segment (start 221.769877 64.873123) (end 206.132192 64.873123) (width 0.254) (layer F.Cu) (net 25))
(segment (start 223.0398 63.6032) (end 221.769877 64.873123) (width 0.254) (layer F.Cu) (net 25))
(segment (start 206.6187 69.1277) (end 207.669564 69.1277) (width 0.254) (layer F.Cu) (net 25))
(segment (start 223.0398 59.8948) (end 223.0398 63.6032) (width 0.254) (layer F.Cu) (net 25))
(via (at 236.705 71.401) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 25))
(segment (start 226.721832 69.75) (end 228.372832 71.401) (width 0.254) (layer B.Cu) (net 25))
(segment (start 228.372832 71.401) (end 236.705 71.401) (width 0.254) (layer B.Cu) (net 25))
(via (at 236.578004 79.021) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 25))
(segment (start 212.142511 79.935399) (end 235.663605 79.935399) (width 0.254) (layer B.Cu) (net 25))
(segment (start 236.171605 79.427399) (end 236.578004 79.021) (width 0.254) (layer B.Cu) (net 25))
(segment (start 235.663605 79.935399) (end 236.171605 79.427399) (width 0.254) (layer B.Cu) (net 25))
(segment (start 210.6192 68.099) (end 211.9908 69.4706) (width 0.254) (layer B.Cu) (net 25))
(segment (start 236.705 78.894004) (end 236.578004 79.021) (width 0.254) (layer F.Cu) (net 25))
(segment (start 209.273 68.099) (end 210.6192 68.099) (width 0.254) (layer B.Cu) (net 25))
(segment (start 235.765204 79.8338) (end 236.578004 79.021) (width 0.254) (layer F.Cu) (net 25))
(segment (start 236.705 71.401) (end 236.705 78.894004) (width 0.254) (layer F.Cu) (net 25))
(segment (start 211.9908 79.783688) (end 212.142511 79.935399) (width 0.254) (layer B.Cu) (net 25))
(segment (start 211.9908 69.4706) (end 211.9908 79.783688) (width 0.254) (layer B.Cu) (net 25))
(segment (start 208.2443 69.1277) (end 209.273 68.099) (width 0.254) (layer B.Cu) (net 25))
(segment (start 194.550166 77.37) (end 194.550166 82.459166) (width 0.254) (layer F.Cu) (net 25))
(via (at 194.668 82.577) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 25))
(segment (start 194.550166 82.459166) (end 194.668 82.577) (width 0.254) (layer F.Cu) (net 25))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 194.922 82.577) (end 194.668 82.577) (width 0.254) (layer B.Cu) (net 25))
(via (at 213.718 82.577) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 25))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 213.718 82.577) (end 194.922 82.577) (width 0.254) (layer B.Cu) (net 25))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 208.376 109.0775) (end 208.376 106.572) (width 0.254) (layer F.Cu) (net 25))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 206.733 101.5) (end 213.718 94.515) (width 0.254) (layer F.Cu) (net 25))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 213.718 94.515) (end 213.718 82.577) (width 0.254) (layer F.Cu) (net 25))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 206.733 104.929) (end 206.733 101.5) (width 0.254) (layer F.Cu) (net 25))
(segment (start 208.376 106.572) (end 206.733 104.929) (width 0.254) (layer F.Cu) (net 25))
(segment (start 189.461 70.004) (end 189.461 69.877) (width 0.254) (layer B.Cu) (net 26))
(segment (start 215.23785 73.506018) (end 218.301833 76.570001) (width 0.254) (layer F.Cu) (net 26))
(segment (start 218.301833 76.570001) (end 219.101832 77.37) (width 0.254) (layer F.Cu) (net 26))
(segment (start 193.226184 73.506018) (end 215.23785 73.506018) (width 0.254) (layer F.Cu) (net 26))
(segment (start 189.470166 69.75) (end 193.226184 73.506018) (width 0.254) (layer F.Cu) (net 26))
(segment (start 219.179 77.447168) (end 219.101832 77.37) (width 0.254) (layer F.Cu) (net 26))
(segment (start 202.876 109.0775) (end 202.876 107.803) (width 0.254) (layer F.Cu) (net 26))
(via (at 202.415 107.342) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 26))
(segment (start 202.876 107.803) (end 202.415 107.342) (width 0.254) (layer F.Cu) (net 26))
(segment (start 202.415 106.767264) (end 202.542 106.640264) (width 0.254) (layer B.Cu) (net 26))
(segment (start 202.415 107.342) (end 202.415 106.767264) (width 0.254) (layer B.Cu) (net 26))
(segment (start 202.542 106.640264) (end 202.542 101.5) (width 0.254) (layer B.Cu) (net 26))
(segment (start 202.542 101.5) (end 202.542 100.738) (width 0.254) (layer B.Cu) (net 26))
(segment (start 202.542 101.5) (end 202.542 101.373) (width 0.254) (layer B.Cu) (net 26))
(segment (start 202.542 100.738) (end 202.542 100.484) (width 0.254) (layer B.Cu) (net 26))
(via (at 202.542 100.611) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 26))
(segment (start 202.542 100.484) (end 202.542 100.611) (width 0.254) (layer B.Cu) (net 26))
(segment (start 202.542 100.611) (end 202.542 93.245) (width 0.254) (layer F.Cu) (net 26))
(via (at 202.034 92.737) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 26))
(segment (start 202.542 93.245) (end 202.034 92.737) (width 0.254) (layer F.Cu) (net 26))
(segment (start 202.034 92.737) (end 188.572 92.737) (width 0.254) (layer B.Cu) (net 26))
(via (at 188.572 92.737) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 26))
(segment (start 188.572 92.737) (end 188.165601 92.330601) (width 0.254) (layer F.Cu) (net 26))
(segment (start 188.165601 78.538399) (end 188.165601 71.054565) (width 0.254) (layer F.Cu) (net 26))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 188.165601 71.054565) (end 189.470166 69.75) (width 0.254) (layer F.Cu) (net 26))
(segment (start 188.165601 92.330601) (end 188.165601 78.538399) (width 0.254) (layer F.Cu) (net 26))
(segment (start 190.270165 68.950001) (end 189.470166 69.75) (width 0.254) (layer B.Cu) (net 26))
(segment (start 197.090166 62.13) (end 190.270165 68.950001) (width 0.254) (layer B.Cu) (net 26))
(segment (start 216.926681 62.13) (end 197.090166 62.13) (width 0.254) (layer B.Cu) (net 26))
(segment (start 217.9598 61.096881) (end 216.926681 62.13) (width 0.254) (layer B.Cu) (net 26))
(segment (start 217.9598 59.8948) (end 217.9598 61.096881) (width 0.254) (layer B.Cu) (net 26))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 233.022 177.6492) (end 230.9392 175.5664) (width 0.254) (layer B.Cu) (net 27))
(segment (start 235.1048 177.6492) (end 233.022 177.6492) (width 0.254) (layer B.Cu) (net 27))
(segment (start 235.9684 176.7856) (end 235.1048 177.6492) (width 0.254) (layer B.Cu) (net 27))
(segment (start 235.9684 171.096) (end 235.9684 176.7856) (width 0.254) (layer B.Cu) (net 27))
(segment (start 232.5902 167.7178) (end 235.9684 171.096) (width 0.254) (layer B.Cu) (net 27))
(segment (start 230.9392 178.1064) (end 228.3992 175.5664) (width 0.254) (layer B.Cu) (net 28))
(segment (start 235.7652 178.1064) (end 230.9392 178.1064) (width 0.254) (layer B.Cu) (net 28))
(segment (start 237.086 176.7856) (end 235.7652 178.1064) (width 0.254) (layer B.Cu) (net 28))
(segment (start 237.086 169.572) (end 237.086 176.7856) (width 0.254) (layer B.Cu) (net 28))
(segment (start 235.2318 167.7178) (end 237.086 169.572) (width 0.254) (layer B.Cu) (net 28))
(segment (start 236.47959 178.56041) (end 228.85321 178.56041) (width 0.254) (layer B.Cu) (net 29))
(segment (start 228.85321 178.56041) (end 225.8592 175.5664) (width 0.254) (layer B.Cu) (net 29))
(segment (start 237.8988 177.1412) (end 236.47959 178.56041) (width 0.254) (layer B.Cu) (net 29))
(segment (start 237.8988 167.7178) (end 237.8988 177.1412) (width 0.254) (layer B.Cu) (net 29))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 248.262 114.581) (end 248.262 115.71237) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 115.71237) (end 248.262 117.121) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 129.821) (end 248.262 130.95237) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 130.95237) (end 248.262 132.361) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 127.281) (end 248.262 129.821) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 124.741) (end 248.262 125.87237) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 125.87237) (end 248.262 127.281) (width 0.254) (layer B.Cu) (net 29))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 248.262 122.201) (end 248.262 123.33237) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 123.33237) (end 248.262 124.741) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 119.661) (end 248.262 122.201) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 117.121) (end 248.262 118.25237) (width 0.254) (layer B.Cu) (net 29))
(segment (start 248.262 118.25237) (end 248.262 119.661) (width 0.254) (layer B.Cu) (net 29))
(via (at 249.151 165.380994) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 29))
(segment (start 248.576264 165.380994) (end 249.151 165.380994) (width 0.254) (layer B.Cu) (net 29))
(segment (start 237.49 167.6924) (end 239.801406 165.380994) (width 0.254) (layer B.Cu) (net 29))
(segment (start 239.801406 165.380994) (end 248.576264 165.380994) (width 0.254) (layer B.Cu) (net 29))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 249.659 164.872994) (end 249.151 165.380994) (width 0.254) (layer F.Cu) (net 29))
(segment (start 249.659 142.14) (end 249.659 164.872994) (width 0.254) (layer F.Cu) (net 29))
(via (at 249.532 142.14) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 29))
(segment (start 249.659 142.14) (end 249.532 142.14) (width 0.254) (layer F.Cu) (net 29))
(segment (start 249.532 133.631) (end 248.262 132.361) (width 0.254) (layer B.Cu) (net 29))
(segment (start 249.532 142.14) (end 249.532 133.631) (width 0.254) (layer B.Cu) (net 29))
Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
(segment (start 242.57 167.6924) (end 239.401378 170.861022) (width 0.254) (layer F.Cu) (net 30))
(segment (start 226.709199 172.176401) (end 225.8592 173.0264) (width 0.254) (layer F.Cu) (net 30))
(segment (start 239.401378 170.861022) (end 228.024578 170.861022) (width 0.254) (layer F.Cu) (net 30))
(segment (start 228.024578 170.861022) (end 226.709199 172.176401) (width 0.254) (layer F.Cu) (net 30))
(segment (start 224.7416 170.2578) (end 225.6306 170.2578) (width 0.254) (layer B.Cu) (net 31))
(segment (start 227.549201 172.176401) (end 228.3992 173.0264) (width 0.254) (layer B.Cu) (net 31))
(segment (start 225.6306 170.2578) (end 227.549201 172.176401) (width 0.254) (layer B.Cu) (net 31))
(segment (start 222.2524 167.7686) (end 224.7416 170.2578) (width 0.254) (layer B.Cu) (net 31))
(segment (start 227.4086 170.3086) (end 228.2214 170.3086) (width 0.254) (layer B.Cu) (net 32))
(segment (start 228.2214 170.3086) (end 230.9392 173.0264) (width 0.254) (layer B.Cu) (net 32))
(segment (start 224.8686 167.7686) (end 227.4086 170.3086) (width 0.254) (layer B.Cu) (net 32))
(segment (start 233.114031 172.661231) (end 233.4792 173.0264) (width 0.254) (layer F.Cu) (net 33))
(segment (start 227.434 167.7686) (end 229.2882 169.6228) (width 0.254) (layer B.Cu) (net 33))
(segment (start 230.0756 169.6228) (end 233.4792 173.0264) (width 0.254) (layer B.Cu) (net 33))
(segment (start 229.2882 169.6228) (end 230.0756 169.6228) (width 0.254) (layer B.Cu) (net 33))
(segment (start 235.2064 173.8392) (end 233.4792 175.5664) (width 0.254) (layer B.Cu) (net 34))
(segment (start 235.2064 172.9756) (end 235.2064 173.8392) (width 0.254) (layer B.Cu) (net 34))
(segment (start 229.9994 167.7686) (end 235.2064 172.9756) (width 0.254) (layer B.Cu) (net 34))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 212.876 109.0775) (end 212.876 107.676) (width 0.254) (layer F.Cu) (net 35))
(segment (start 221.763968 98.788032) (end 246.185855 98.788032) (width 0.254) (layer F.Cu) (net 35))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 212.876 107.676) (end 221.763968 98.788032) (width 0.254) (layer F.Cu) (net 35))
(segment (start 246.185855 98.788032) (end 246.760591 98.788032) (width 0.254) (layer F.Cu) (net 35))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(via (at 246.760591 98.788032) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 35))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 246.760591 98.213296) (end 246.760591 98.788032) (width 0.254) (layer B.Cu) (net 35))
(segment (start 247.246 97.727887) (end 246.760591 98.213296) (width 0.254) (layer B.Cu) (net 35))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 247.246 64.84272) (end 247.246 97.727887) (width 0.254) (layer B.Cu) (net 35))
(segment (start 245.16828 62.765) (end 247.246 64.84272) (width 0.254) (layer B.Cu) (net 35))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 213.376 108.25875) (end 221.91275 99.722) (width 0.254) (layer F.Cu) (net 36))
(segment (start 213.376 109.0775) (end 213.376 108.25875) (width 0.254) (layer F.Cu) (net 36))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(segment (start 221.91275 99.722) (end 247.433264 99.722) (width 0.254) (layer F.Cu) (net 36))
Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
(segment (start 247.433264 99.722) (end 248.008 99.722) (width 0.254) (layer F.Cu) (net 36))
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
(via (at 248.008 99.722) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 36))
(segment (start 247.70828 99.42228) (end 248.008 99.722) (width 0.254) (layer B.Cu) (net 36))
(segment (start 247.70828 62.765) (end 247.70828 99.42228) (width 0.254) (layer B.Cu) (net 36))
(segment (start 221.144264 155.094) (end 221.719 155.094) (width 0.254) (layer B.Cu) (net 37))
(segment (start 217.401 155.093978) (end 217.401022 155.094) (width 0.254) (layer B.Cu) (net 37))
(via (at 221.719 155.094) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 37))
(segment (start 217.401022 155.094) (end 221.144264 155.094) (width 0.254) (layer B.Cu) (net 37))
(via (at 209.628608 155.368881) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 37))
(segment (start 209.55 160.0724) (end 209.55 155.447489) (width 0.254) (layer F.Cu) (net 37))
(segment (start 209.55 155.447489) (end 209.628608 155.368881) (width 0.254) (layer F.Cu) (net 37))
(segment (start 217.401 155.094) (end 210.478225 155.094) (width 0.254) (layer B.Cu) (net 37))
(segment (start 210.203344 155.368881) (end 209.628608 155.368881) (width 0.254) (layer B.Cu) (net 37))
(segment (start 210.478225 155.094) (end 210.203344 155.368881) (width 0.254) (layer B.Cu) (net 37))
(segment (start 209.876 125.584997) (end 221.719 137.427996) (width 0.254) (layer F.Cu) (net 37))
(segment (start 209.876 124.4025) (end 209.876 125.584997) (width 0.254) (layer F.Cu) (net 37))
(segment (start 221.719 154.519264) (end 221.719 155.094) (width 0.254) (layer F.Cu) (net 37))
(segment (start 221.719 137.427996) (end 221.719 154.519264) (width 0.254) (layer F.Cu) (net 37))
(segment (start 215.429264 129.948) (end 216.004 129.948) (width 0.254) (layer F.Cu) (net 38))
(segment (start 210.876 125.394736) (end 215.429264 129.948) (width 0.254) (layer F.Cu) (net 38))
(segment (start 210.876 124.4025) (end 210.876 125.394736) (width 0.254) (layer F.Cu) (net 38))
(via (at 216.004 129.948) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 38))
(segment (start 216.004 129.948) (end 215.429264 129.948) (width 0.254) (layer B.Cu) (net 38))
(via (at 211.432 129.948) (size 0.8128) (drill 0.4064) (layers F.Cu B.Cu) (net 38))
(segment (start 215.429264 129.948) (end 211.432 129.948) (width 0.254) (layer B.Cu) (net 38))
(segment (start 212.4988 131.0148) (end 212.4988 144.807) (width 0.254) (layer F.Cu) (net 38))
(segment (start 211.432 129.948) (end 212.4988 131.0148) (width 0.254) (layer F.Cu) (net 38))
(segment (start 237.49 159.0184) (end 237.49 160.0724) (width 0.254) (layer F.Cu) (net 39))
(segment (start 237.467 158.9954) (end 237.49 159.0184) (width 0.254) (layer F.Cu) (net 39))
(segment (start 227.01166 134.382898) (end 227.063866 134.382898) (width 0.254) (layer F.Cu) (net 39))
(segment (start 227.063866 134.382898) (end 237.467 144.786032) (width 0.254) (layer F.Cu) (net 39))
(segment (start 226.099308 133.470546) (end 227.01166 134.382898) (width 0.254) (layer F.Cu) (net 39))
(segment (start 216.961819 124.280851) (end 226.099308 133.41834) (width 0.254) (layer F.Cu) (net 39))
(segment (start 237.467 144.786032) (end 237.467 158.9954) (width 0.254) (layer F.Cu) (net 39))
(segment (start 216.961819 122.349854) (end 216.961819 124.280851) (width 0.254) (layer F.Cu) (net 39))
(segment (start 226.099308 133.41834) (end 226.099308 133.470546) (width 0.254) (layer F.Cu) (net 39))
(segment (start 216.351964 121.74) (end 216.961819 122.349854) (width 0.254) (layer F.Cu) (net 39))
(segment (start 215.5385 121.74) (end 216.351964 121.74) (width 0.254) (layer F.Cu) (net 39))
(segment (start 232.41 140.878534) (end 232.41 159.0184) (width 0.254) (layer F.Cu) (net 40))
(segment (start 232.41 159.0184) (end 232.41 160.0724) (width 0.254) (layer F.Cu) (net 40))
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Silk screen cleanups
2020-04-14 05:29:19 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add 16-pin socket for custom interface/prototyping
2020-04-16 21:56:06 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
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ATMega2560 PCB fixes and updates - add additional key matrix connector (for custom matrix including Apple 2) - Fix bypassed diodes. Diodes on rows 8-15 should have been - jumpered (bypassed), but instead were standard diode footprints.
2020-05-12 22:12:07 +00:00
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Add Atmega2560-based ASCII interface board
2020-04-14 01:54:56 +00:00
)
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