fix register confusion if interleave=0

2023-08-30 19:00:56 -04:00 · 2023-08-30 19:00:56 -04:00 · a41a656906
parent 017a7b214b
commit a41a656906
1 changed files with 2 additions and 0 deletions
--- a/0BOOT.S
+++ b/0BOOT.S
@ -225,6 +225,8 @@ read
 !if interleave=1 {
        tax
        ldy     $100, x
+} else {
+        tay
 }
        sty     <(sector+1)     ;store index for later
        ldx     <addrtbl, y     ;fetch corresponding address