Replaced classic approach of generating dependency files via rule with generating them as side effect of generating object files. The issue with "No rule to make target ..." is solved as suggested in http://make.paulandlesley.org/autodep.html.

At least with gcc (and cc65) the dependency files are generated without an additional run of the C compiler. This is especially beneficial on Cygwin because of the fork() performance issue.

Makefile.include

@@ -87,6 +87,7 @@ CONTIKI_OBJECTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(CONTIKI_SOURCEFI
 PROJECT_OBJECTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(PROJECT_SOURCEFILES)}}
 
 ### Include application makefiles
+
 ifdef APPS
   APPDIRS += ${wildcard ${addprefix $(CONTIKI)/apps/, $(APPS)} \
                 ${addprefix $(CONTIKI)/platform/$(TARGET)/apps/, $(APPS)}}
@@ -100,6 +101,7 @@ ifdef APPS
 endif
 
 ### Include target makefile (TODO Unsafe?)
+
 target_makefile := $(wildcard $(CONTIKI)/platform/$(TARGET)/Makefile.$(TARGET))
 
 # Check if the target makefile exists
@@ -136,6 +138,15 @@ ifneq ($(MAKECMDGOALS),clean)
 				   $(PROJECT_SOURCEFILES:.c=.d)}
 endif
 
+### See http://make.paulandlesley.org/autodep.html#advanced
+
+define FINALIZE_DEPENDENCY
+cp $(@:.o=.d) $(@:.o=.$$$$); \
+sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
+    -e '/^$$/ d' -e 's/$$/ :/' < $(@:.o=.$$$$) >> $(@:.o=.d); \
+rm -f $(@:.o=.$$$$)
+endef
+
 clean:
 	rm -f *~ *core core *.srec \
 	*.lst *.map \
@@ -151,7 +162,8 @@ endif
 
 ifndef CUSTOM_RULE_C_TO_OBJECTDIR_O
 $(OBJECTDIR)/%.o: %.c
-	$(CC) $(CFLAGS) -c $< -o $@
+	$(CC) $(CFLAGS) -MMD -c $< -o $@
+	@$(FINALIZE_DEPENDENCY)
 endif
 
 ifndef CUSTOM_RULE_S_TO_OBJECTDIR_O
@@ -178,21 +190,6 @@ contiki-$(TARGET).a: $(CONTIKI_OBJECTFILES)
 	$(AR) $(AROPTS) $@ $^
 endif
 
-ifndef CCDEP
-  CCDEP = $(CC)
-endif
-ifndef CDEPFLAGS
-  CDEPFLAGS = $(CFLAGS)
-endif
-
-ifndef CUSTOM_RULE_C_TO_OBJECTDIR_D
-$(OBJECTDIR)/%.d: %.c
-	@echo Making dependencies for $<; set -e; rm -f $@; \
-	$(CCDEP) -MM $(CDEPFLAGS) $< > $@.$$$$; \
-	sed 's,\($*\)\.o[ :]*,$(OBJECTDIR)/\1.o $@ : ,g' < $@.$$$$ > $@; \
-	rm -f $@.$$$$
-endif
-
 ifndef LD
   LD = $(CC)
 endif

cpu/6502/Makefile.6502

@@ -30,7 +30,7 @@
 #
 # Author: Oliver Schmidt <ol.sc@web.de>
 #
-# $Id: Makefile.6502,v 1.27 2008/05/22 19:43:37 oliverschmidt Exp $
+# $Id: Makefile.6502,v 1.28 2009/07/02 22:36:35 oliverschmidt Exp $
 #
 
 ifndef CC65_INC
@@ -77,16 +77,13 @@ AROPTS  = a
 
 .SUFFIXES:
 
-CUSTOM_RULE_C_TO_OBJECTDIR_D = 1
-# No explicit dependency file generation necessary since it is done 
-# as compilation side effect using the --create-dep compiler option
-
 CUSTOM_RULE_C_TO_OBJECTDIR_O = 1
 $(OBJECTDIR)/%.o: %.c
 	$(CC) $(CFLAGS) --create-dep $< -o $(@:.o=.s)
 	@$(AS) $(ASFLAGS) $(@:.o=.s) -o $@
 	@sed 's!.s:!.o:!' < $(@:.o=.u) > $(@:.o=.d)
 	@rm -f $(@:.o=.s) $(@:.o=.u)
+	@$(FINALIZE_DEPENDENCY)
 
 CUSTOM_RULE_C_TO_CO = 1
 %.co: %.c

cpu/z80/Makefile.z80

@@ -2,7 +2,7 @@
 # Makefile for z80/SDCC
 # @author Takahide Matsutsuka <markn@markn.org>
 #
-# $Id: Makefile.z80,v 1.11 2007/12/21 00:49:57 oliverschmidt Exp $
+# $Id: Makefile.z80,v 1.12 2009/07/02 22:36:35 oliverschmidt Exp $
 #
 
 ### Compiler definitions
@@ -14,7 +14,6 @@ OBJCOPY  = objcopy
 STRIP    = strip
 
 ### Custom rules
-CUSTOM_RULE_C_TO_OBJECTDIR_D=1
 CUSTOM_RULE_ALLOBJS_TO_TARGETLIB=1
 CUSTOM_RULE_LINK=1