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tmr imts works. I'm not thrilled with how the interrupts and modes are
set... but I'm not sure what to do about it. The big problem is that I have to be in user mode to service irqs, but I can't enable and disable F and I in usermode. All I can do is an swi and then have handler which lets me enable or disable them (like a mini-syscall).
This commit is contained in:
Mariano Alvira
parent
10fdafbcb2
commit
bdbf279d0f
6
Makefile
6
Makefile
@ -63,14 +63,14 @@ all: src/start.o src/isr.o $(ALL)
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tests/nvm-read.obj: src/maca.o src/nvm.o
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tests/rftest-rx.obj: src/maca.o src/nvm.o
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tests/rftest-tx.obj: src/maca.o src/nvm.o
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tests/tmr-ints.obj: src/interrupt-utils.o src/sys-interrupt.o src/isr.o
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tests/tmr-ints.obj: src/isr.o
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NOTHUMB_CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
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-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
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-I$(TOPDIR)/include \
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-fno-builtin -ffreestanding -nostdinc -isystem \
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$(gccincdir) -pipe
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NOTHUMB_CPPFLAGS_EXTRA = -march=armv4t -mlong-calls -mthumb-interwork -mtune=arm7tdmi-s -DCONFIG_ARM -D__ARM__
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NOTHUMB_CPPFLAGS_EXTRA = -march=armv4t -mlong-calls -mtune=arm7tdmi-s -DCONFIG_ARM -D__ARM__ #-mthumb-interwork
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src/isr.o: src/isr.c
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@ -88,7 +88,7 @@ src/isr.o: src/isr.c
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%.dis: %.obj
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$(OBJDUMP) -SD $< > $@
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%.obj: $(LDSCRIPT) %.o src/interrupt-utils.o
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%.obj: $(LDSCRIPT) %.o #src/interrupt-utils.o
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$(LD) $(LDFLAGS) $(AOBJS) \
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--start-group $(PLATFORM_LIBS) --end-group \
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-Map $*.map $^ -o $@
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@ -26,7 +26,7 @@
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# clean the slate ...
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PLATFORM_LDFLAGS =
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PLATFORM_RELFLAGS = -fno-strict-aliasing -fno-common -ffixed-r8 -ffunction-sections -msoft-float
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PLATFORM_CPPFLAGS = -march=armv4t -mlong-calls -mcallee-super-interworking -mthumb -mthumb-interwork -mtune=arm7tdmi-s -DCONFIG_ARM -D__ARM__
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PLATFORM_CPPFLAGS = -march=armv4t -mlong-calls -mtune=arm7tdmi-s -DCONFIG_ARM -D__ARM__ #-mcallee-super-interworking -mthumb -mthumb-interwork
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TEXT_BASE = 0x00400000
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#########################################################################
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@ -13,7 +13,7 @@
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#define no_isrs() no_tmr_isr();
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#define enable_tmr_irq() *(volatile uint32_t *)(INTENNUM)
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#define enable_tmr_irq() *(volatile uint32_t *)(INTENNUM) = 5;
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#define no_tmr_isr() void tmr_isr(void) { return; }
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extern void tmr_isr(void);
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@ -1,15 +1,15 @@
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#include "embedded_types.h"
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#include "interrupt-utils.h"
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//#include "interrupt-utils.h"
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#include "isr.h"
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#define reg32(x) (*(volatile uint32_t *)(x))
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__attribute__ ((interrupt("IRQ")))
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//__attribute__ ((interrupt("IRQ")))
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void isr(void)
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{
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// ISR_ENTRY();
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/* check for TMR0 interrupt */
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// tmr_isr(); // led turns off if I have this, indicating that the isr does jump to tmr_isr
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tmr_isr(); // led turns off if I have this, indicating that the isr does jump to tmr_isr
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// if(reg32(INTSRC) & (1<<5)) { tmr_isr(); }
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// asm("SUBS PC,R14_IRQ,#4")
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// enableIRQ(); // I think this is necessary, but the LED never turns off when I have this
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@ -17,4 +17,6 @@ void isr(void)
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/* putting anything in here breaks the other code :( */
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// asm("ldmfd sp!, {r0-r12,lr}");
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// enableIRQ();
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}
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112
src/start.S
112
src/start.S
@ -23,15 +23,33 @@
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* MA 02111-1307 USA
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*/
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
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.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
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.equ USR_MODE, 0x10
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.equ FIQ_MODE, 0x11
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.equ IRQ_MODE, 0x12
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.equ SVC_MODE, 0x13
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.equ ABT_MODE, 0x17
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.equ UND_MODE, 0x1B
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.equ SYS_MODE, 0x1F
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.equ usr_stack_size, 256*4
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.equ irq_stack_size, 128*4
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.equ fiq_stack_size, 128*4
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.equ und_stack_size, 32*4
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.equ abt_stack_size, 32*4
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.equ sup_stack_size, 32*4
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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*/
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.set base, .
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.set _rom_data_init, 0x108d0
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@ -72,7 +90,37 @@ ROM_var_end: .word 0
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.code 32
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.align
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_begin:
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ldr r1,=_system_stack
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msr cpsr_c,#(SVC_MODE | I_BIT | F_BIT)
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add r1,r1,#sup_stack_size
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mov sp,r1
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msr cpsr_c,#(IRQ_MODE | I_BIT | F_BIT)
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add r1,r1,#irq_stack_size
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mov sp,r1
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msr cpsr_c,#(FIQ_MODE | I_BIT | F_BIT)
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add r1,r1,#fiq_stack_size
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mov sp,r1
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msr cpsr_c,#(ABT_MODE | I_BIT | F_BIT)
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add r1,r1,#abt_stack_size
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mov sp,r1
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msr cpsr_c,#(UND_MODE | I_BIT | F_BIT)
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add r1,r1,#und_stack_size
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mov sp,r1
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// msr cpsr_c,#(USR_MODE | I_BIT | F_BIT)
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// add r1,r1,#usr_stack_size
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// mov sp,r1
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bl _rom_data_init+.-base
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msr cpsr_c,#(SVC_MODE) // turn on interrupts --- for debug only
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msr cpsr_c,#(USR_MODE) // turn on interrupts --- for debug only
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// swi
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b main
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_undefined_instruction: .word undefined_instruction
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@ -82,9 +130,8 @@ _data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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@ -105,6 +152,10 @@ _TEXT_BASE:
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_armboot_start:
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.word _start
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_system_stack:
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. = . + usr_stack_size + irq_stack_size + fiq_stack_size + und_stack_size + abt_stack_size + sup_stack_size
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/*
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* These are defined in the board-specific linker script.
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*/
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@ -118,6 +169,8 @@ _bss_end:
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_start_armboot: .word main
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/*
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*************************************************************************
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*
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@ -139,42 +192,6 @@ cpu_init_crit:
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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@ -197,8 +214,18 @@ not_used:
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.align 5
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irq:
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push {lr}
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movs lr,pc
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b isr
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.align 5
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pop {lr}
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subs pc,r14,#4 // suggested irq return cmd
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// STMFD sp!, {r0-r12,lr}
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// MOVNE lr,pc
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// ldr r0, =isr
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// BX r0
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// LDMFD r13!, {r0-r12,r14}
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// MOVS PC, R14
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// subs pc, r14, #4
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fiq:
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.align 5
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@ -206,3 +233,4 @@ fiq:
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.globl reset_cpu
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reset_cpu:
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mov pc, r0
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@ -47,7 +47,7 @@
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#define reg16(x) (*(volatile uint16_t *)(x))
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#include "embedded_types.h"
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#include "sys-interrupt.h"
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//#include "sys-interrupt.h"
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#include "isr.h"
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@ -76,9 +76,22 @@ void tmr_isr(void) {
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}
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/* void enIRQ(void) { */
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/* asm volatile ( */
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/* ".code 32;" */
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/* "msr cpsr_c,#0x10;" */
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/* ".code 16;" */
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/* ); */
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/* } */
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__attribute__ ((section ("startup")))
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void main(void) {
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// *(volatile uint32_t *)0x80020010 = 0x20;
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// *(volatile uint32_t *)0x80020034 = 0xffff; //force an int.
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/* pin direction */
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led_init();
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@ -94,8 +107,8 @@ void main(void) {
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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reg16(TMR_ENBL) = 0; /* tmrs reset to enabled */
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reg16(TMR0_SCTRL) = 0;
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reg16(TMR0_CSCTRL) =0x0040;
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reg16(TMR0_SCTRL) = 0;
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reg16(TMR0_CSCTRL) =0x0040;
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reg16(TMR0_LOAD) = 0; /* reload to zero */
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reg16(TMR0_COMP_UP) = 18750; /* trigger a reload at the end */
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reg16(TMR0_CMPLD1) = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
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@ -106,7 +119,8 @@ void main(void) {
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led_on();
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enable_tmr_irq();
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enableIRQ();
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// enIRQ();
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while(1) {
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/* sit here and let the interrupts do the work */
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