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tmr
This commit is contained in:
Mariano Alvira
parent
a2b51b0e3c
commit
cd5e5b1706
@ -6,6 +6,7 @@
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#include "gpio.h"
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#include "crm.h"
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#include "nvm.h"
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#include "tmr.h"
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#include "uart1.h"
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#include "utils.h"
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92
libmc1322x/include/tmr.h
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92
libmc1322x/include/tmr.h
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@ -0,0 +1,92 @@
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#include "utils.h"
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/* Timer registers are all 16-bit wide with 16-bit access only */
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#define TMR_OFFSET (0x20)
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#define TMR_BASE (0x80007000)
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#define TMR0_BASE (TMR_BASE)
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#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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/* one enable register to rule them all */
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#define TMR_ENBL ((volatile uint16_t *) TMR0_BASE + TMR_REGOFF_ENBL)
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/* Timer 0 registers */
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#define TMR0_COMP1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP1))
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CAPT))
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#define TMR0_LOAD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_LOAD))
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#define TMR0_HOLD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_HOLD))
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#define TMR0_CNTR ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
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#define TMR0_CTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
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#define TMR0_SCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_SCTRL))
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#define TMR0_CMPLD1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD1))
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#define TMR0_CMPLD2 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD2))
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#define TMR0_CSCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 1 registers */
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#define TMR1_COMP1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP1))
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#define TMR1_COMP_UP TMR1_COMP1
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#define TMR1_COMP2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP2))
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#define TMR1_COMP_DOWN TMR1_COMP2
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#define TMR1_CAPT ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CAPT))
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#define TMR1_LOAD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_LOAD))
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#define TMR1_HOLD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_HOLD))
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#define TMR1_CNTR ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
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#define TMR1_CTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
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#define TMR1_SCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_SCTRL))
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#define TMR1_CMPLD1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD1))
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#define TMR1_CMPLD2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD2))
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#define TMR1_CSCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 2 registers */
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#define TMR2_COMP1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP1))
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#define TMR2_COMP_UP TMR2_COMP1
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#define TMR2_COMP2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP2))
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#define TMR2_COMP_DOWN TMR2_COMP2
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#define TMR2_CAPT ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CAPT))
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#define TMR2_LOAD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_LOAD))
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#define TMR2_HOLD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_HOLD))
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#define TMR2_CNTR ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
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#define TMR2_CTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
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#define TMR2_SCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_SCTRL))
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#define TMR2_CMPLD1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD1))
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#define TMR2_CMPLD2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD2))
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#define TMR2_CSCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 3 registers */
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#define TMR3_COMP1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP1))
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#define TMR3_COMP_UP TMR3_COMP1
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#define TMR3_COMP2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP2))
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#define TMR3_COMP_DOWN TMR3_COMP2
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#define TMR3_CAPT ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CAPT))
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#define TMR3_LOAD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_LOAD))
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#define TMR3_HOLD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_HOLD))
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#define TMR3_CNTR ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
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#define TMR3_CTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
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#define TMR3_SCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_SCTRL))
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#define TMR3_CMPLD1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD1))
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#define TMR3_CMPLD2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD2))
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#define TMR3_CSCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CSCTRL))
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#define TCF 15
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#define TCF1 4
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#define TCF2 5
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#define TMR(num, reg) CAT2(TMR,num,_##reg)
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@ -6,7 +6,7 @@ MC1322X := ..
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COBJS := tests.o put.o
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# all of the target programs to build
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TARGETS := blink-red blink-green blink-blue blink-white blink-allio uart1-loopback nvm-read nvm-write romimg flasher
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TARGETS := blink-red blink-green blink-blue blink-white blink-allio uart1-loopback nvm-read nvm-write romimg flasher tmr
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include $(MC1322X)/Makefile.include
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@ -2,6 +2,7 @@
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#define TESTS_H
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#include "put.h"
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#include "led.h"
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void uart1_init(uint16_t inc, uint16_t mod);
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void print_welcome(char* testname);
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44
tests/tmr.c
44
tests/tmr.c
@ -1,21 +1,15 @@
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#define MBAR_GPIO 0x80000000
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#define GPIO_PAD_DIR0 0x80000000
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#define GPIO_DATA0 0x80000008
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#define UART1_DATA 0x80005008
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#define DELAY 400000
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#include <mc1322x.h>
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#include <board.h>
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#include "embedded_types.h"
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#include "utils.h"
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#include "timer.h"
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#include "led.h"
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#include "tests.h"
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#include "config.h"
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#define LED LED_YELLOW
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__attribute__ ((section ("startup")))
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void main(void) {
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/* pin direction */
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reg32(GPIO_PAD_DIR0) = LED;
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*GPIO_PAD_DIR0 = LED;
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/* timer setup */
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/* CTRL */
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@ -28,28 +22,28 @@ void main(void) {
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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reg16(TMR_ENBL) = 0; /* tmrs reset to enabled */
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reg16(TMR0_SCTRL) = 0;
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reg16(TMR0_LOAD) = 0; /* reload to zero */
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reg16(TMR0_COMP_UP) = 18750; /* trigger a reload at the end */
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reg16(TMR0_CMPLD1) = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
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reg16(TMR0_CNTR) = 0; /* reset count register */
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reg16(TMR0_CTRL) = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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reg16(TMR_ENBL) = 0xf; /* enable all the timers --- why not? */
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*TMR_ENBL = 0; /* tmrs reset to enabled */
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*TMR0_SCTRL = 0;
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*TMR0_LOAD = 0; /* reload to zero */
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*TMR0_COMP_UP = 18750; /* trigger a reload at the end */
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*TMR0_CMPLD1 = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
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*TMR0_CNTR = 0; /* reset count register */
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*TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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*TMR_ENBL = 0xf; /* enable all the timers --- why not? */
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while(1) {
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/* blink on */
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reg32(GPIO_DATA0) = LED;
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*GPIO_DATA0 = LED;
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while((reg16(TMR0_SCTRL)>>15) == 0) { continue; }
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reg16(TMR0_SCTRL) = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
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while((*TMR0_SCTRL >> 15) == 0) { continue; }
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*TMR0_SCTRL = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
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/* blink off */
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reg32(GPIO_DATA0) = 0x00000000;
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*GPIO_DATA0 = 0x00000000;
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while((reg16(TMR0_SCTRL)>>15) == 0) { continue; }
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reg16(TMR0_SCTRL) = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
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while((*TMR0_SCTRL >> 15) == 0) { continue; }
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*TMR0_SCTRL = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
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};
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}
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