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25c07613c2
The Intel Quark X1000 SoC includes a message bus that is accessible via PCI configuration registers. It communicates to various SoC components such as the Isolated Memory Region (IMR) registers and the Remote Management Unit. This patch adds a driver for accessing the message bus.
114 lines
3.8 KiB
C
114 lines
3.8 KiB
C
/*
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* Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "msg-bus.h"
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#include "pci.h"
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/** Message bus control register */
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#define MCR_PCI_REG_ADDR 0xD0
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/** Message data register */
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#define MDR_PCI_REG_ADDR 0xD4
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/** Message control register extension */
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#define MCRX_PCI_REG_ADDR 0xD8
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typedef union mcr {
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struct {
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uint32_t : 4;
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uint32_t byte_en : 4;
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uint32_t reg_off : 8;
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uint32_t port : 8;
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uint32_t opcode : 8;
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};
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uint32_t raw;
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} mcr_t;
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typedef union mcrx {
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struct {
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uint32_t : 8;
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uint32_t reg_off : 24;
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};
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uint32_t raw;
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} mcrx_t;
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/*---------------------------------------------------------------------------*/
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static void
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request_op(uint8_t port, uint32_t reg_off, uint8_t opcode)
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{
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pci_config_addr_t pci_addr = { .raw = 0 };
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mcr_t mcr = { .raw = 0 };
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mcrx_t mcrx = { .raw = 0 };
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pci_addr.reg_off = MCR_PCI_REG_ADDR;
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mcr.opcode = opcode;
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mcr.byte_en = 0xF;
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mcr.port = port;
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mcr.reg_off = reg_off & 0xFF;
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pci_config_write(pci_addr, mcr.raw);
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pci_addr.reg_off = MCRX_PCI_REG_ADDR;
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mcrx.reg_off = reg_off >> 8;
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pci_config_write(pci_addr, mcrx.raw);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Read from a message bus register.
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* \param port Port of message bus register to be read.
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* \param reg_off Register/offset identifier of message bus register to read.
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* \param val Storage location for value that has been read.
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*/
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void
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quarkX1000_msg_bus_read(uint8_t port, uint32_t reg_off, uint32_t *val)
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{
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pci_config_addr_t pci_addr = { .raw = 0 };
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request_op(port, reg_off, 0x10);
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pci_addr.reg_off = MDR_PCI_REG_ADDR;
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*val = pci_config_read(pci_addr);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Write to a message bus register.
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* \param port Port of message bus register to be written.
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* \param reg_off Register/offset identifier of message bus register to write.
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* \param val Value to write.
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*/
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void
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quarkX1000_msg_bus_write(uint8_t port, uint32_t reg_off, uint32_t val)
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{
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pci_config_addr_t pci_addr = { .raw = 0 };
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pci_addr.reg_off = MDR_PCI_REG_ADDR;
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pci_config_write(pci_addr, val);
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request_op(port, reg_off, 0x11);
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}
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/*---------------------------------------------------------------------------*/
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