2018-09-29 04:59:14 +00:00
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; Display e-mail demo
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; 40x96 graphics as well as half-screen text manipulation
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check_email:
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;===================
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; init screen
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jsr TEXT
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jsr HOME
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bit KEYRESET
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;===================
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; init vars
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lda #0
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sta DRAW_PAGE
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;=============================
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; Load graphic page0
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lda #$0c
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sta BASH
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lda #$00
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sta BASL ; load image to $c00
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lda #<email_low
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sta GBASL
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lda #>email_low
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sta GBASH
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jsr load_rle_gr
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lda #4
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sta DRAW_PAGE
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jsr gr_copy_to_current ; copy to page1
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; GR part
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bit PAGE1
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bit LORES ; 4
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bit SET_GR ; 4
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bit FULLGR ; 4
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;=============================
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; Load graphic page1
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lda #$0c
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sta BASH
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lda #$00
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sta BASL ; load image to $c00
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lda #<email_high
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sta GBASL
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lda #>email_high
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sta GBASH
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jsr load_rle_gr
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lda #0
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sta DRAW_PAGE
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jsr gr_copy_to_current
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; GR part
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bit PAGE0
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;==============================
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; setup graphics for vapor lock
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;==============================
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jsr vapor_lock ; 6
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; vapor lock returns with us at beginning of hsync in line
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; 114 (7410 cycles), so with 5070 lines to go
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jsr gr_copy_to_current ; 6+ 9292
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; now we have 322 left
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; GR part
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bit LORES ; 4
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bit SET_GR ; 4
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bit FULLGR ; 4
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; 322 - 12 = 310
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; - 3 for jmp
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; 307
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; Try X=9 Y=6 cycles=307
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ldy #6 ; 2
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celoopA:ldx #9 ; 2
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celoopB:dex ; 2
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bne celoopB ; 2nt/3
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dey ; 2
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bne celoopA ; 2nt/3
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2018-09-29 15:41:43 +00:00
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jmp em_begin_loop
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2018-09-29 04:59:14 +00:00
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.align $100
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;================================================
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; Email Loop
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;================================================
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; each scan line 65 cycles
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; 1 cycle each byte (40cycles) + 25 for horizontal
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; Total of 12480 cycles to draw screen
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; Vertical blank = 4550 cycles (70 scan lines)
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; Total of 17030 cycles to get back to where was
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; For this part we want
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; T00000000000000000000 G0000000000000000000000
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; T00000000000000000000 G0000000000000000000000
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; T00000000000000000000 G1111111111111111111111
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; T00000000000000000000 G1111111111111111111111
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; T11111111111111111111 G0000000000000000000000
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; T11111111111111111111 G0000000000000000000000
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; T11111111111111111111 G1111111111111111111111
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; T11111111111111111111 G1111111111111111111111
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2018-09-29 15:41:43 +00:00
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; 0,1,0,1 0,0,1,1
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; 54,55,54,55 54,54,55,55
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2018-09-29 04:59:14 +00:00
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2018-09-29 15:41:43 +00:00
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em_begin_loop:
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2018-09-29 04:59:14 +00:00
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2018-09-29 15:41:43 +00:00
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em_display_loop:
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2018-09-29 04:59:14 +00:00
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2018-09-29 17:24:13 +00:00
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ldy #24
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2018-09-29 04:59:14 +00:00
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em_outer_loop:
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2018-09-29 17:24:13 +00:00
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;== line0
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2018-09-29 15:41:43 +00:00
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bit PAGE0 ; 4
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lda #$54 ; 2
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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2018-09-29 17:24:13 +00:00
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;== line1
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2018-09-29 15:41:43 +00:00
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bit PAGE0 ; 4
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lda #$54 ; 2
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2018-09-29 17:24:13 +00:00
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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;== line2
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bit PAGE0 ; 4
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lda #$55 ; 2
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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;== line3
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bit PAGE0 ; 4
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lda #$55 ; 2
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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;== line4
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bit PAGE1 ; 4
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lda #$54 ; 2
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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;== line5
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bit PAGE1 ; 4
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lda #$54 ; 2
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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;== line6
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bit PAGE1 ; 4
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lda #$55 ; 2
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sta draw_line_p1+1 ; 4
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jsr draw_line_1 ; 6
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;== line7
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bit PAGE0 ; 4
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lda #$55 ; 2
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2018-09-29 15:41:43 +00:00
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sta draw_line_p2+1 ; 4
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jsr draw_line_2 ; 6
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2018-09-29 17:24:13 +00:00
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2018-09-29 15:41:43 +00:00
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dey ; 2
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bne em_outer_loop ; 3
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; -1
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2018-09-29 04:59:14 +00:00
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2018-09-29 15:41:43 +00:00
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; 8+17+14 +8+15
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;em_begin_loop:
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;
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;em_display_loop:
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;
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; ldy #96 ; 2
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2018-09-29 04:59:14 +00:00
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2018-09-29 15:41:43 +00:00
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;em_outer_loop:
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2018-09-29 04:59:14 +00:00
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2018-09-29 15:41:43 +00:00
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; line0
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; bit PAGE0 ; 4
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; bit SET_TEXT ; 4
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; nop ; 2
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; nop ; 2
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; nop ; 2
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; nop ; 2
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; nop ; 2
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;==============
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; 33
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; bit PAGE0 ; 4
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; bit SET_GR ; 4
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; lda $0
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; lda $0
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; lda $0
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; lda $0
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; lda $0
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; lda $0
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; lda $0
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; lda $0
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;==============
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; 32
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; line1
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; bit PAGE0 ; 4
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; bit SET_TEXT ; 4
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; nop ; 2
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; nop ; 2
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; nop ; 2
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; nop ; 2
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; nop ; 2
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;
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;==============
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; 33
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; bit PAGE0 ; 4
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; bit SET_GR ; 4
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; lda $0 ; 3
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; lda $0 ; 3
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; lda $0 ; 3
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; nop ; 2
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; nop ; 2
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; nop ; 2
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; nop ; 2
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; nop ; 2
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;==============
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; 27
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;em_page1_loop:
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2018-09-29 04:59:14 +00:00
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2018-09-29 15:41:43 +00:00
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; dey ; 2
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; bne em_outer_loop ; 3
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; -1
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2018-09-29 04:59:14 +00:00
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;======================================================
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; We have 4550 cycles in the vblank, use them wisely
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;======================================================
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; do_nothing should be 4550+1 -2-9 -7= 4533
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jsr do_nothing ; 6
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lda KEYPRESS ; 4
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bpl em_no_keypress ; 3
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jmp em_start_over
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em_no_keypress:
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jmp em_display_loop ; 3
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em_start_over:
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bit KEYRESET ; clear keypress ; 4
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rts ; 6
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2018-09-29 17:24:13 +00:00
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;======================
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; Draw split line
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; with no room for rec/jump at end
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2018-09-29 15:41:43 +00:00
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draw_line_1: ; line0
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; come in with 16
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2018-09-29 17:24:13 +00:00
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lda $0
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2018-09-29 15:41:43 +00:00
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bit SET_TEXT ; 4
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2018-09-29 17:24:13 +00:00
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2018-09-29 15:41:43 +00:00
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nop ; 2
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nop ; 2
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nop ; 2
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nop ; 2
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nop ; 2
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;==============
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; 33
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2018-09-29 17:24:13 +00:00
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nop
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nop
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bit SET_GR ; 4
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2018-09-29 15:41:43 +00:00
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draw_line_p1:
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bit PAGE0 ; 4
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2018-09-29 17:24:13 +00:00
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2018-09-29 15:41:43 +00:00
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lda $0
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lda $0
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lda $0
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lda $0
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2018-09-29 17:24:13 +00:00
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; nop
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; nop
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2018-09-29 15:41:43 +00:00
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nop
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rts
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;==============
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; 32
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2018-09-29 17:24:13 +00:00
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;======================
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; Draw split line
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; with room for 5 cycles of dec/jump at end
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2018-09-29 15:41:43 +00:00
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draw_line_2: ; line0
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; come in with 16
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lda $0 ; 3
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bit SET_TEXT ; 4
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nop ; 2
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nop ; 2
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nop ; 2
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nop ; 2
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nop ; 2
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2018-09-29 17:24:13 +00:00
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nop
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nop
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2018-09-29 15:41:43 +00:00
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;==============
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; 33
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2018-09-29 17:24:13 +00:00
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bit SET_GR ; 4
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2018-09-29 15:41:43 +00:00
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draw_line_p2:
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bit PAGE0 ; 4
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lda $0
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lda $0
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lda $0
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; lda $0
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; nop
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2018-09-29 17:24:13 +00:00
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; nop
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; nop
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2018-09-29 15:41:43 +00:00
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; lda $0
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; lda $0
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rts
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;==============
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; 32
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2018-09-29 04:59:14 +00:00
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.include "email_40_96.inc"
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