224 lines
5.1 KiB
ArmAsm
224 lines
5.1 KiB
ArmAsm
; VMW Minimal Mockingboard Issue Reproducer
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; ZP addresses
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MB_CHUNK_OFFSET = $94
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MB_VALUE = $91
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WAIT = $FCA8 ; 1/2(26+27A+5A^2) us
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; 85 = 19.223ms
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; 86 = 19.6ms
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; 87 = 20.11ms
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; 120 = 37.6ms
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; 240 = 147.25ms
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; left channel
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MOCK_6522_1_ORB = $C400 ; 6522 #1 port b data
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MOCK_6522_1_ORA = $C401 ; 6522 #1 port a data
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MOCK_6522_1_DDRB = $C402 ; 6522 #1 data direction port B
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MOCK_6522_1_DDRA = $C403 ; 6522 #1 data direction port A
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MOCK_6522_1_T1C_L = $C404 ; 6522 #1 Low-order counter
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MOCK_6522_1_T1C_H = $C405 ; 6522 #1 High-order counter
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MOCK_6522_1_T1L_L = $C406 ; 6522 #1 Low-order latch
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MOCK_6522_1_T1L_H = $C407 ; 6522 #1 High-order latch
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MOCK_6522_1_T2C_L = $C408 ; 6522 #1 Timer2 Low-order Latch/Counter
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MOCK_6522_1_T2C_H = $C409 ; 6522 #1 Timer2 High-order Latch/Counter
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MOCK_6522_1_SR = $C40A ; 6522 #1 Shift Register
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MOCK_6522_1_ACR = $C40B ; 6522 #1 Auxiliary Control Register
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MOCK_6522_1_PCR = $C40C ; 6522 #1 Peripheral Control Register
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MOCK_6522_1_IFR = $C40D ; 6522 #1 Interrupt Flag Register
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MOCK_6522_1_IER = $C40E ; 6522 #1 Interrupt Enable Register
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MOCK_6522_1_ORAN = $C40F ; 6522 #1 port a data, no handshake
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; right channel
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MOCK_6522_2_ORB = $C480 ; 6522 #2 port b data
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MOCK_6522_2_ORA = $C481 ; 6522 #2 port a data
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MOCK_6522_2_DDRB = $C482 ; 6522 #2 data direction port B
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MOCK_6522_2_DDRA = $C483 ; 6522 #2 data direction port A
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MOCK_6522_2_T1C_L = $C484 ; 6522 #2 Low-order counter
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MOCK_6522_2_T1C_H = $C485 ; 6522 #2 High-order counter
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MOCK_6522_2_T1L_L = $C486 ; 6522 #2 Low-order latch
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MOCK_6522_2_T1L_H = $C487 ; 6522 #2 High-order latch
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MOCK_6522_2_T2C_L = $C488 ; 6522 #2 Timer2 Low-order Latch/Counter
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MOCK_6522_2_T2C_H = $C489 ; 6522 #2 Timer2 High-order Latch/Counter
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MOCK_6522_2_SR = $C48A ; 6522 #2 Shift Register
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MOCK_6522_2_ACR = $C48B ; 6522 #2 Auxiliary Control Register
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MOCK_6522_2_PCR = $C48C ; 6522 #2 Peripheral Control Register
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MOCK_6522_2_IFR = $C48D ; 6522 #2 Interrupt Flag Register
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MOCK_6522_2_IER = $C48E ; 6522 #2 Interrupt Enable Register
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MOCK_6522_2_ORAN = $C48F ; 6522 #2 port a data, no handshake
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; AY-3-8910 commands on port B
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; RESET BDIR BC1
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MOCK_AY_RESET = $0 ; 0 0 0
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MOCK_AY_INACTIVE = $4 ; 1 0 0
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MOCK_AY_READ = $5 ; 1 0 1
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MOCK_AY_WRITE = $6 ; 1 1 0
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MOCK_AY_LATCH_ADDR = $7 ; 1 1 1
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;=========================
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; Init Variables
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;=========================
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lda #$0
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sta MB_CHUNK_OFFSET
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;============================
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; Init the Mockingboard
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;============================
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;========================
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; Mockingboard Init
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;========================
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; Initialize the 6522s
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; set the data direction for all pins of PortA/PortB to be output
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mockingboard_init:
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lda #$ff ; all 8 pins output (1), portA
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sta MOCK_6522_1_DDRA
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sta MOCK_6522_2_DDRA
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; only 3 pins output (1), port B
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lda #$7
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sta MOCK_6522_1_DDRB
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sta MOCK_6522_2_DDRB
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reset_ay_both:
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;======================
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; Reset Left AY-3-8910
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;======================
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reset_ay_left:
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lda #MOCK_AY_RESET
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sta MOCK_6522_1_ORB
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lda #MOCK_AY_INACTIVE
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sta MOCK_6522_1_ORB
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; AY-3-8913: Wait 5 us
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nop
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nop
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nop
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nop
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nop
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;======================
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; Reset Right AY-3-8910
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;======================
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reset_ay_right:
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lda #MOCK_AY_RESET
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sta MOCK_6522_2_ORB
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lda #MOCK_AY_INACTIVE
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sta MOCK_6522_2_ORB
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; AY-3-8913: Wait 5 us
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nop
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nop
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nop
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nop
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nop
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;=========================
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; Setup initial conditions
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;=========================
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; 5: C CHANNEL COARSE
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ldx #5
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lda #$0 ; always 0
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sta MB_VALUE
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jsr write_ay_address_right
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; 7: ENABLE
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ldx #7
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lda #$38 ; noise disabled, ABC enabled
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sta MB_VALUE
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jsr write_ay_address_right
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; 10: C Amplitude
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ldx #10
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lda #$c ; always volume 12
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sta MB_VALUE
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jsr write_ay_address_right
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; 4: C CHANNEL FINE
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ldx #4
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lda #$51
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sta MB_VALUE
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jsr write_ay_address_right
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main_loop:
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lda #$51
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sta MB_VALUE
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jsr write_ay_value_right
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; delay ~20ms
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lda #87
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jsr WAIT ; wait 20ms or so
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lda #$3C
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sta MB_VALUE
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jsr write_ay_value_right
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; delay ~20ms
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lda #87
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jsr WAIT ; wait 20ms or so
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jmp main_loop
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;=========================================
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; Write Right/Left to save value AY-3-8910
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;=========================================
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; register in X
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; value in MB_VALUE
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; Write sequence
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; ADDRESS: Inactive -> Latch Address -> Addr -> Inactive
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; Programming manual (as well as timing diagrams)
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; say you can flip latch / addr order, but the simulators
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; don't like that.
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; Value: Inactive -> Data -> Write Data -> Inactive
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;
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write_ay_address_right:
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; address
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stx MOCK_6522_2_ORA ; put address on PA1 ; 3
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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sta MOCK_6522_2_ORB ; latch_address on PB1 ; 3
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; on AY-3-8913 hold 300ns, on AY-3-8910 hold 400ns
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_2_ORB ; 3
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; on AY-3-8913 hold 50ns, on AY-3-8910 hold 100ns
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write_ay_value_right:
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lda MB_VALUE ; 3
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sta MOCK_6522_2_ORA ; put value on PA2 ; 4
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; AY-3-8913 + AY-3-8910: 50ns
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; presumably the next two instructions take 6*1us so plenty of time
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_2_ORB ; write on PB2 ; 4
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; AY-3-8913 hold 1800ns, AY-3-8910 500ns
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_2_ORB ; 4
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; AY-3-8913 + AY-3-8910: 100ns
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rts ; 6
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