mirror of https://github.com/buserror/mii_emu.git
sw: Added a big soft switch bitfield
These are fetched often, so might as well cache them into a bitfield, also removed the old BSR state, as it might as well be in that bitfield. Converted all the user of these soft switches to this new bitfield. Signed-off-by: Michel Pollet <buserror@gmail.com>
This commit is contained in:
Michel Pollet
parent
66e2b7707d
commit
73059bfd93
74
src/mii.c
74
src/mii.c
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@ -157,18 +157,19 @@ mii_page_table_update(
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if (!mii->mem_dirty)
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return;
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mii->mem_dirty = 0;
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int altzp = mii_sw(mii, SWALTPZ);
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int page2 = mii_sw(mii, SWPAGE2);
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int store80 = mii_sw(mii, SW80STORE);
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int hires = mii_sw(mii, SWHIRES);
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int ramrd = mii_sw(mii, SWRAMRD);
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int ramwrt = mii_sw(mii, SWRAMWRT);
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int intcxrom = mii_sw(mii, SWINTCXROM);
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int slotc3rom = mii_sw(mii, SWSLOTC3ROM);
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bool altzp = SW_GETSTATE(mii, SWALTPZ);
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bool page2 = SW_GETSTATE(mii, SWPAGE2);
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bool store80 = SW_GETSTATE(mii, SW80STORE);
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bool hires = SW_GETSTATE(mii, SWHIRES);
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bool ramrd = SW_GETSTATE(mii, SWRAMRD);
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bool ramwrt = SW_GETSTATE(mii, SWRAMWRT);
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bool intcxrom = SW_GETSTATE(mii, SWINTCXROM);
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bool slotc3rom = SW_GETSTATE(mii, SWSLOTC3ROM);
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if (mii->trace_cpu)
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printf("%04x: page table update altzp:%02x page2:%02x store80:%02x hires:%02x ramrd:%02x ramwrt:%02x intcxrom:%02x slotc3rom:%02x\n",
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mii->cpu.PC,
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printf("%04x: page table update altzp:%d page2:%d store80:%d "
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"hires:%d ramrd:%d ramwrt:%d intcxrom:%d "
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"slotc3rom:%d\n", mii->cpu.PC,
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altzp, page2, store80, hires, ramrd, ramwrt, intcxrom, slotc3rom);
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// clean slate
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mii_page_set(mii, MII_BANK_MAIN, MII_BANK_MAIN, 0x00, 0xc0);
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@ -191,23 +192,26 @@ mii_page_table_update(
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mii_page_set(mii, MII_BANK_CARD_ROM, _SAME, 0xc1, 0xc7);
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mii_page_set(mii,
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slotc3rom ? MII_BANK_CARD_ROM : MII_BANK_ROM, _SAME, 0xc3, 0xc3);
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bool bsrread = SW_GETSTATE(mii, BSRREAD);
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bool bsrwrite = SW_GETSTATE(mii, BSRWRITE);
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bool bsrpage2 = SW_GETSTATE(mii, BSRPAGE2);
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mii_page_set(mii,
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mii->bsr_mode.read ?
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altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR :
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MII_BANK_ROM,
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mii->bsr_mode.write ?
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altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR :
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MII_BANK_ROM,
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bsrread ?
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altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR :
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MII_BANK_ROM,
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bsrwrite ?
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altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR :
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MII_BANK_ROM,
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0xd0, 0xff);
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// BSR P2
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mii_page_set(mii,
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mii->bsr_mode.read ?
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(altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) +
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mii->bsr_mode.page2 : MII_BANK_ROM,
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mii->bsr_mode.write ?
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(altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) +
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mii->bsr_mode.page2 : MII_BANK_ROM,
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0xd0, 0xdf);
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bsrread ?
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(altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) + bsrpage2 :
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MII_BANK_ROM,
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bsrwrite ?
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(altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) + bsrpage2 :
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MII_BANK_ROM,
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0xd0, 0xdf);
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}
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void
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@ -272,9 +276,9 @@ mii_access_soft_switches(
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static const int read_modes[4] = { 1, 0, 0, 1, };
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uint8_t rd = read_modes[mode & 3];
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uint8_t wr = write_modes[mode & 3];
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mii->bsr_mode.write = wr;
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mii->bsr_mode.read = rd;
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mii->bsr_mode.page2 = mode & 0x08 ? 0 : 1;
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SW_SETSTATE(mii, BSRWRITE, wr);
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SW_SETSTATE(mii, BSRREAD, rd);
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SW_SETSTATE(mii, BSRPAGE2, !(mode & 0x08));
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mii->mem_dirty = 1;
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if (mii->trace_cpu)
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printf("%04x: BSR mode addr %04x:%02x read:%s write:%s %s altzp:%02x\n",
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@ -282,7 +286,7 @@ mii_access_soft_switches(
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mode,
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rd ? "BSR" : "ROM",
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wr ? "BSR" : "ROM",
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mii->bsr_mode.page2 ? "page2" : "page1",
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SW_GETSTATE(mii, BSRPAGE2) ? "page2" : "page1",
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mii_sw(mii, SWALTPZ));
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} break;
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case 0xcfff:
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@ -293,12 +297,14 @@ mii_access_soft_switches(
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case SWPAGE2OFF:
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case SWPAGE2ON:
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res = true;
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SW_SETSTATE(mii, SWPAGE2, addr & 1);
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mii_bank_poke(main, SWPAGE2, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWHIRESOFF:
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case SWHIRESON:
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res = true;
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SW_SETSTATE(mii, SWHIRES, addr & 1);
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mii_bank_poke(main, SWHIRES, (addr & 1) << 7);
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mii->mem_dirty = 1;
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// printf("HIRES %s\n", (addr & 1) ? "ON" : "OFF");
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@ -319,36 +325,42 @@ mii_access_soft_switches(
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case SW80STOREOFF:
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case SW80STOREON:
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res = true;
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SW_SETSTATE(mii, SW80STORE, addr & 1);
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mii_bank_poke(main, SW80STORE, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWRAMRDOFF:
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case SWRAMRDON:
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res = true;
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SW_SETSTATE(mii, SWRAMRD, addr & 1);
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mii_bank_poke(main, SWRAMRD, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWRAMWRTOFF:
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case SWRAMWRTON:
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res = true;
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SW_SETSTATE(mii, SWRAMWRT, addr & 1);
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mii_bank_poke(main, SWRAMWRT, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWALTPZOFF:
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case SWALTPZON:
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res = true;
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SW_SETSTATE(mii, SWALTPZ, addr & 1);
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mii_bank_poke(main, SWALTPZ, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWINTCXROMOFF:
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case SWINTCXROMON:
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res = true;
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SW_SETSTATE(mii, SWINTCXROM, addr & 1);
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mii_bank_poke(main, SWINTCXROM, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWSLOTC3ROMOFF:
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case SWSLOTC3ROMON:
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res = true;
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SW_SETSTATE(mii, SWSLOTC3ROM, addr & 1);
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mii_bank_poke(main, SWSLOTC3ROM, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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@ -356,11 +368,11 @@ mii_access_soft_switches(
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} else {
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switch (addr) {
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case SWBSRBANK2:
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*byte = mii->bsr_mode.page2 ? 0x80 : 0;
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*byte = SW_GETSTATE(mii, BSRPAGE2) ? 0x80 : 0;
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res = true;
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break;
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case SWBSRREADRAM:
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*byte = mii->bsr_mode.read ? 0x80 : 0;
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*byte = SW_GETSTATE(mii, BSRREAD) ? 0x80 : 0;
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res = true;
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break;
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case SWRAMRD:
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@ -514,10 +526,8 @@ mii_reset(
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{
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// printf("%s cold %d\n", __func__, cold);
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mii->cpu_state.reset = 1;
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mii->bsr_mode.write = 1;
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mii->bsr_mode.read = 0;
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mii->bsr_mode.page2 = 1;
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mii_bank_t * main = &mii->bank[MII_BANK_MAIN];
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mii->sw_state = M_BSRWRITE | M_BSRPAGE2;
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mii_bank_poke(main, SWSLOTC3ROM, 0);
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mii_bank_poke(main, SWRAMRD, 0);
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mii_bank_poke(main, SWRAMWRT, 0);
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@ -92,10 +92,7 @@ typedef struct mii_t {
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uint8_t read : 4, write : 4;
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} mem[256];
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int mem_dirty; // recalculate mem[] on next access
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struct {
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int write, read, page2;
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} bsr_mode;
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uint32_t sw_state; // B_SW* bitfield
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mii_trace_t trace;
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int trace_cpu;
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mii_trap_t trap;
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83
src/mii_sw.h
83
src/mii_sw.h
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@ -3,20 +3,19 @@
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#pragma once
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enum {
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SW80STOREOFF = 0xc000,
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SW80STOREON = 0xc001,
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SWALTCHARSETOFF = 0xc00e,
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SWALTCHARSETON = 0xc00f,
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SW80STORE = 0xc018,
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SWVBL = 0xc019,
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SWALTCHARSET = 0xc01e,
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SW80COL = 0xc01f,
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SWTEXT = 0xc01a,
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SWMIXED = 0xc01b,
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SWPAGE2 = 0xc01c,
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SWHIRES = 0xc01d,
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SWALTCHARSET = 0xc01e,
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SW80STOREOFF = 0xc000,
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SW80STOREON = 0xc001,
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SWALTCHARSETOFF = 0xc00e,
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SWALTCHARSETON = 0xc00f,
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SW80COLOFF = 0xc00c,
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SW80COLON = 0xc00d,
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SWTEXTOFF = 0xc050, // (AKA LORES ON)
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@ -29,8 +28,8 @@ enum {
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SWHIRESON = 0xc057,
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// this one is inverted, the ON is the even address
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SWDHIRESOFF = 0xc05f, // AN3_ON
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SWDHIRESON = 0xc05e, // AN3_OFF
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SWDHIRESOFF = 0xc05f, // AN3_ON
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SWDHIRESON = 0xc05e, // AN3_OFF
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SWAN3 = 0xc05e, // AN3 status
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SWAN3_REGISTER = 0xc05f, // AN3 register for video mode
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SWRDDHIRES = 0xc07f,
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@ -47,13 +46,81 @@ enum {
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SWSLOTC3ROMON = 0xc00b,
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SWBSRBANK2 = 0xc011,
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SWBSRREADRAM = 0xc012,
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SWRAMRD = 0xc013,
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SWRAMWRT = 0xc014,
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SWINTCXROM = 0xc015,
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SWALTPZ = 0xc016,
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SWSLOTC3ROM = 0xc017,
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SWSPEAKER = 0xc030,
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SWKBD = 0xc000,
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SWAKD = 0xc010,
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};
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enum {
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B_SW80STORE = ( 0),
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// B_SWVBL = ( 1),
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B_SWALTCHARSET = ( 2),
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B_SW80COL = ( 3),
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B_SWTEXT = ( 4),
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B_SWMIXED = ( 5),
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B_SWPAGE2 = ( 6),
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B_SWHIRES = ( 7),
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B_SWRAMRD = ( 8),
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B_SWRAMWRT = ( 9),
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B_SWINTCXROM = (10),
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B_SWALTPZ = (11),
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B_SWSLOTC3ROM = (12),
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B_BSRWRITE = (13),
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B_BSRREAD = (14),
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B_BSRPAGE2 = (15),
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B_SWDHIRES = (16),
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M_SW80STORE = (1 << B_SW80STORE),
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// M_SWVBL = (1 << B_SWVBL),
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M_SWALTCHARSET = (1 << B_SWALTCHARSET),
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M_SW80COL = (1 << B_SW80COL),
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M_SWTEXT = (1 << B_SWTEXT),
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M_SWMIXED = (1 << B_SWMIXED),
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M_SWPAGE2 = (1 << B_SWPAGE2),
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M_SWHIRES = (1 << B_SWHIRES),
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M_SWRAMRD = (1 << B_SWRAMRD),
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M_SWRAMWRT = (1 << B_SWRAMWRT),
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M_SWINTCXROM = (1 << B_SWINTCXROM),
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M_SWALTPZ = (1 << B_SWALTPZ),
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M_SWSLOTC3ROM = (1 << B_SWSLOTC3ROM),
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M_BSRWRITE = (1 << B_BSRWRITE),
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M_BSRREAD = (1 << B_BSRREAD),
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M_BSRPAGE2 = (1 << B_BSRPAGE2),
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M_SWDHIRES = (1 << B_SWDHIRES),
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};
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// unused is to prevent the stupid warnings about unused static stuff
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static const char __attribute__((unused)) *mii_sw_names[] = {
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"80STORE",
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"VBL",
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"ALTCHARSET",
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"80COL",
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"TEXT",
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"MIXED",
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"PAGE2",
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"HIRES",
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"RAMRD",
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"RAMWRT",
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"INTCXROM",
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"ALTPZ",
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"SLOTC3ROM",
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"BSRWRITE",
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"BSRREAD",
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"BSRPAGE2",
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"DHIRES",
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NULL,
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} ;
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#define SW_SETSTATE(_mii, _sw, _state) \
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(_mii)->sw_state = ((_mii)->sw_state & ~(M_##_sw)) | \
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(!!(_state) << B_##_sw)
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#define SW_GETSTATE(_mii, _sw) \
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(!!((_mii)->sw_state & M_##_sw))
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@ -146,13 +146,13 @@ mii_video_run(
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mii->video.wait = mii->cycles - mii->video.wait;
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}
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mii_bank_t * main = &mii->bank[MII_BANK_MAIN];
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bool text = !!mii_bank_peek(main, SWTEXT);
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bool page2 = !!mii_bank_peek(main, SWPAGE2);
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bool col80 = !!mii_bank_peek(main, SW80COL);
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bool store80 = !!mii_bank_peek(main, SW80STORE);
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bool mixed = !!mii_bank_peek(main, SWMIXED);
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bool hires = !!mii_bank_peek(main, SWHIRES);
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bool dhires = !!mii_bank_peek(main, SWRDDHIRES);
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bool text = SW_GETSTATE(mii, SWTEXT);
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bool page2 = SW_GETSTATE(mii, SWPAGE2);
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bool col80 = SW_GETSTATE(mii, SW80COL);
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bool store80 = SW_GETSTATE(mii, SW80STORE);
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bool mixed = SW_GETSTATE(mii, SWMIXED);
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bool hires = SW_GETSTATE(mii, SWHIRES);
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bool dhires = SW_GETSTATE(mii, SWDHIRES);
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pt_start(mii->video.state);
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/*
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@ -164,7 +164,6 @@ mii_video_run(
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mii_bank_poke(main, SWVBL, 0x80);
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if (mixed && !text) {
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text = mii->video.line >= 192 - (4 * 8);
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hires = 0;
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}
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// http://www.1000bit.it/support/manuali/apple/technotes/aiie/tn.aiie.03.html
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if (hires && !text && col80 && dhires) {
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@ -362,6 +361,7 @@ mii_access_video(
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case SWALTCHARSETON:
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if (!write) break;
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res = true;
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SW_SETSTATE(mii, SWALTCHARSET, addr & 1);
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mii_bank_poke(main, SWALTCHARSET, (addr & 1) << 7);
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break;
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case SWVBL:
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@ -380,8 +380,8 @@ mii_access_video(
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case SW80COLON:
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if (!write) break;
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res = true;
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SW_SETSTATE(mii, SW80COL, addr & 1);
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mii_bank_poke(main, SW80COL, (addr & 1) << 7);
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// printf("80COL %s\n", on ? "ON" : "OFF");
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break;
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case SWDHIRESOFF: // 0xc05f,
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case SWDHIRESON: { // = 0xc05e,
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@ -392,22 +392,27 @@ mii_access_video(
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if (an3_on && !an3) {
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uint8_t bit = !!mii_bank_peek(main, SW80COL);
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reg = ((reg << 1) | bit) & 3;
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printf("VIDEO 80:%d REG now %x\n", bit, reg);
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// printf("VIDEO 80:%d REG now %x\n", bit, reg);
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mii_bank_poke(main, SWAN3_REGISTER, reg);
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}
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mii_bank_poke(main, SWAN3, an3_on);
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printf("DHRES IS %s mode:%d\n",
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(addr & 1) ? "OFF" : "ON", reg);
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// printf("DHRES IS %s mode:%d\n",
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// (addr & 1) ? "OFF" : "ON", reg);
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mii->sw_state = (mii->sw_state & ~M_SWDHIRES) |
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(!(addr & 1) << B_SWDHIRES);
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SW_SETSTATE(mii, SWDHIRES, !(addr & 1));
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mii_bank_poke(main, SWRDDHIRES, (!(addr & 1)) << 7);
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} break;
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case SWTEXTOFF:
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case SWTEXTON:
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res = true;
|
||||
SW_SETSTATE(mii, SWTEXT, addr & 1);
|
||||
mii_bank_poke(main, SWTEXT, (addr & 1) << 7);
|
||||
break;
|
||||
case SWMIXEDOFF:
|
||||
case SWMIXEDON:
|
||||
res = true;
|
||||
SW_SETSTATE(mii, SWMIXED, addr & 1);
|
||||
mii_bank_poke(main, SWMIXED, (addr & 1) << 7);
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue