mirror of https://github.com/buserror/mii_emu.git
715 lines
16 KiB
C
715 lines
16 KiB
C
/*
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* mii.c
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*
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* Copyright (C) 2023 Michel Pollet <buserror@gmail.com>
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*
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* SPDX-License-Identifier: MIT
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <ctype.h>
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#include "mii_rom_iiee.h"
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#include "mii.h"
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#include "mii_bank.h"
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#include "mii_video.h"
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#include "mii_sw.h"
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#include "mii_65c02.h"
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#include "minipt.h"
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mii_slot_drv_t * mii_slot_drv_list = NULL;
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static const mii_bank_t _mii_banks_init[MII_BANK_COUNT] = {
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[MII_BANK_MAIN] = {
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.name = "MAIN",
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.base = 0x0000,
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.size = 0xd0, // 208 pages, 48KB
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},
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[MII_BANK_BSR] = {
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.name = "BSR",
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.base = 0xd000,
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.size = 64,
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},
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[MII_BANK_BSR_P2] = {
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.name = "BSR P2",
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.base = 0xd000,
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.size = 16,
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},
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[MII_BANK_AUX] = {
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.name = "AUX",
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.base = 0x0000,
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.size = 0xd0, // 208 pages, 48KB
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},
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[MII_BANK_AUX_BSR] = {
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.name = "AUX BSR",
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.base = 0xd000,
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.size = 64,
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},
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[MII_BANK_AUX_BSR_P2] = {
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.name = "AUX BSR P2",
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.base = 0xd000,
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.size = 16,
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},
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[MII_BANK_ROM] = {
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.name = "ROM",
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.base = 0xc000,
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.size = 0x40, // 64 pages, 16KB
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.ro = 1,
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},
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[MII_BANK_CARD_ROM] = {
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.name = "CARD ROM",
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.base = 0xc100,
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.size = 15,
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.ro = 1,
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},
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};
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#include "mii_65c02_ops.h"
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#include "mii_65c02_disasm.h"
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void
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mii_dump_trace_state(
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mii_t *mii)
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{
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mii_cpu_t * cpu = &mii->cpu;
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mii_cpu_state_t s = mii->cpu_state;
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printf("PC:%04X A:%02X X:%02X Y:%02X S:%02x #%d %c AD:%04X D:%02x %c ",
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cpu->PC, cpu->A, cpu->X, cpu->Y, cpu->S, cpu->cycle,
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s.sync ? 'I' : ' ', s.addr, s.data, s.w ? 'W' : 'R');
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// display the S flags
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static const char *s_flags = "CZIDBRVN";
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for (int i = 0; i < 8; i++)
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printf("%c", cpu->P.P[7-i] ? s_flags[7-i] : tolower(s_flags[7-i]));
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if (s.sync) {
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uint8_t op[16];
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for (int i = 0; i < 4; i++) {
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mii_mem_access(mii, mii->cpu.PC + i, op + i, false, false);
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}
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mii_op_t d = mii_cpu_op[op[0]];
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printf(" ");
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char dis[32];
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mii_cpu_disasm_one(op, cpu->PC, dis, sizeof(dis),
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MII_DUMP_DIS_DUMP_HEX);
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printf(": %s", dis);
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if (d.desc.branch) {
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if (cpu->P.P[d.desc.s_bit] == d.desc.s_bit_value)
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printf(" ; taken");
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}
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printf("\n");
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} else
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printf("\n");
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}
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void
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mii_dump_run_trace(
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mii_t *mii)
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{
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// walk all the previous PC values in mii->trace, and display a line
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// of disassebly for all of them
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for (int li = 0; li < MII_PC_LOG_SIZE; li++) {
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int idx = (mii->trace.idx + li) & (MII_PC_LOG_SIZE - 1);
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uint16_t pc = mii->trace.log[idx];
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uint8_t op[16];
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for (int i = 0; i < 4; i++)
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mii_mem_access(mii, pc + i, op + i, false, false);
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// mii_op_t d = mii_cpu_op[op[0]];
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char dis[64];
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mii_cpu_disasm_one(op, pc, dis, sizeof(dis),
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MII_DUMP_DIS_PC | MII_DUMP_DIS_DUMP_HEX);
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printf("%s\n", dis);
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}
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}
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#define _SAME 0xf
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static inline void
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mii_page_set(
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mii_t * mii,
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uint8_t read,
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uint8_t write,
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uint8_t bank,
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uint8_t end )
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{
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for (int i = bank; i <= end; i++) {
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if (read != _SAME)
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mii->mem[i].read = read;
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if (write != _SAME)
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mii->mem[i].write = write;
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}
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}
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static inline uint8_t
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mii_sw(
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mii_t *mii,
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uint16_t sw)
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{
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return mii_bank_peek(&mii->bank[MII_BANK_MAIN], sw);
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}
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static void
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mii_page_table_update(
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mii_t *mii)
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{
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if (!mii->mem_dirty)
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return;
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mii->mem_dirty = 0;
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int altzp = mii_sw(mii, SWALTPZ);
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int page2 = mii_sw(mii, SWPAGE2);
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int store80 = mii_sw(mii, SW80STORE);
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int hires = mii_sw(mii, SWHIRES);
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int ramrd = mii_sw(mii, SWRAMRD);
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int ramwrt = mii_sw(mii, SWRAMWRT);
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int intcxrom = mii_sw(mii, SWINTCXROM);
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int slotc3rom = mii_sw(mii, SWSLOTC3ROM);
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if (mii->trace_cpu)
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printf("%04x: page table update altzp:%02x page2:%02x store80:%02x hires:%02x ramrd:%02x ramwrt:%02x intcxrom:%02x slotc3rom:%02x\n",
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mii->cpu.PC,
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altzp, page2, store80, hires, ramrd, ramwrt, intcxrom, slotc3rom);
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// clean slate
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mii_page_set(mii, MII_BANK_MAIN, MII_BANK_MAIN, 0x00, 0xc0);
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mii_page_set(mii, MII_BANK_ROM, MII_BANK_ROM, 0xc1, 0xff);
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if (altzp)
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mii_page_set(mii, MII_BANK_AUX, MII_BANK_AUX, 0x00, 0x01);
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mii_page_set(mii,
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ramrd ? MII_BANK_AUX : MII_BANK_MAIN,
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ramwrt ? MII_BANK_AUX : MII_BANK_MAIN, 0x02, 0xbf);
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if (store80) {
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mii_page_set(mii,
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page2 ? MII_BANK_AUX : MII_BANK_MAIN,
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page2 ? MII_BANK_AUX : MII_BANK_MAIN, 0x04, 0x07);
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if (hires)
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mii_page_set(mii,
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page2 ? MII_BANK_AUX : MII_BANK_MAIN,
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page2 ? MII_BANK_AUX : MII_BANK_MAIN, 0x20, 0x3f);
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}
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if (!intcxrom)
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mii_page_set(mii, MII_BANK_CARD_ROM, _SAME, 0xc1, 0xc7);
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mii_page_set(mii,
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slotc3rom ? MII_BANK_CARD_ROM : MII_BANK_ROM, _SAME, 0xc3, 0xc3);
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mii_page_set(mii,
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mii->bsr_mode.read ?
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altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR :
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MII_BANK_ROM,
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mii->bsr_mode.write ?
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altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR :
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MII_BANK_ROM,
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0xd0, 0xff);
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// BSR P2
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mii_page_set(mii,
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mii->bsr_mode.read ?
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(altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) +
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mii->bsr_mode.page2 : MII_BANK_ROM,
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mii->bsr_mode.write ?
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(altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) +
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mii->bsr_mode.page2 : MII_BANK_ROM,
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0xd0, 0xdf);
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}
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void
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mii_set_sw_override(
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mii_t *mii,
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uint16_t sw_addr,
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mii_bank_access_cb cb,
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void *param)
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{
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if (!mii->soft_switches_override)
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mii->soft_switches_override = calloc(256,
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sizeof(*mii->soft_switches_override));
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sw_addr &= 0xff;
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mii->soft_switches_override[sw_addr].cb = cb;
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mii->soft_switches_override[sw_addr].param = param;
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}
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static bool
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mii_access_soft_switches(
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mii_t *mii,
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uint16_t addr,
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uint8_t * byte,
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bool write)
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{
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if (!(addr >= 0xc000 && addr <= 0xc0ff) || addr == 0xcfff)
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return false;
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bool res = false;
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uint8_t on = 0;
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mii_bank_t * main = &mii->bank[MII_BANK_MAIN];
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/*
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* This allows driver (titan accelerator etc) to have their own
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* soft switches, and override/supplement any default ones.
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*/
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if (mii->soft_switches_override && mii->soft_switches_override[addr & 0xff].cb) {
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res = mii->soft_switches_override[addr & 0xff].cb(
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main, mii->soft_switches_override[addr & 0xff].param,
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addr, byte, write);
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if (res)
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return res;
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}
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switch (addr) {
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case 0xc090 ... 0xc0ff: {
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res = true;
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int slot = ((addr >> 4) & 7) - 1;
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#if 0
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printf("SLOT %d addr %04x write %d %02x drv %s\n",
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slot, addr, write, *byte,
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mii->slot[slot].drv ? mii->slot[slot].drv->name : "none");
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#endif
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if (mii->slot[slot].drv) {
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on = mii->slot[slot].drv->access(mii,
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&mii->slot[slot], addr, *byte, write);
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if (!write)
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*byte = on;
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}
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} break;
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case 0xc080 ... 0xc08f: {
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res = true;
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uint8_t mode = addr & 0x0f;
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static const int write_modes[4] = { 0, 1, 0, 1, };
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static const int read_modes[4] = { 1, 0, 0, 1, };
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uint8_t rd = read_modes[mode & 3];
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uint8_t wr = write_modes[mode & 3];
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mii->bsr_mode.write = wr;
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mii->bsr_mode.read = rd;
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mii->bsr_mode.page2 = mode & 0x08 ? 0 : 1;
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mii->mem_dirty = 1;
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if (mii->trace_cpu)
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printf("%04x: BSR mode addr %04x:%02x read:%s write:%s %s altzp:%02x\n",
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mii->cpu.PC, addr,
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mode,
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rd ? "BSR" : "ROM",
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wr ? "BSR" : "ROM",
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mii->bsr_mode.page2 ? "page2" : "page1",
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mii_sw(mii, SWALTPZ));
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} break;
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case 0xcfff:
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res = true;
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mii->mem_dirty = 1;
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printf("%s TODO reset SLOT roms\n", __func__);
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break;
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case SWPAGE2OFF:
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case SWPAGE2ON:
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res = true;
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mii_bank_poke(main, SWPAGE2, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWHIRESOFF:
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case SWHIRESON:
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res = true;
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mii_bank_poke(main, SWHIRES, (addr & 1) << 7);
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mii->mem_dirty = 1;
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// printf("HIRES %s\n", (addr & 1) ? "ON" : "OFF");
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break;
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case SWSPEAKER:
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res = true;
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mii_speaker_click(&mii->speaker);
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break;
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case 0xc068:
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res = true;
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// IIgs register, read by prodos tho
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break;
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}
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if (res && !mii->mem_dirty)
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return res;
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if (write) {
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switch (addr) {
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case SW80STOREOFF:
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case SW80STOREON:
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res = true;
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mii_bank_poke(main, SW80STORE, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWRAMRDOFF:
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case SWRAMRDON:
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res = true;
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mii_bank_poke(main, SWRAMRD, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWRAMWRTOFF:
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case SWRAMWRTON:
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res = true;
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mii_bank_poke(main, SWRAMWRT, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWALTPZOFF:
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case SWALTPZON:
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res = true;
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mii_bank_poke(main, SWALTPZ, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWINTCXROMOFF:
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case SWINTCXROMON:
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res = true;
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mii_bank_poke(main, SWINTCXROM, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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case SWSLOTC3ROMOFF:
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case SWSLOTC3ROMON:
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res = true;
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mii_bank_poke(main, SWSLOTC3ROM, (addr & 1) << 7);
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mii->mem_dirty = 1;
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break;
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}
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} else {
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switch (addr) {
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case SWBSRBANK2:
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*byte = mii->bsr_mode.page2 ? 0x80 : 0;
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res = true;
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break;
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case SWBSRREADRAM:
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*byte = mii->bsr_mode.read ? 0x80 : 0;
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res = true;
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break;
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case SWRAMRD:
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case SWRAMWRT:
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case SW80STORE:
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case SWINTCXROM:
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case SWALTPZ:
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case SWSLOTC3ROM:
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res = true;
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*byte = mii_bank_peek(main, addr);
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break;
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case 0xc020: // toggle TAPE output ?!?!
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case 0xc064: // Analog Input 0 (paddle 0)
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case 0xc065: // Analog Input 1 (paddle 1)
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case 0xc079: // Analog Input Reset
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res = true;
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break;
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case 0xc068:
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res = true;
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// IIgs register, read by prodos tho
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break;
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}
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}
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if (!res) {
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// printf("%s addr %04x write %d %02x\n", __func__, addr, write, *byte);
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// mii->state = MII_STOPPED;
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}
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mii_page_table_update(mii);
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return res;
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}
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static bool
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mii_access_keyboard(
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mii_t *mii,
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uint16_t addr,
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uint8_t * byte,
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bool write)
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{
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bool res = false;
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mii_bank_t * main = &mii->bank[MII_BANK_MAIN];
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switch (addr) {
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case SWKBD:
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if (!write) {
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/* If fifo not empty, peek at the next key to process, it already
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* has the 0x80 bit on -- otherwise, return 0 */
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res = true;
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#if 1
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*byte = mii_bank_peek(main, SWKBD);
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#else
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if (mii_key_fifo_isempty(&mii->keys))
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*byte = 0;
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else
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*byte = mii_key_fifo_read_at(&mii->keys, 0).key;
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#endif
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}
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break;
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case SWAKD:
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res = true;
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#if 1
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{
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uint8_t r = mii_bank_peek(main, SWAKD);
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if (!write)
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*byte = r;
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r &= 0x7f;
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mii_bank_poke(main, SWAKD, r);
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mii_bank_poke(main, SWKBD, r);
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}
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#else
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// if (write) {
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/* clear latch, and replace it immediately with the new key
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* if there's one in the FIFO */
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if (!mii_key_fifo_isempty(&mii->keys)) {
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mii_key_t k = mii_key_fifo_read(&mii->keys);
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mii_bank_poke(main, SWAKD, k.key);
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} else
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mii_bank_poke(main, SWAKD,
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mii_bank_peek(main, SWAKD) & ~0x80);
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// } else
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if (!write)
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*byte = mii_bank_peek(main, SWAKD);
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#endif
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break;
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case 0xc061 ... 0xc063: // Push Button 0, 1, 2 (Apple Keys)
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res = true;
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if (!write)
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*byte = mii_bank_peek(main, addr);
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break;
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}
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return res;
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}
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void
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mii_keypress(
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mii_t *mii,
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uint8_t key)
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{
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mii_bank_t * main = &mii->bank[MII_BANK_MAIN];
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key |= 0x80;
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mii_bank_poke(main, SWAKD, key);
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mii_bank_poke(main, SWKBD, key);
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#if 0
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mii_key_t k = {
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.key = key | 0x80,
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};
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if (!mii_key_fifo_isfull(&mii->keys))
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mii_key_fifo_write(&mii->keys, k);
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else {
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printf("%s key fifo full\n", __func__);
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}
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#endif
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}
|
|
|
|
|
|
void
|
|
mii_init(
|
|
mii_t *mii )
|
|
{
|
|
memset(mii, 0, sizeof(*mii));
|
|
mii->speed = 1.0;
|
|
for (int i = 0; i < MII_BANK_COUNT; i++)
|
|
mii->bank[i] = _mii_banks_init[i];
|
|
mii->bank[MII_BANK_ROM].mem = (uint8_t*)&iie_enhanced_rom_bin[0];
|
|
mii->cpu.trap = MII_TRAP;
|
|
mii_reset(mii, true);
|
|
mii_speaker_init(mii, &mii->speaker);
|
|
mii->cpu_state = mii_cpu_init(&mii->cpu);
|
|
for (int i = 0; i < 7; i++)
|
|
mii->slot[i].id = i;
|
|
}
|
|
|
|
void
|
|
mii_prepare(
|
|
mii_t *mii,
|
|
uint32_t flags )
|
|
{
|
|
printf("%s driver table\n", __func__);
|
|
mii_slot_drv_t * drv = mii_slot_drv_list;
|
|
while (drv) {
|
|
printf("%s driver: %s\n", __func__, drv->name);
|
|
if (drv->probe && drv->probe(mii, flags)) {
|
|
printf("%s %s probe done\n", __func__, drv->name);
|
|
}
|
|
drv = drv->next;
|
|
}
|
|
}
|
|
|
|
void
|
|
mii_reset(
|
|
mii_t *mii,
|
|
bool cold)
|
|
{
|
|
// printf("%s cold %d\n", __func__, cold);
|
|
mii->cpu_state.reset = 1;
|
|
mii->bsr_mode.write = 1;
|
|
mii->bsr_mode.read = 0;
|
|
mii->bsr_mode.page2 = 1;
|
|
mii_bank_t * main = &mii->bank[MII_BANK_MAIN];
|
|
mii_bank_poke(main, SWSLOTC3ROM, 0);
|
|
mii_bank_poke(main, SWRAMRD, 0);
|
|
mii_bank_poke(main, SWRAMWRT, 0);
|
|
mii_bank_poke(main, SWALTPZ, 0);
|
|
mii_bank_poke(main, SW80STORE, 0);
|
|
mii_bank_poke(main, SW80COL, 0);
|
|
mii->mem_dirty = 1;
|
|
if (cold) {
|
|
/* these HAS to be reset in that state somehow */
|
|
mii_bank_poke(main, SWINTCXROM, 0);
|
|
uint8_t z[2] = {0x55,0x55};
|
|
mii_bank_write(main, 0x3f2, z, 2);
|
|
}
|
|
mii->mem_dirty = 1;
|
|
mii_page_table_update(mii);
|
|
for (int i = 0; i < 7; i++) {
|
|
if (mii->slot[i].drv && mii->slot[i].drv->reset)
|
|
mii->slot[i].drv->reset(mii, &mii->slot[i]);
|
|
}
|
|
}
|
|
|
|
void
|
|
mii_mem_access(
|
|
mii_t *mii,
|
|
uint16_t addr,
|
|
uint8_t * d,
|
|
bool wr,
|
|
bool do_sw)
|
|
{
|
|
if (!do_sw && addr >= 0xc000 && addr <= 0xc0ff)
|
|
return;
|
|
uint8_t done =
|
|
mii_access_keyboard(mii, addr, d, wr) ||
|
|
mii_access_video(mii, addr, d, wr) ||
|
|
mii_access_soft_switches(mii, addr, d, wr);
|
|
if (!done) {
|
|
uint8_t page = addr >> 8;
|
|
if (wr) {
|
|
uint8_t m = mii->mem[page].write;
|
|
mii_bank_t * b = &mii->bank[m];
|
|
if (b->ro) {
|
|
// printf("%s write to RO bank %s %04x:%02x\n",
|
|
// __func__, b->name, addr, *d);
|
|
} else
|
|
mii_bank_write(b, addr, d, 1);
|
|
} else {
|
|
uint8_t m = mii->mem[page].read;
|
|
mii_bank_t * b = &mii->bank[m];
|
|
*d = mii_bank_peek(b, addr);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
_mii_handle_trap(
|
|
mii_t *mii)
|
|
{
|
|
// printf("%s TRAP hit PC: %04x\n", __func__, mii->cpu.PC);
|
|
mii->cpu_state.sync = 1;
|
|
mii->cpu_state.trap = 0;
|
|
mii->cpu.state = NULL;
|
|
uint8_t trap = mii_read_one(mii, mii->cpu.PC);
|
|
mii->cpu.PC += 1;
|
|
// printf("%s TRAP %02x return PC %04x\n", __func__, trap, mii->cpu.PC);
|
|
if (mii->trap.map & (1 << trap)) {
|
|
if (mii->trap.trap[trap].cb)
|
|
mii->trap.trap[trap].cb(mii, trap);
|
|
} else {
|
|
printf("%s TRAP %02x not handled\n", __func__, trap);
|
|
mii->state = MII_STOPPED;
|
|
}
|
|
// mii->state = MII_STOPPED;
|
|
}
|
|
|
|
uint8_t
|
|
mii_register_trap(
|
|
mii_t *mii,
|
|
mii_trap_handler_cb cb)
|
|
{
|
|
if (mii->trap.map == 0xffff) {
|
|
printf("%s no more traps!!\n", __func__);
|
|
return 0xff;
|
|
}
|
|
for (int i = 0; i < (int)sizeof(mii->trap.map) * 8; i++) {
|
|
if (!(mii->trap.map & (1 << i))) {
|
|
mii->trap.map |= 1 << i;
|
|
mii->trap.trap[i].cb = cb;
|
|
return i;
|
|
}
|
|
}
|
|
return 0xff;
|
|
}
|
|
|
|
void
|
|
mii_run(
|
|
mii_t *mii)
|
|
{
|
|
/* this runs all cycles for one instruction */
|
|
do {
|
|
if (mii->trace_cpu)
|
|
mii_dump_trace_state(mii);
|
|
mii->cpu_state = mii_cpu_run(&mii->cpu, mii->cpu_state);
|
|
mii_video_run(mii);
|
|
mii_speaker_run(&mii->speaker);
|
|
// extract 16-bit address from pin mask
|
|
const uint16_t addr = mii->cpu_state.addr;
|
|
const uint8_t data = mii->cpu_state.data;
|
|
int wr = mii->cpu_state.w;
|
|
uint8_t d = data;
|
|
if (mii->debug.bp_map) {
|
|
for (int i = 0; i < (int)sizeof(mii->debug.bp_map) * 8; i++) {
|
|
if (!(mii->debug.bp_map & (1 << i)))
|
|
continue;
|
|
if (addr >= mii->debug.bp[i].addr &&
|
|
addr < mii->debug.bp[i].addr + mii->debug.bp[i].size) {
|
|
if (((mii->debug.bp[i].kind & MII_BP_R) && !wr) ||
|
|
((mii->debug.bp[i].kind & MII_BP_W) && wr)) {
|
|
|
|
if (1 || !mii->debug.bp[i].silent) {
|
|
printf("BREAKPOINT %d at %04x PC:%04x\n",
|
|
i, addr, mii->cpu.PC);
|
|
mii_dump_run_trace(mii);
|
|
mii_dump_trace_state(mii);
|
|
mii->state = MII_STOPPED;
|
|
}
|
|
}
|
|
if (!(mii->debug.bp[i].kind & MII_BP_STICKY))
|
|
mii->debug.bp_map &= ~(1 << i);
|
|
mii->debug.bp[i].kind |= MII_BP_HIT;
|
|
}
|
|
}
|
|
}
|
|
mii_mem_access(mii, addr, &d, wr, true);
|
|
if (!wr)
|
|
mii->cpu_state.data = d;
|
|
if (mii->cpu_state.trap) {
|
|
_mii_handle_trap(mii);
|
|
}
|
|
} while (!(mii->cpu_state.sync));
|
|
mii->cycles += mii->cpu.cycle;
|
|
// log PC for the running disassembler display
|
|
mii->trace.log[mii->trace.idx] = mii->cpu.PC;
|
|
mii->trace.idx = (mii->trace.idx + 1) & (MII_PC_LOG_SIZE - 1);
|
|
for (int i = 0; i < 7; i++) {
|
|
if (mii->slot[i].drv && mii->slot[i].drv->run)
|
|
mii->slot[i].drv->run(mii, &mii->slot[i]);
|
|
}
|
|
}
|
|
|
|
//! Read one byte from and addres, using the current memory mapping
|
|
uint8_t
|
|
mii_read_one(
|
|
mii_t *mii,
|
|
uint16_t addr)
|
|
{
|
|
uint8_t d = 0;
|
|
mii_mem_access(mii, addr, &d, 0, false);
|
|
return d;
|
|
}
|
|
//! Read a word from addr, using current memory mapping (little endian)
|
|
uint16_t
|
|
mii_read_word(
|
|
mii_t *mii,
|
|
uint16_t addr)
|
|
{
|
|
uint8_t d = 0;
|
|
uint16_t res = 0;
|
|
mii_mem_access(mii, addr, &d, 0, false);
|
|
res = d;
|
|
mii_mem_access(mii, addr + 1, &d, 0, false);
|
|
res |= d << 8;
|
|
return res;
|
|
}
|
|
/* same accessors, for write
|
|
*/
|
|
void
|
|
mii_write_one(
|
|
mii_t *mii,
|
|
uint16_t addr,
|
|
uint8_t d)
|
|
{
|
|
mii_mem_access(mii, addr, &d, 1, false);
|
|
}
|
|
void
|
|
mii_write_word(
|
|
mii_t *mii,
|
|
uint16_t addr,
|
|
uint16_t w)
|
|
{
|
|
uint8_t d = w;
|
|
mii_mem_access(mii, addr, &d, 1, false);
|
|
d = w >> 8;
|
|
mii_mem_access(mii, addr + 1, &d, 1, false);
|
|
}
|