Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2025-02-18 05:30:34 +00:00
Code Issues Projects Releases Wiki Activity

refactor IR returnregs 2

Browse Source
This commit is contained in:
Irmen de Jong 2023-03-13 02:21:58 +01:00
parent 1fdee861e8
commit 03c5dab79d
6 changed files with 409 additions and 394 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt
View File

@ -142,14 +142,14 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
// calculate the assignment value // calculate the assignment value
if (vmDt == IRDataType.FLOAT) { if (vmDt == IRDataType.FLOAT) {
resultFpRegister = codeGen.registers.nextFreeFloat() resultFpRegister = codeGen.registers.nextFreeFloat()
val tr = expressionEval.translateExpression(assignment.value, -1, resultFpRegister) val tr = expressionEval.translateExpression(assignment.value)
addToResult(result, tr, -1, resultFpRegister) addToResult(result, tr, -1, resultFpRegister)
} else { } else {
resultRegister = if (assignment.value is PtMachineRegister) { resultRegister = if (assignment.value is PtMachineRegister) {
(assignment.value as PtMachineRegister).register (assignment.value as PtMachineRegister).register
} else { } else {
val reg = codeGen.registers.nextFree() val reg = codeGen.registers.nextFree()
val tr = expressionEval.translateExpression(assignment.value, reg, -1) val tr = expressionEval.translateExpression(assignment.value)
addToResult(result, tr, reg, -1) addToResult(result, tr, reg, -1)
reg reg
} }
@ -178,7 +178,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
if(array.index.type!=DataType.UBYTE) if(array.index.type!=DataType.UBYTE)
throw AssemblyError("non-array var indexing requires bytes index") throw AssemblyError("non-array var indexing requires bytes index")
val idxReg = codeGen.registers.nextFree() val idxReg = codeGen.registers.nextFree()
val tr = expressionEval.translateExpression(array.index, idxReg, -1) val tr = expressionEval.translateExpression(array.index)
addToResult(result, tr, idxReg, -1) addToResult(result, tr, idxReg, -1)
val code = IRCodeChunk(null, null) val code = IRCodeChunk(null, null)
if(zero) { if(zero) {
@ -235,7 +235,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
result += chunk result += chunk
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
val tr = expressionEval.translateExpression(memory.address, addressReg, -1) val tr = expressionEval.translateExpression(memory.address)
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) } result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) }
} }
@ -245,7 +245,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
result += chunk result += chunk
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
val tr = expressionEval.translateExpression(memory.address, addressReg, -1) val tr = expressionEval.translateExpression(memory.address)
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg) } result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg) }
} }
@ -258,15 +258,16 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
} }
private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): IRCodeChunks { private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): IRCodeChunks {
val result = mutableListOf<IRCodeChunkBase>()
val tr = if(itemsize==1) { val tr = if(itemsize==1) {
expressionEval.translateExpression(array.index, indexReg, -1) expressionEval.translateExpression(array.index)
} else { } else {
val mult = PtBinaryExpression("*", DataType.UBYTE, array.position) val mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
mult.children += array.index mult.children += array.index
mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position) mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
expressionEval.translateExpression(mult, indexReg, -1) expressionEval.translateExpression(mult)
} }
require(tr.resultReg==indexReg && tr.resultFpReg==-1) // TODO weg addToResult(result, tr, indexReg, -1)
return tr.chunks return result
} }
} }

53
codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt
View File

@ -112,9 +112,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
val leftRegister = codeGen.registers.nextFree() val leftRegister = codeGen.registers.nextFree()
val rightRegister = codeGen.registers.nextFree() val rightRegister = codeGen.registers.nextFree()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
var tr = exprGen.translateExpression(call.args[0], leftRegister, -1) var tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, leftRegister, -1) addToResult(result, tr, leftRegister, -1)
tr = exprGen.translateExpression(call.args[1], rightRegister, -1) tr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, rightRegister, -1) addToResult(result, tr, rightRegister, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister) it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister)
@ -135,7 +135,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
else -> throw IllegalArgumentException("weird type") else -> throw IllegalArgumentException("weird type")
} }
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, tr, SyscallRegisterBase, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
@ -159,7 +159,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
else -> throw IllegalArgumentException("weird type") else -> throw IllegalArgumentException("weird type")
} }
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, tr, SyscallRegisterBase, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
@ -174,7 +174,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
val sourceDt = call.args.single().type val sourceDt = call.args.single().type
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
if(sourceDt!=DataType.UWORD) { if(sourceDt!=DataType.UWORD) {
val tr = exprGen.translateExpression(call.args[0], resultRegister, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
when (sourceDt) { when (sourceDt) {
DataType.UBYTE -> { DataType.UBYTE -> {
@ -214,7 +214,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
private fun funcSgn(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { private fun funcSgn(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
val reg = codeGen.registers.nextFree() val reg = codeGen.registers.nextFree()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args.single(), reg, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, reg, -1) addToResult(result, tr, reg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.SGN, codeGen.irType(call.type), reg1 = resultRegister, reg2 = reg) it += IRInstruction(Opcode.SGN, codeGen.irType(call.type), reg1 = resultRegister, reg2 = reg)
@ -225,7 +225,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
private fun funcSqrt16(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { private fun funcSqrt16(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
val reg = codeGen.registers.nextFree() val reg = codeGen.registers.nextFree()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args.single(), reg, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, reg, -1) addToResult(result, tr, reg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.SQRT, IRDataType.WORD, reg1=resultRegister, reg2=reg) it += IRInstruction(Opcode.SQRT, IRDataType.WORD, reg1=resultRegister, reg2=reg)
@ -254,7 +254,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
private fun funcPush(call: PtBuiltinFunctionCall): IRCodeChunks { private fun funcPush(call: PtBuiltinFunctionCall): IRCodeChunks {
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val reg = codeGen.registers.nextFree() val reg = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args.single(), reg, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, reg, -1) addToResult(result, tr, reg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.PUSH, IRDataType.BYTE, reg1=reg) it += IRInstruction(Opcode.PUSH, IRDataType.BYTE, reg1=reg)
@ -265,7 +265,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
private fun funcPushw(call: PtBuiltinFunctionCall): IRCodeChunks { private fun funcPushw(call: PtBuiltinFunctionCall): IRCodeChunks {
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val reg = codeGen.registers.nextFree() val reg = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args.single(), reg, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, reg, -1) addToResult(result, tr, reg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.PUSH, IRDataType.WORD, reg1 = reg) it += IRInstruction(Opcode.PUSH, IRDataType.WORD, reg1 = reg)
@ -284,7 +284,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
else -> throw IllegalArgumentException("weird type to reverse") else -> throw IllegalArgumentException("weird type to reverse")
} }
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, tr, SyscallRegisterBase, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
@ -307,7 +307,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
else -> throw IllegalArgumentException("weird type to sort") else -> throw IllegalArgumentException("weird type to sort")
} }
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, tr, SyscallRegisterBase, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
@ -319,9 +319,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
val msbReg = codeGen.registers.nextFree() val msbReg = codeGen.registers.nextFree()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
var tr = exprGen.translateExpression(call.args[0], msbReg, -1) var tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, msbReg, -1) addToResult(result, tr, msbReg, -1)
tr = exprGen.translateExpression(call.args[1], resultRegister, -1) tr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg) it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg)
@ -339,7 +339,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args[0], addressReg, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREZI, IRDataType.WORD, reg1 = addressReg) it += IRInstruction(Opcode.STOREZI, IRDataType.WORD, reg1 = addressReg)
@ -349,16 +349,16 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
if (call.args[0] is PtNumber) { if (call.args[0] is PtNumber) {
val address = (call.args[0] as PtNumber).number.toInt() val address = (call.args[0] as PtNumber).number.toInt()
val tr = exprGen.translateExpression(call.args[1], valueReg, -1) val tr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, valueReg, -1) addToResult(result, tr, valueReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address) it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address)
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
var tr = exprGen.translateExpression(call.args[0], addressReg, -1) var tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
tr = exprGen.translateExpression(call.args[1], valueReg, -1) tr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, valueReg, -1) addToResult(result, tr, valueReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg) it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg)
@ -378,7 +378,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args[0], addressReg, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREZI, IRDataType.BYTE, reg1 = addressReg) it += IRInstruction(Opcode.STOREZI, IRDataType.BYTE, reg1 = addressReg)
@ -388,16 +388,16 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
if (call.args[0] is PtNumber) { if (call.args[0] is PtNumber) {
val address = (call.args[0] as PtNumber).number.toInt() val address = (call.args[0] as PtNumber).number.toInt()
val tr = exprGen.translateExpression(call.args[1], valueReg, -1) val tr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, valueReg, -1) addToResult(result, tr, valueReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address) it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address)
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
var tr = exprGen.translateExpression(call.args[0], addressReg, -1) var tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
tr = exprGen.translateExpression(call.args[1], valueReg, -1) tr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, valueReg, -1) addToResult(result, tr, valueReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg) it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg)
@ -416,7 +416,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args.single(), addressReg, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADI, IRDataType.WORD, reg1 = resultRegister, reg2 = addressReg) it += IRInstruction(Opcode.LOADI, IRDataType.WORD, reg1 = resultRegister, reg2 = addressReg)
@ -434,7 +434,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressReg = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args.single(), addressReg, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1 = resultRegister, reg2 = addressReg) it += IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1 = resultRegister, reg2 = addressReg)
@ -451,15 +451,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
} }
private fun funcLsb(call: PtBuiltinFunctionCall): ExpressionCodeResult { private fun funcLsb(call: PtBuiltinFunctionCall): ExpressionCodeResult {
val resultRegister = codeGen.registers.nextFree() return exprGen.translateExpression(call.args.single())
return exprGen.translateExpression(call.args.single(), resultRegister, -1)
// note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here. // note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here.
} }
private fun funcMsb(call: PtBuiltinFunctionCall): ExpressionCodeResult { private fun funcMsb(call: PtBuiltinFunctionCall): ExpressionCodeResult {
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val resultRegister = codeGen.registers.nextFree() val resultRegister = codeGen.registers.nextFree()
val tr = exprGen.translateExpression(call.args.single(), resultRegister, -1) val tr = exprGen.translateExpression(call.args.single())
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = resultRegister, reg2 = resultRegister) it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = resultRegister, reg2 = resultRegister)
@ -471,7 +470,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
private fun funcRolRor(opcode: Opcode, call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { private fun funcRolRor(opcode: Opcode, call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
val vmDt = codeGen.irType(call.args[0].type) val vmDt = codeGen.irType(call.args[0].type)
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = exprGen.translateExpression(call.args[0], resultRegister, -1) val tr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(opcode, vmDt, reg1 = resultRegister) it += IRInstruction(opcode, vmDt, reg1 = resultRegister)

636
codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
View File

File diff suppressed because it is too large Load Diff

83
codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt
View File

@ -240,12 +240,11 @@ class IRCodeGen(
is PtNodeGroup -> translateGroup(node.children) is PtNodeGroup -> translateGroup(node.children)
is PtBuiltinFunctionCall -> { is PtBuiltinFunctionCall -> {
val result = translateBuiltinFunc(node) val result = translateBuiltinFunc(node)
result.chunks // it's not an expression so no result value. result.chunks // it's not an expression so no result value.
} }
is PtFunctionCall -> { is PtFunctionCall -> {
val result = expressionEval.translate(node, 0, 0) val result = expressionEval.translate(node)
require(result.resultReg==0 && result.resultFpReg==0) // TODO weg result.chunks // it's not an expression so no result value
result.chunks
} }
is PtNop -> emptyList() is PtNop -> emptyList()
is PtReturn -> translate(node) is PtReturn -> translate(node)
@ -405,7 +404,7 @@ class IRCodeGen(
val valueReg = registers.nextFree() val valueReg = registers.nextFree()
val choiceReg = registers.nextFree() val choiceReg = registers.nextFree()
val valueDt = irType(whenStmt.value.type) val valueDt = irType(whenStmt.value.type)
val tr = expressionEval.translateExpression(whenStmt.value, valueReg, -1) val tr = expressionEval.translateExpression(whenStmt.value)
addToResult(result, tr, valueReg, -1) addToResult(result, tr, valueReg, -1)
val choices = whenStmt.choices.children.map {it as PtWhenChoice } val choices = whenStmt.choices.children.map {it as PtWhenChoice }
val endLabel = createLabelName() val endLabel = createLabelName()
@ -531,9 +530,9 @@ class IRCodeGen(
val loopLabel = createLabelName() val loopLabel = createLabelName()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
var tr = expressionEval.translateExpression(iterable.to, endvalueReg, -1) var tr = expressionEval.translateExpression(iterable.to)
addToResult(result, tr, endvalueReg, -1) addToResult(result, tr, endvalueReg, -1)
tr = expressionEval.translateExpression(iterable.from, indexReg, -1) tr = expressionEval.translateExpression(iterable.from)
addToResult(result, tr, indexReg, -1) addToResult(result, tr, indexReg, -1)
val labelAfterFor = createLabelName() val labelAfterFor = createLabelName()
@ -916,15 +915,13 @@ class IRCodeGen(
private fun translateIfFollowedByJustGoto(ifElse: PtIfElse, goto: PtJump, irDtLeft: IRDataType, signed: Boolean): MutableList<IRCodeChunkBase> { private fun translateIfFollowedByJustGoto(ifElse: PtIfElse, goto: PtJump, irDtLeft: IRDataType, signed: Boolean): MutableList<IRCodeChunkBase> {
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
if(irDtLeft==IRDataType.FLOAT) { if(irDtLeft==IRDataType.FLOAT) {
val leftFpRegNum = registers.nextFreeFloat() val leftTr = expressionEval.translateExpression(ifElse.condition.left)
val rightFpRegNum = registers.nextFreeFloat() addToResult(result, leftTr, -1, leftTr.resultFpReg)
val compResultReg = registers.nextFree() val rightTr = expressionEval.translateExpression(ifElse.condition.right)
var tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpRegNum) addToResult(result, rightTr, -1, rightTr.resultFpReg)
addToResult(result, tr, -1, leftFpRegNum)
tr = expressionEval.translateExpression(ifElse.condition.right, -1, rightFpRegNum)
addToResult(result, tr, -1, rightFpRegNum)
result += IRCodeChunk(null,null).also { result += IRCodeChunk(null,null).also {
it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum) val compResultReg = registers.nextFree()
it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg)
val gotoOpcode = when (ifElse.condition.operator) { val gotoOpcode = when (ifElse.condition.operator) {
"==" -> Opcode.BZ "==" -> Opcode.BZ
"!=" -> Opcode.BNZ "!=" -> Opcode.BNZ
@ -942,47 +939,45 @@ class IRCodeGen(
IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = goto.identifier!!.name) IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = goto.identifier!!.name)
} }
} else { } else {
val leftRegNum = registers.nextFree() val leftTr = expressionEval.translateExpression(ifElse.condition.left)
val rightRegNum = registers.nextFree() addToResult(result, leftTr, leftTr.resultReg, -1)
var tr = expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1) val rightTr = expressionEval.translateExpression(ifElse.condition.right)
addToResult(result, tr, leftRegNum, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
tr = expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1)
addToResult(result, tr, rightRegNum, -1)
val opcode: Opcode val opcode: Opcode
val firstReg: Int val firstReg: Int
val secondReg: Int val secondReg: Int
when (ifElse.condition.operator) { when (ifElse.condition.operator) {
"==" -> { "==" -> {
opcode = Opcode.BEQ opcode = Opcode.BEQ
firstReg = leftRegNum firstReg = leftTr.resultReg
secondReg = rightRegNum secondReg = rightTr.resultReg
} }
"!=" -> { "!=" -> {
opcode = Opcode.BNE opcode = Opcode.BNE
firstReg = leftRegNum firstReg = leftTr.resultReg
secondReg = rightRegNum secondReg = rightTr.resultReg
} }
"<" -> { "<" -> {
// swapped '>' // swapped '>'
opcode = if (signed) Opcode.BGTS else Opcode.BGT opcode = if (signed) Opcode.BGTS else Opcode.BGT
firstReg = rightRegNum firstReg = rightTr.resultReg
secondReg = leftRegNum secondReg = leftTr.resultReg
} }
">" -> { ">" -> {
opcode = if (signed) Opcode.BGTS else Opcode.BGT opcode = if (signed) Opcode.BGTS else Opcode.BGT
firstReg = leftRegNum firstReg = leftTr.resultReg
secondReg = rightRegNum secondReg = rightTr.resultReg
} }
"<=" -> { "<=" -> {
// swapped '>=' // swapped '>='
opcode = if (signed) Opcode.BGES else Opcode.BGE opcode = if (signed) Opcode.BGES else Opcode.BGE
firstReg = rightRegNum firstReg = rightTr.resultReg
secondReg = leftRegNum secondReg = leftTr.resultReg
} }
">=" -> { ">=" -> {
opcode = if (signed) Opcode.BGES else Opcode.BGE opcode = if (signed) Opcode.BGES else Opcode.BGE
firstReg = leftRegNum firstReg = leftTr.resultReg
secondReg = rightRegNum secondReg = rightTr.resultReg
} }
else -> throw AssemblyError("invalid comparison operator") else -> throw AssemblyError("invalid comparison operator")
} }
@ -1006,7 +1001,7 @@ class IRCodeGen(
val leftFpReg = registers.nextFreeFloat() val leftFpReg = registers.nextFreeFloat()
val rightFpReg = registers.nextFreeFloat() val rightFpReg = registers.nextFreeFloat()
compResultReg = registers.nextFree() compResultReg = registers.nextFree()
val tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpReg) val tr = expressionEval.translateExpression(ifElse.condition.left)
addToResult(result, tr, -1, leftFpReg) addToResult(result, tr, -1, leftFpReg)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = rightFpReg, fpValue = 0f) it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = rightFpReg, fpValue = 0f)
@ -1025,7 +1020,7 @@ class IRCodeGen(
// integer comparisons // integer comparisons
branchDt = irDtLeft branchDt = irDtLeft
compResultReg = registers.nextFree() compResultReg = registers.nextFree()
val tr = expressionEval.translateExpression(ifElse.condition.left, compResultReg, -1) val tr = expressionEval.translateExpression(ifElse.condition.left)
addToResult(result, tr, compResultReg, -1) addToResult(result, tr, compResultReg, -1)
elseBranch = when (ifElse.condition.operator) { elseBranch = when (ifElse.condition.operator) {
"==" -> Opcode.BNZ "==" -> Opcode.BNZ
@ -1068,9 +1063,9 @@ class IRCodeGen(
val leftFpRegNum = registers.nextFreeFloat() val leftFpRegNum = registers.nextFreeFloat()
val rightFpRegNum = registers.nextFreeFloat() val rightFpRegNum = registers.nextFreeFloat()
val compResultReg = registers.nextFree() val compResultReg = registers.nextFree()
var tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpRegNum) var tr = expressionEval.translateExpression(ifElse.condition.left)
addToResult(result, tr, -1, leftFpRegNum) addToResult(result, tr, -1, leftFpRegNum)
tr = expressionEval.translateExpression(ifElse.condition.right, -1, rightFpRegNum) tr = expressionEval.translateExpression(ifElse.condition.right)
addToResult(result, tr, -1, rightFpRegNum) addToResult(result, tr, -1, rightFpRegNum)
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null) addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null)
val elseBranch = when (ifElse.condition.operator) { val elseBranch = when (ifElse.condition.operator) {
@ -1103,9 +1098,9 @@ class IRCodeGen(
branchDt = irDtLeft branchDt = irDtLeft
val leftRegNum = registers.nextFree() val leftRegNum = registers.nextFree()
val rightRegNum = registers.nextFree() val rightRegNum = registers.nextFree()
var tr = expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1) var tr = expressionEval.translateExpression(ifElse.condition.left)
addToResult(result, tr, leftRegNum, -1) addToResult(result, tr, leftRegNum, -1)
tr = expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1) tr = expressionEval.translateExpression(ifElse.condition.right)
addToResult(result, tr, rightRegNum, -1) addToResult(result, tr, rightRegNum, -1)
when (ifElse.condition.operator) { when (ifElse.condition.operator) {
"==" -> { "==" -> {
@ -1197,7 +1192,7 @@ class IRCodeGen(
} else { } else {
val incReg = registers.nextFree() val incReg = registers.nextFree()
val addressReg = registers.nextFree() val addressReg = registers.nextFree()
val tr = expressionEval.translateExpression(memory.address, addressReg, -1) val tr = expressionEval.translateExpression(memory.address,)
addToResult(result, tr, addressReg, -1) addToResult(result, tr, addressReg, -1)
val chunk = IRCodeChunk(null, null) val chunk = IRCodeChunk(null, null)
chunk += IRInstruction(Opcode.LOADI, irDt, reg1 = incReg, reg2 = addressReg) chunk += IRInstruction(Opcode.LOADI, irDt, reg1 = incReg, reg2 = addressReg)
@ -1215,7 +1210,7 @@ class IRCodeGen(
} else { } else {
val incReg = registers.nextFree() val incReg = registers.nextFree()
val indexReg = registers.nextFree() val indexReg = registers.nextFree()
val tr = expressionEval.translateExpression(array.index, indexReg, -1) val tr = expressionEval.translateExpression(array.index)
addToResult(result, tr, indexReg, -1) addToResult(result, tr, indexReg, -1)
val chunk = IRCodeChunk(null, null) val chunk = IRCodeChunk(null, null)
chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexReg, labelSymbol=variable) chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexReg, labelSymbol=variable)
@ -1244,7 +1239,7 @@ class IRCodeGen(
val counterReg = registers.nextFree() val counterReg = registers.nextFree()
val irDt = irType(repeat.count.type) val irDt = irType(repeat.count.type)
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val tr = expressionEval.translateExpression(repeat.count, counterReg, -1) val tr = expressionEval.translateExpression(repeat.count)
addToResult(result, tr, counterReg, -1) addToResult(result, tr, counterReg, -1)
addInstr(result, IRInstruction(Opcode.BZ, irDt, reg1=counterReg, labelSymbol = skipRepeatLabel), null) addInstr(result, IRInstruction(Opcode.BZ, irDt, reg1=counterReg, labelSymbol = skipRepeatLabel), null)
result += labelFirstChunk(translateNode(repeat.statements), repeatLabel) result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
@ -1286,13 +1281,13 @@ class IRCodeGen(
} else { } else {
if(value.type==DataType.FLOAT) { if(value.type==DataType.FLOAT) {
val reg = registers.nextFreeFloat() val reg = registers.nextFreeFloat()
val tr = expressionEval.translateExpression(value, -1, reg) val tr = expressionEval.translateExpression(value)
addToResult(result, tr, -1, reg) addToResult(result, tr, -1, reg)
addInstr(result, IRInstruction(Opcode.RETURNREG, IRDataType.FLOAT, fpReg1 = reg), null) addInstr(result, IRInstruction(Opcode.RETURNREG, IRDataType.FLOAT, fpReg1 = reg), null)
} }
else { else {
val reg = registers.nextFree() val reg = registers.nextFree()
val tr = expressionEval.translateExpression(value, reg, -1) val tr = expressionEval.translateExpression(value)
addToResult(result, tr, reg, -1) addToResult(result, tr, reg, -1)
addInstr(result, IRInstruction(Opcode.RETURNREG, irType(value.type) , reg1=reg), null) addInstr(result, IRInstruction(Opcode.RETURNREG, irType(value.type) , reg1=reg), null)
} }

10
compiler/src/prog8/compiler/Compiler.kt
View File

@ -6,9 +6,11 @@ import prog8.ast.Program
import prog8.ast.base.AstException import prog8.ast.base.AstException
import prog8.ast.expressions.Expression import prog8.ast.expressions.Expression
import prog8.ast.expressions.NumericLiteral import prog8.ast.expressions.NumericLiteral
import prog8.ast.printProgram
import prog8.ast.statements.Directive import prog8.ast.statements.Directive
import prog8.code.SymbolTableMaker import prog8.code.SymbolTableMaker
import prog8.code.ast.PtProgram import prog8.code.ast.PtProgram
import prog8.code.ast.printAst
import prog8.code.core.* import prog8.code.core.*
import prog8.code.target.* import prog8.code.target.*
import prog8.codegen.vm.VmCodeGen import prog8.codegen.vm.VmCodeGen
@ -115,10 +117,10 @@ fun compileProgram(args: CompilerArguments): CompilationResult? {
args.errors.report() args.errors.report()
val intermediateAst = IntermediateAstMaker(program, compilationOptions).transform() val intermediateAst = IntermediateAstMaker(program, compilationOptions).transform()
// println("*********** COMPILER AST RIGHT BEFORE ASM GENERATION *************") println("*********** COMPILER AST RIGHT BEFORE ASM GENERATION *************")
// printProgram(program) printProgram(program)
// println("*********** AST RIGHT BEFORE ASM GENERATION *************") println("*********** AST RIGHT BEFORE ASM GENERATION *************")
// printAst(intermediateAst, ::println) printAst(intermediateAst, ::println)
if(!createAssemblyAndAssemble(intermediateAst, args.errors, compilationOptions)) { if(!createAssemblyAndAssemble(intermediateAst, args.errors, compilationOptions)) {
System.err.println("Error in codegeneration or assembler") System.err.println("Error in codegeneration or assembler")

2
docs/source/todo.rst
View File

@ -3,6 +3,8 @@ TODO
For next minor release For next minor release
^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^
- fix IR/VM crashing in bouncegfx and textelite
- reduce the usage of register.nextFree() in IR codegen
- get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes... - get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes...
... ...