Apple-2-SW/prog8
1
0 Fork 0
mirror of https://github.com/irmen/prog8.git synced 2026-10-22 05:02:58 +00:00
Code Issues Projects Releases Wiki Activity

fix some 6502 code gen regressions

Browse Source
This commit is contained in:
Irmen de Jong committed 2026-04-26 00:18:28 +02:00
1 parent 91ff17f666
commit 1c376aa9d1
3 files changed
+137 -14
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

codeGenCpu6502/src/prog8/codegen/cpu6502/IfElseAsmGen.kt
+1 -1
View File
@@ -1110,7 +1110,7 @@ _jump jmp (${target.asmLabel})
}
} else {
// uword <= 0 --> uword == 0
wordEqualsZero(value, true, false, jump, stmt)
wordEqualsZero(value, false, false, jump, stmt)
}
}
compiler/test/codegeneration/TestComparisonIssues.kt
+118
View File
@@ -0,0 +1,118 @@
package prog8tests.codegeneration
import io.kotest.core.spec.style.FunSpec
import io.kotest.engine.spec.tempdir
import prog8.code.target.Cx16Target
import prog8tests.helpers.compileText
import prog8tests.helpers.shouldContainInOrder
import kotlin.io.path.readText
class TestComparisonIssues : FunSpec({
val outputDir = tempdir().toPath()
test("long augmented addition generates loop") {
val text = """
main {
sub start() {
long a = 1000
long b = 2000
a += b
}
}
""".trimIndent()
val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
val asmFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val asm = asmFile.readText()
asm.shouldContainInOrder("ldx", "#252", "lda", "p8v_a+4,x", "adc", "p8v_b+4,x", "sta", "p8v_a+4,x", "inx", "bne")
}
test("long augmented subtraction generates loop") {
val text = """
main {
sub start() {
long a = 2000
long b = 1000
a -= b
}
}
""".trimIndent()
val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
val asmFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val asm = asmFile.readText()
asm.shouldContainInOrder("ldx", "#252", "lda", "p8v_a+4,x", "sbc", "p8v_b+4,x", "sta", "p8v_a+4,x", "inx", "bne")
}
test("word <= 0 signed comparison (identifier)") {
val text = """
main {
sub start() {
word w = -1
if w <= 0 {
cx16.r0 = 1
}
}
}
""".trimIndent()
val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
val asmFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val asm = asmFile.readText()
// lda var+1 | bmi + | ora var | bne falseLabel | +
asm.shouldContainInOrder("lda", "p8v_w+1", "bmi", "+", "ora", "p8v_w", "bne", "p8_label_gen")
}
test("word > 0 signed comparison (identifier)") {
val text = """
main {
sub start() {
word w = 1
if w > 0 {
cx16.r0 = 1
}
}
}
""".trimIndent()
val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
val asmFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val asm = asmFile.readText()
// lda var+1 | bmi falseLabel | ora var | beq falseLabel
asm.shouldContainInOrder("lda", "p8v_w+1", "bmi", "p8_label_gen", "ora", "p8v_w", "beq", "p8_label_gen")
}
test("unsigned word <= 0 becomes == 0") {
val text = """
main {
sub start() {
uword uw = 0
if uw <= 0 {
cx16.r0 = 1
}
}
}
""".trimIndent()
val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
val asmFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val asm = asmFile.readText()
// lda var | ora var+1 | bne falseLabel
asm.shouldContainInOrder("lda", "p8v_uw", "ora", "p8v_uw+1", "bne", "p8_label_gen")
}
test("word <= 0 in if-else (identifier)") {
val text = """
main {
sub start() {
word w = 1
if w <= 0 {
cx16.r0 = 1
} else {
cx16.r0 = 2
}
}
}
""".trimIndent()
val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
val asmFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val asm = asmFile.readText()
// lda msb | bmi + | ora lsb | bne elseLabel | +
asm.shouldContainInOrder("lda", "p8v_w+1", "bmi", "+", "ora", "p8v_w", "bne", "p8_label_gen")
}
})
compiler/test/codegeneration/TestVariousCodeGen.kt
+18 -13
View File
@@ -15,6 +15,7 @@ import prog8.code.core.DataType
import prog8.code.target.*
import prog8tests.helpers.ErrorReporterForTests
import prog8tests.helpers.compileText
import prog8tests.helpers.shouldContainInOrder
import kotlin.io.path.readText
class TestVariousCodeGen: FunSpec({
@@ -679,23 +680,27 @@ main {
val result = compileText(C64Target(), true, text, outputDir, writeAssembly = true)!!
val assemblyFile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm")
val assembly = assemblyFile.readText()
assembly shouldContain "bit cx16.r0L"
assembly shouldContain "bit cx16.r1L"
assembly shouldContain "bit cx16.r2L"
assembly shouldContain "bit cx16.r3L"
assembly shouldContain "bit cx16.r4L"
assembly shouldContain "bit cx16.r5L"
assembly.shouldContainInOrder(
"bit cx16.r0L",
"bit cx16.r1L",
"bit cx16.r2L",
"bit cx16.r3L",
"bit cx16.r4L",
"bit cx16.r5L"
)
val resultIR = compileText(VMTarget(), true, text, outputDir, writeAssembly = true)!!
val irFile = resultIR.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
val ir = irFile.readText()
ir shouldContain "bit.b ${'$'}ff02" // r0
ir shouldContain "bit.b ${'$'}ff04" // r1
ir shouldContain "bit.b ${'$'}ff06" // f2
ir shouldContain "bit.b ${'$'}ff08" // r3
ir shouldContain "bit.b ${'$'}ff0a" // r4
ir shouldContain "bit.b ${'$'}ff0c" // r5
}
ir.shouldContainInOrder(
"bit.b ${'$'}ff02", // r0
"bit.b ${'$'}ff04", // r1
"bit.b ${'$'}ff06", // f2
"bit.b ${'$'}ff08", // r3
"bit.b ${'$'}ff0a", // r4
"bit.b ${'$'}ff0c" // r5
)
}
test("strings in if expression") {
val src="""