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vm: remove BNER opcode -> CMP + BSTNE

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This commit is contained in:
Irmen de Jong 2023-09-23 11:47:24 +02:00
parent 36e8f10d2b
commit 1da0c59182
3 changed files with 5 additions and 16 deletions
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8
codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt
View File

@ -1120,13 +1120,14 @@ class IRCodeGen(
var useCmp = false
when (condition.operator) {
"==" -> {
opcode = Opcode.BSTEQ
useCmp = true
opcode = Opcode.BSTEQ
firstReg = leftTr.resultReg
secondReg = rightTr.resultReg
}
"!=" -> {
opcode = Opcode.BNER
useCmp = true
opcode = Opcode.BSTNE
firstReg = leftTr.resultReg
secondReg = rightTr.resultReg
}
@ -1405,7 +1406,8 @@ class IRCodeGen(
addToResult(result, rightTr, rightTr.resultReg, -1)
when (condition.operator) {
"==" -> {
elseBranch = Opcode.BNER
useCmp = true
elseBranch = Opcode.BSTNE
elseBranchFirstReg = leftTr.resultReg
elseBranchSecondReg = rightTr.resultReg
}

4
intermediate/src/prog8/intermediate/IRInstructions.kt
View File

@ -83,7 +83,6 @@ bstpos address - branch to location if Status bit Negat
bstneg address - branch to location if Status bit Negative is set
bstvc address - branch to location if Status bit Overflow is clear
bstvs address - branch to location if Status bit Overflow is set
bner reg1, reg2, address - jump to location in program given by location, if reg1 != reg2
bgt reg1, value, address - jump to location in program given by location, if reg1 > immediate value (unsigned)
bgts reg1, value, address - jump to location in program given by location, if reg1 > immediate value (signed)
bgtr reg1, reg2, address - jump to location in program given by location, if reg1 > reg2 (unsigned)
@ -258,7 +257,6 @@ enum class Opcode {
BSTPOS,
BSTVC,
BSTVS,
BNER,
BGTR,
BGT,
BLT,
@ -401,7 +399,6 @@ val OpcodesThatBranch = setOf(
Opcode.BSTPOS,
Opcode.BSTVC,
Opcode.BSTVS,
Opcode.BNER,
Opcode.BGTR,
Opcode.BGT,
Opcode.BLT,
@ -549,7 +546,6 @@ val instructionFormats = mutableMapOf(
Opcode.BSTPOS to InstructionFormat.from("N,<a"),
Opcode.BSTVC to InstructionFormat.from("N,<a"),
Opcode.BSTVS to InstructionFormat.from("N,<a"),
Opcode.BNER to InstructionFormat.from("BW,<r1,<r2,<a"),
Opcode.BGTR to InstructionFormat.from("BW,<r1,<r2,<a"),
Opcode.BGT to InstructionFormat.from("BW,<r1,<i,<a"),
Opcode.BLT to InstructionFormat.from("BW,<r1,<i,<a"),

9
virtualmachine/src/prog8/vm/VirtualMachine.kt
View File

@ -191,7 +191,6 @@ class VirtualMachine(irProgram: IRProgram) {
Opcode.BSTNEG -> InsBSTNEG(ins)
Opcode.BSTPOS -> InsBSTPOS(ins)
Opcode.BSTVC, Opcode.BSTVS -> TODO("overflow status flag not yet supported in VM (BSTVC,BSTVS)")
Opcode.BNER -> InsBNER(ins)
Opcode.BGTR -> InsBGTR(ins)
Opcode.BGTSR -> InsBGTSR(ins)
Opcode.BGER -> InsBGER(ins)
@ -668,14 +667,6 @@ class VirtualMachine(irProgram: IRProgram) {
nextPc()
}
private fun InsBNER(i: IRInstruction) {
val (left: Int, right: Int) = getBranchOperands(i)
if(left!=right)
branchTo(i)
else
nextPc()
}
private fun InsBGTR(i: IRInstruction) {
val (left: UInt, right: UInt) = getBranchOperandsU(i)
if(left>right)