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https://github.com/irmen/prog8.git
synced 2026-04-21 17:16:33 +00:00
IR: added signed multiplication opcodes
This commit is contained in:
Irmen de Jong
@@ -134,7 +134,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val chunks = when (augAssign.operator) {
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"+=" -> operatorPlusInplace(symbol, array, constAddress, memTarget, targetDt, value)
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"-=" -> operatorMinusInplace(symbol, array, constAddress, memTarget, targetDt, value)
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"*=" -> operatorMultiplyInplace(symbol, array, constAddress, memTarget, targetDt, value)
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"*=" -> operatorMultiplyInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
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"/=" -> operatorDivideInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
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"|=" -> operatorOrInplace(symbol, array, constAddress, memTarget, targetDt, value)
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"or=" -> operatorLogicalOrInplace(symbol, array, constAddress, memTarget, targetDt, value)
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@@ -231,7 +231,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val tr = expressionEval.translateExpression(array.index)
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addToResult(result, tr, tr.resultReg, -1)
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if(!array.splitWords && eltSize>1)
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result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
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result += codeGen.multiplyByConst(DataType.UBYTE, tr.resultReg, eltSize)
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return tr.resultReg
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}
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@@ -793,7 +793,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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return result
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}
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private fun operatorMultiplyInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks? {
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private fun operatorMultiplyInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
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if(array!=null) {
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val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
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val result = mutableListOf<IRCodeChunkBase>()
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@@ -807,7 +807,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val valueReg=codeGen.registers.next(eltDt)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, eltDt, reg1=valueReg, immediate = constValue)
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it += IRInstruction(Opcode.MULM, eltDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
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val opcode = if(signed) Opcode.MULSM else Opcode.MULM
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it += IRInstruction(opcode, eltDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
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}
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}
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return result
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@@ -827,22 +828,23 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val tr = expressionEval.translateExpression(operand)
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addToResult(result, tr, -1, tr.resultFpReg)
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addInstr(result, if(constAddress!=null)
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IRInstruction(Opcode.MULM, vmDt, fpReg1 = tr.resultFpReg, address = constAddress)
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IRInstruction(Opcode.MULSM, vmDt, fpReg1 = tr.resultFpReg, address = constAddress)
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else
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IRInstruction(Opcode.MULM, vmDt, fpReg1 = tr.resultFpReg, labelSymbol = symbol)
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IRInstruction(Opcode.MULSM, vmDt, fpReg1 = tr.resultFpReg, labelSymbol = symbol)
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, null)
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}
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} else {
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if(constFactorRight!=null && !constFactorRight.type.isFloat) {
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val factor = constFactorRight.number.toInt()
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result += codeGen.multiplyByConstInplace(vmDt, constAddress, symbol, factor)
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result += codeGen.multiplyByConstInplace(vmDt, signed, constAddress, symbol, factor)
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} else {
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val tr = expressionEval.translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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val opcode = if(signed) Opcode.MULSM else Opcode.MULM
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addInstr(result, if(constAddress!=null)
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IRInstruction(Opcode.MULM, vmDt, reg1=tr.resultReg, address = constAddress)
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IRInstruction(opcode, vmDt, reg1=tr.resultReg, address = constAddress)
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else
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IRInstruction(Opcode.MULM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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IRInstruction(opcode, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
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, null)
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}
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}
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@@ -3,6 +3,7 @@ package prog8.codegen.intermediate
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.BaseDataType
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import prog8.code.core.DataType
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import prog8.intermediate.*
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@@ -662,7 +663,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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addToResult(result, indexTr, indexTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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if(eltSize>1)
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it += codeGen.multiplyByConst(IRDataType.BYTE, indexTr.resultReg, eltSize)
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it += codeGen.multiplyByConst(DataType.UBYTE, indexTr.resultReg, eltSize)
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if(msb)
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it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexTr.resultReg)
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it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1=indexTr.resultReg, labelSymbol = target.variable.name)
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@@ -683,7 +684,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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addToResult(result, indexTr, indexTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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if(eltSize>1)
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it += codeGen.multiplyByConst(IRDataType.BYTE, indexTr.resultReg, eltSize)
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it += codeGen.multiplyByConst(DataType.UBYTE, indexTr.resultReg, eltSize)
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if(msb)
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it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexTr.resultReg)
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=indexTr.resultReg, labelSymbol = target.variable.name)
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@@ -2,10 +2,7 @@ package prog8.codegen.intermediate
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import prog8.code.*
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.BaseDataType
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import prog8.code.core.Cx16VirtualRegisters
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import prog8.code.core.Statusflag
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import prog8.code.core.*
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import prog8.intermediate.*
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@@ -392,7 +389,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val tr = translateExpression(arrayIx.index)
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addToResult(result, tr, tr.resultReg, -1)
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if(eltSize>1)
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result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
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result += codeGen.multiplyByConst(DataType.UBYTE, tr.resultReg, eltSize)
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if(vmDt==IRDataType.FLOAT) {
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resultFpRegister = codeGen.registers.next(IRDataType.FLOAT)
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addInstr(result, IRInstruction(Opcode.LOADX, IRDataType.FLOAT, fpReg1 = resultFpRegister, reg1=tr.resultReg, labelSymbol = arrayVarSymbol), null)
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@@ -565,8 +562,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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return when(binExpr.operator) {
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"+" -> operatorPlus(binExpr, vmDt)
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"-" -> operatorMinus(binExpr, vmDt)
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"*" -> operatorMultiply(binExpr, vmDt)
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"/" -> operatorDivide(binExpr, vmDt, signed)
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"*" -> operatorMultiply(binExpr, binExpr.left.type)
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"/" -> operatorDivide(binExpr, binExpr.left.type)
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"%" -> operatorModulo(binExpr, vmDt)
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"|" -> operatorOr(binExpr, vmDt, true)
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"&" -> operatorAnd(binExpr, vmDt, true)
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@@ -1224,7 +1221,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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}
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private fun operatorDivide(binExpr: PtBinaryExpression, vmDt: IRDataType, signed: Boolean): ExpressionCodeResult {
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private fun operatorDivide(binExpr: PtBinaryExpression, dt: DataType): ExpressionCodeResult {
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val vmDt = irType(dt)
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val result = mutableListOf<IRCodeChunkBase>()
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val constFactorRight = binExpr.right as? PtNumber
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if(vmDt==IRDataType.FLOAT) {
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@@ -1239,7 +1237,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, leftTr, -1, leftTr.resultFpReg)
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val rightTr = translateExpression(binExpr.right)
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addToResult(result, rightTr, -1, rightTr.resultFpReg)
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addInstr(result, if(signed)
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addInstr(result, if(dt.isSigned)
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IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2=rightTr.resultFpReg)
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else
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IRInstruction(Opcode.DIVR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2=rightTr.resultFpReg)
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@@ -1251,13 +1249,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val tr = translateExpression(binExpr.left)
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addToResult(result, tr, tr.resultReg, -1)
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val factor = constFactorRight.number.toInt()
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result += codeGen.divideByConst(vmDt, tr.resultReg, factor, signed)
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result += codeGen.divideByConst(vmDt, tr.resultReg, factor, dt.isSigned)
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ExpressionCodeResult(result, vmDt, tr.resultReg, -1)
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} else {
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if(binExpr.right is PtNumber) {
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val leftTr = translateExpression(binExpr.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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addInstr(result, if (signed)
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addInstr(result, if (dt.isSigned)
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IRInstruction(Opcode.DIVS, vmDt, reg1 = leftTr.resultReg, immediate = (binExpr.right as PtNumber).number.toInt())
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else
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IRInstruction(Opcode.DIV, vmDt, reg1 = leftTr.resultReg, immediate = (binExpr.right as PtNumber).number.toInt())
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@@ -1268,7 +1266,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val rightTr = translateExpression(binExpr.right)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, if (signed)
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addInstr(result, if (dt.isSigned)
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IRInstruction(Opcode.DIVSR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg)
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else
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IRInstruction(Opcode.DIVR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg)
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@@ -1279,7 +1277,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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}
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private fun operatorMultiply(binExpr: PtBinaryExpression, vmDt: IRDataType): ExpressionCodeResult {
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private fun operatorMultiply(binExpr: PtBinaryExpression, dt: DataType): ExpressionCodeResult {
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val vmDt = irType(dt)
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val result = mutableListOf<IRCodeChunkBase>()
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val constFactorLeft = binExpr.left as? PtNumber
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val constFactorRight = binExpr.right as? PtNumber
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@@ -1301,7 +1300,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, leftTr, -1, leftTr.resultFpReg)
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val rightTr = translateExpression(binExpr.right)
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addToResult(result, rightTr, -1, rightTr.resultFpReg)
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addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
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addInstr(result, IRInstruction(Opcode.MULSR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
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ExpressionCodeResult(result, vmDt, -1, leftTr.resultFpReg)
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}
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} else {
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@@ -1309,20 +1308,21 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val tr = translateExpression(binExpr.right)
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addToResult(result, tr, tr.resultReg, -1)
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val factor = constFactorLeft.number.toInt()
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result += codeGen.multiplyByConst(vmDt, tr.resultReg, factor)
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result += codeGen.multiplyByConst(dt, tr.resultReg, factor)
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ExpressionCodeResult(result, vmDt, tr.resultReg, -1)
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} else if(constFactorRight!=null && !constFactorRight.type.isFloat) {
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val tr = translateExpression(binExpr.left)
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addToResult(result, tr, tr.resultReg, -1)
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val factor = constFactorRight.number.toInt()
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result += codeGen.multiplyByConst(vmDt, tr.resultReg, factor)
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result += codeGen.multiplyByConst(dt, tr.resultReg, factor)
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ExpressionCodeResult(result, vmDt, tr.resultReg, -1)
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} else {
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val leftTr = translateExpression(binExpr.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val rightTr = translateExpression(binExpr.right)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null)
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val opcode = if(dt.isSigned) Opcode.MULSR else Opcode.MULR
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addInstr(result, IRInstruction(opcode, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null)
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ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1)
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}
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}
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@@ -780,7 +780,7 @@ class IRCodeGen(
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code += if(factor==0.0) {
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IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = fpReg, immediateFp = 0.0)
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} else {
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IRInstruction(Opcode.MUL, IRDataType.FLOAT, fpReg1 = fpReg, immediateFp = factor)
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IRInstruction(Opcode.MULS, IRDataType.FLOAT, fpReg1 = fpReg, immediateFp = factor)
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}
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return code
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}
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@@ -798,38 +798,40 @@ class IRCodeGen(
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val factorReg = registers.next(IRDataType.FLOAT)
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code += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1=factorReg, immediateFp = factor)
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code += if(knownAddress!=null)
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IRInstruction(Opcode.MULM, IRDataType.FLOAT, fpReg1 = factorReg, address = knownAddress)
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IRInstruction(Opcode.MULSM, IRDataType.FLOAT, fpReg1 = factorReg, address = knownAddress)
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else
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IRInstruction(Opcode.MULM, IRDataType.FLOAT, fpReg1 = factorReg, labelSymbol = symbol)
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IRInstruction(Opcode.MULSM, IRDataType.FLOAT, fpReg1 = factorReg, labelSymbol = symbol)
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}
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return code
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}
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internal fun multiplyByConst(dt: IRDataType, reg: Int, factor: Int): IRCodeChunk {
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internal fun multiplyByConst(dt: DataType, reg: Int, factor: Int): IRCodeChunk {
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val irdt = irType(dt)
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val code = IRCodeChunk(null, null)
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if(factor==1)
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return code
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val pow2 = powersOfTwoInt.indexOf(factor)
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if(pow2==1) {
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// just shift 1 bit
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code += IRInstruction(Opcode.LSL, dt, reg1=reg)
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code += IRInstruction(Opcode.LSL, irdt, reg1=reg)
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}
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else if(pow2>=1) {
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// just shift multiple bits
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val pow2reg = registers.next(IRDataType.BYTE)
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code += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=pow2reg, immediate = pow2)
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code += IRInstruction(Opcode.LSLN, dt, reg1=reg, reg2=pow2reg)
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code += IRInstruction(Opcode.LSLN, irdt, reg1=reg, reg2=pow2reg)
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} else {
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code += if (factor == 0) {
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IRInstruction(Opcode.LOAD, dt, reg1=reg, immediate = 0)
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IRInstruction(Opcode.LOAD, irdt, reg1=reg, immediate = 0)
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} else {
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IRInstruction(Opcode.MUL, dt, reg1=reg, immediate = factor)
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val opcode = if(dt.isSigned) Opcode.MULS else Opcode.MUL
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IRInstruction(opcode, irdt, reg1=reg, immediate = factor)
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}
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}
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return code
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}
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internal fun multiplyByConstInplace(dt: IRDataType, knownAddress: Int?, symbol: String?, factor: Int): IRCodeChunk {
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internal fun multiplyByConstInplace(dt: IRDataType, signed: Boolean, knownAddress: Int?, symbol: String?, factor: Int): IRCodeChunk {
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val code = IRCodeChunk(null, null)
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if(factor==1)
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return code
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@@ -859,10 +861,11 @@ class IRCodeGen(
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else {
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val factorReg = registers.next(dt)
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code += IRInstruction(Opcode.LOAD, dt, reg1=factorReg, immediate = factor)
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val opcode = if(signed) Opcode.MULSM else Opcode.MULM
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code += if(knownAddress!=null)
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IRInstruction(Opcode.MULM, dt, reg1=factorReg, address = knownAddress)
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IRInstruction(opcode, dt, reg1=factorReg, address = knownAddress)
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else
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IRInstruction(Opcode.MULM, dt, reg1=factorReg, labelSymbol = symbol)
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IRInstruction(opcode, dt, reg1=factorReg, labelSymbol = symbol)
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}
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}
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return code
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@@ -357,7 +357,7 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
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var changed = false
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indexedInstructions.reversed().forEach { (idx, ins) ->
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when (ins.opcode) {
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Opcode.DIV, Opcode.DIVS, Opcode.MUL, Opcode.MOD -> {
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Opcode.DIV, Opcode.DIVS, Opcode.MUL, Opcode.MULS, Opcode.MOD -> {
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if (ins.immediate == 1) {
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chunk.instructions.removeAt(idx)
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changed = true
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+49
-12
@@ -4,18 +4,55 @@
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main {
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sub start() {
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bool status
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cx16.r0L, status = func()
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if_cs {
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cx16.r0L++
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}
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}
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word w1, w2, w3, w4
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uword uw1, uw2, uw3
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asmsub func() -> ubyte @A, bool @Pv {
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%asm {{
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lda #99
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sec
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rts
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}}
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w1 = -111
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w2 = 222
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w3 = -333
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w4 = -20
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uw1 = 111
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uw2 = 222
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uw3 = 333
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txt.print_w(w2*w3)
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txt.spc()
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w1 = w2 * w3
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txt.print_w(w1)
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txt.nl()
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txt.print_w(w3*w4)
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txt.nl()
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txt.print_uw(uw2*uw3)
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txt.spc()
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uw1 = uw2 * uw3
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txt.print_uw(uw1)
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txt.nl()
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txt.nl()
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w1 = -111
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w2 = 22222
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w3 = -333
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w4 = -17
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uw1 = 111
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uw2 = 22222
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uw3 = 333
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txt.print_w(w2/w3)
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txt.spc()
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w1 = w2 / w3
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txt.print_w(w1)
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txt.nl()
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txt.print_w(w3/w4)
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txt.nl()
|
||||
|
||||
txt.print_uw(uw2/uw3)
|
||||
txt.spc()
|
||||
uw1 = uw2 / uw3
|
||||
txt.print_uw(uw1)
|
||||
txt.nl()
|
||||
}
|
||||
}
|
||||
|
||||
@@ -146,13 +146,16 @@ subr reg1, reg2 - reg1 -= reg2
|
||||
sub reg1, value - reg1 -= value
|
||||
subm reg1, address - memory at address -= reg1
|
||||
mulr reg1, reg2 - unsigned multiply reg1 *= reg2 note: byte*byte->byte, no type extension to word!
|
||||
mulsr reg1, reg2 - signed multiply reg1 *= reg2 note: byte*byte->byte, no type extension to word!
|
||||
mul reg1, value - unsigned multiply reg1 *= value note: byte*byte->byte, no type extension to word!
|
||||
mulm reg1, address - memory at address *= reg2 note: byte*byte->byte, no type extension to word!
|
||||
muls reg1, value - signed multiply reg1 *= value note: byte*byte->byte, no type extension to word!
|
||||
mulm reg1, address - unsigned memory at address *= reg2 note: byte*byte->byte, no type extension to word!
|
||||
mulsm reg1, address - signed memory at address *= reg2 note: byte*byte->byte, no type extension to word!
|
||||
divr reg1, reg2 - unsigned division reg1 /= reg2 note: division by zero yields max int $ff/$ffff
|
||||
div reg1, value - unsigned division reg1 /= value note: division by zero yields max int $ff/$ffff
|
||||
divm reg1, address - memory at address /= reg2 note: division by zero yields max int $ff/$ffff
|
||||
divsr reg1, reg2 - signed division reg1 /= reg2 note: division by zero yields max signed int 127 / 32767
|
||||
div reg1, value - unsigned division reg1 /= value note: division by zero yields max int $ff/$ffff
|
||||
divs reg1, value - signed division reg1 /= value note: division by zero yields max signed int 127 / 32767
|
||||
divm reg1, address - memory at address /= reg2 note: division by zero yields max int $ff/$ffff
|
||||
divsm reg1, address - signed memory at address /= reg2 note: division by zero yields max signed int 127 / 32767
|
||||
modr reg1, reg2 - remainder (modulo) of unsigned division reg1 %= reg2 note: division by zero yields max signed int $ff/$ffff
|
||||
mod reg1, value - remainder (modulo) of unsigned division reg1 %= value note: division by zero yields max signed int $ff/$ffff
|
||||
@@ -327,6 +330,9 @@ enum class Opcode {
|
||||
MULR,
|
||||
MUL,
|
||||
MULM,
|
||||
MULSR,
|
||||
MULS,
|
||||
MULSM,
|
||||
DIVR,
|
||||
DIV,
|
||||
DIVM,
|
||||
@@ -664,9 +670,12 @@ val instructionFormats = mutableMapOf(
|
||||
Opcode.SUBR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.SUB to InstructionFormat.from("BW,<>r1,<i | F,<>fr1,<i"),
|
||||
Opcode.SUBM to InstructionFormat.from("BW,<r1,<>a | F,<fr1,<>a"),
|
||||
Opcode.MULR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.MUL to InstructionFormat.from("BW,<>r1,<i | F,<>fr1,<i"),
|
||||
Opcode.MULM to InstructionFormat.from("BW,<r1,<>a | F,<fr1,<>a"),
|
||||
Opcode.MULR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.MUL to InstructionFormat.from("BW,<>r1,<i"),
|
||||
Opcode.MULM to InstructionFormat.from("BW,<r1,<>a"),
|
||||
Opcode.MULSR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.MULS to InstructionFormat.from("BW,<>r1,<i | F,<>fr1,<i"),
|
||||
Opcode.MULSM to InstructionFormat.from("BW,<r1,<>a | F,<fr1,<>a"),
|
||||
Opcode.DIVR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.DIV to InstructionFormat.from("BW,<>r1,<i"),
|
||||
Opcode.DIVM to InstructionFormat.from("BW,<r1,<>a"),
|
||||
|
||||
@@ -258,6 +258,9 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
Opcode.MULR -> InsMULR(ins)
|
||||
Opcode.MUL -> InsMUL(ins)
|
||||
Opcode.MULM -> InsMULM(ins)
|
||||
Opcode.MULSR -> InsMULSR(ins)
|
||||
Opcode.MULS -> InsMULS(ins)
|
||||
Opcode.MULSM -> InsMULSM(ins)
|
||||
Opcode.DIVR -> InsDIVR(ins)
|
||||
Opcode.DIV -> InsDIV(ins)
|
||||
Opcode.DIVM -> InsDIVM(ins)
|
||||
@@ -1118,6 +1121,48 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsMULSR(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> plusMinusMultAnyByteSigned("*", i.reg1!!, i.reg2!!)
|
||||
IRDataType.WORD -> plusMinusMultAnyWordSigned("*", i.reg1!!, i.reg2!!)
|
||||
IRDataType.FLOAT -> {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val right = registers.getFloat(i.fpReg2!!)
|
||||
val result = arithFloat(left, "*", right)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsMULS(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> plusMinusMultConstByteSigned("*", i.reg1!!, i.immediate!!.toByte())
|
||||
IRDataType.WORD -> plusMinusMultConstWordSigned("*", i.reg1!!, i.immediate!!.toShort())
|
||||
IRDataType.FLOAT -> {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val result = arithFloat(left, "*", i.immediateFp!!)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsMULSM(i: IRInstruction) {
|
||||
val address = i.address!!
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> plusMinusMultAnyByteSignedInplace("*", i.reg1!!, address)
|
||||
IRDataType.WORD -> plusMinusMultAnyWordSignedInplace("*", i.reg1!!, address)
|
||||
IRDataType.FLOAT -> {
|
||||
val left = memory.getFloat(address)
|
||||
val right = registers.getFloat(i.fpReg1!!)
|
||||
val result = arithFloat(left, "*", right)
|
||||
memory.setFloat(address, result)
|
||||
}
|
||||
}
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsDIVR(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> divOrModByteUnsigned("/", i.reg1!!, i.reg2!!)
|
||||
@@ -1355,6 +1400,18 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
registers.setUB(reg1, result.toUByte())
|
||||
}
|
||||
|
||||
private fun plusMinusMultAnyByteSigned(operator: String, reg1: Int, reg2: Int) {
|
||||
val left = registers.getSB(reg1)
|
||||
val right = registers.getSB(reg2)
|
||||
val result = when(operator) {
|
||||
"+" -> left + right
|
||||
"-" -> left - right
|
||||
"*" -> left * right
|
||||
else -> throw IllegalArgumentException("operator byte $operator")
|
||||
}
|
||||
registers.setSB(reg1, result.toByte())
|
||||
}
|
||||
|
||||
private fun plusMinusMultConstByte(operator: String, reg1: Int, value: UByte) {
|
||||
val left = registers.getUB(reg1)
|
||||
val result = when(operator) {
|
||||
@@ -1366,6 +1423,17 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
registers.setUB(reg1, result.toUByte())
|
||||
}
|
||||
|
||||
private fun plusMinusMultConstByteSigned(operator: String, reg1: Int, value: Byte) {
|
||||
val left = registers.getSB(reg1)
|
||||
val result = when(operator) {
|
||||
"+" -> left + value
|
||||
"-" -> left - value
|
||||
"*" -> left * value
|
||||
else -> throw IllegalArgumentException("operator byte $operator")
|
||||
}
|
||||
registers.setSB(reg1, result.toByte())
|
||||
}
|
||||
|
||||
private fun plusMinusMultAnyByteInplace(operator: String, reg1: Int, address: Int) {
|
||||
val memvalue = memory.getUB(address)
|
||||
val operand = registers.getUB(reg1)
|
||||
@@ -1378,6 +1446,18 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
memory.setUB(address, result.toUByte())
|
||||
}
|
||||
|
||||
private fun plusMinusMultAnyByteSignedInplace(operator: String, reg1: Int, address: Int) {
|
||||
val memvalue = memory.getSB(address)
|
||||
val operand = registers.getSB(reg1)
|
||||
val result = when(operator) {
|
||||
"+" -> memvalue + operand
|
||||
"-" -> memvalue - operand
|
||||
"*" -> memvalue * operand
|
||||
else -> throw IllegalArgumentException("operator byte $operator")
|
||||
}
|
||||
memory.setSB(address, result.toByte())
|
||||
}
|
||||
|
||||
private fun divModByteSigned(operator: String, reg1: Int, reg2: Int) {
|
||||
val left = registers.getSB(reg1)
|
||||
val right = registers.getSB(reg2)
|
||||
@@ -1528,6 +1608,22 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
registers.setUW(reg1, result.toUShort())
|
||||
}
|
||||
|
||||
private fun plusMinusMultAnyWordSigned(operator: String, reg1: Int, reg2: Int) {
|
||||
val left = registers.getSW(reg1)
|
||||
val right = registers.getSW(reg2)
|
||||
val result: Int
|
||||
when(operator) {
|
||||
"+" -> result = left + right
|
||||
"-" -> result = left - right
|
||||
"*" -> {
|
||||
result = left.toInt() * right
|
||||
mul16LastUpper = result.toUInt() shr 16
|
||||
}
|
||||
else -> throw IllegalArgumentException("operator word $operator")
|
||||
}
|
||||
registers.setSW(reg1, result.toShort())
|
||||
}
|
||||
|
||||
private fun plusMinusMultConstWord(operator: String, reg1: Int, value: UShort) {
|
||||
val left = registers.getUW(reg1)
|
||||
val result: UInt
|
||||
@@ -1543,6 +1639,21 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
registers.setUW(reg1, result.toUShort())
|
||||
}
|
||||
|
||||
private fun plusMinusMultConstWordSigned(operator: String, reg1: Int, value: Short) {
|
||||
val left = registers.getSW(reg1)
|
||||
val result: Int
|
||||
when(operator) {
|
||||
"+" -> result = left + value
|
||||
"-" -> result = left - value
|
||||
"*" -> {
|
||||
result = left.toInt() * value
|
||||
mul16LastUpper = result.toUInt() shr 16
|
||||
}
|
||||
else -> throw IllegalArgumentException("operator word $operator")
|
||||
}
|
||||
registers.setSW(reg1, result.toShort())
|
||||
}
|
||||
|
||||
private fun plusMinusMultAnyWordInplace(operator: String, reg1: Int, address: Int) {
|
||||
val memvalue = memory.getUW(address)
|
||||
val operand = registers.getUW(reg1)
|
||||
@@ -1559,6 +1670,22 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
memory.setUW(address, result.toUShort())
|
||||
}
|
||||
|
||||
private fun plusMinusMultAnyWordSignedInplace(operator: String, reg1: Int, address: Int) {
|
||||
val memvalue = memory.getSW(address)
|
||||
val operand = registers.getSW(reg1)
|
||||
val result: Int
|
||||
when(operator) {
|
||||
"+" -> result = memvalue + operand
|
||||
"-" -> result = memvalue - operand
|
||||
"*" -> {
|
||||
result = memvalue.toInt() * operand
|
||||
mul16LastUpper = result.toUInt() shr 16
|
||||
}
|
||||
else -> throw IllegalArgumentException("operator word $operator")
|
||||
}
|
||||
memory.setSW(address, result.toShort())
|
||||
}
|
||||
|
||||
private fun divOrModWordUnsigned(operator: String, reg1: Int, reg2: Int) {
|
||||
val left = registers.getUW(reg1)
|
||||
val right = registers.getUW(reg2)
|
||||
|
||||
Reference in New Issue
Block a user