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synced 2026-03-11 05:41:42 +00:00
cx16: add support for VIA timer IRQ in the irq routines
This commit is contained in:
Irmen de Jong
@@ -424,10 +424,13 @@ cx16 {
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&ubyte via1pra = VIA1_BASE + 1
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&ubyte via1ddrb = VIA1_BASE + 2
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&ubyte via1ddra = VIA1_BASE + 3
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&uword via1t1 = VIA1_BASE + 4
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&ubyte via1t1l = VIA1_BASE + 4
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&ubyte via1t1h = VIA1_BASE + 5
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&uword via1t1lw = VIA1_BASE + 6
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&ubyte via1t1ll = VIA1_BASE + 6
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&ubyte via1t1lh = VIA1_BASE + 7
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&uword via1t2 = VIA1_BASE + 8
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&ubyte via1t2l = VIA1_BASE + 8
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&ubyte via1t2h = VIA1_BASE + 9
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&ubyte via1sr = VIA1_BASE + 10
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@@ -437,15 +440,18 @@ cx16 {
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&ubyte via1ier = VIA1_BASE + 14
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&ubyte via1ora = VIA1_BASE + 15
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const uword VIA2_BASE = $9f10 ;VIA 6522 #2
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const uword VIA2_BASE = $9f10 ;VIA 6522 #2, not always present
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&ubyte via2prb = VIA2_BASE + 0
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&ubyte via2pra = VIA2_BASE + 1
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&ubyte via2ddrb = VIA2_BASE + 2
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&ubyte via2ddra = VIA2_BASE + 3
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&uword via2t1 = VIA2_BASE + 4
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&ubyte via2t1l = VIA2_BASE + 4
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&ubyte via2t1h = VIA2_BASE + 5
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&uword via2t1lw = VIA2_BASE + 6
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&ubyte via2t1ll = VIA2_BASE + 6
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&ubyte via2t1lh = VIA2_BASE + 7
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&uword via2t2 = VIA2_BASE + 8
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&ubyte via2t2l = VIA2_BASE + 8
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&ubyte via2t2h = VIA2_BASE + 9
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&ubyte via2sr = VIA2_BASE + 10
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@@ -1322,7 +1328,7 @@ inline asmsub disable_irqs() clobbers(A) {
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asmsub enable_irq_handlers(bool disable_all_irq_sources @Pc) clobbers(A,Y) {
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; Install the "master IRQ handler" that will dispatch IRQs
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; to the registered handler for each type. (Only Vera IRQs supported for now).
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; to the registered handler for each type.
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; The handlers don't need to clear its ISR bit, but have to return 0 or 1 in A,
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; where 1 means: continue with the system IRQ handler, 0 means: don't call that.
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%asm {{
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@@ -1330,7 +1336,11 @@ asmsub enable_irq_handlers(bool disable_all_irq_sources @Pc) clobbers(A,Y) {
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sei
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bcc +
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lda #%00001111
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trb cx16.VERA_IEN ; disable all IRQ sources
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; disable all IRQ sources on VERA and VIA1
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trb cx16.VERA_IEN
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lda #%01111111
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sta cx16.via1ier
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+ lda #<_irq_dispatcher
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ldy #>_irq_dispatcher
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sta cbm.CINV
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@@ -1348,6 +1358,8 @@ asmsub enable_irq_handlers(bool disable_all_irq_sources @Pc) clobbers(A,Y) {
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sty _aflow_vec+1
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sta _sprcol_vec
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sty _sprcol_vec+1
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sta _timer1_vec
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sty _timer1_vec+1
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plp
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rts
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@@ -1357,11 +1369,12 @@ _vsync_vec .word ?
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_line_vec .word ?
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_aflow_vec .word ?
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_sprcol_vec .word ?
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_timer1_vec .word ?
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_continue_with_system_handler .byte ?
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.send BSS
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_irq_dispatcher
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; order of handling: LINE, SPRCOL, AFLOW, VSYNC.
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; order of handling: LINE, TIMER1(VIA1), VSYNC, SPRCOL, AFLOW
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jsr sys.save_prog8_internals
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cld
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lda cx16.VERA_ISR
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@@ -1377,7 +1390,17 @@ _irq_dispatcher
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tsb _continue_with_system_handler
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pla
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+ lsr a
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; timer1 (VIA1) irq?
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+ pha
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lda #%01000000
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and cx16.via1ifr
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beq + ; not timer1 irq
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sta cx16.via1ifr
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jsr _timer1_handler
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tsb _continue_with_system_handler
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+ pla
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lsr a
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bcc +
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pha
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jsr _vsync_handler
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@@ -1422,6 +1445,8 @@ _sprcol_handler
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jmp (_sprcol_vec)
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_aflow_handler
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jmp (_aflow_vec)
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_timer1_handler
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jmp (_timer1_vec)
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}}
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}
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@@ -1486,6 +1511,28 @@ asmsub set_aflow_irq_handler(uword address @AY) clobbers(A) {
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}}
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}
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asmsub set_timer1_irq_handler(uword address @AY) {
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; Sets the VIA1 TIMER1 irq handler to use with enable_irq_handlers(). Does not enable or disable VIA1 timer irqs setting.
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%asm {{
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php
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sei
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sta enable_irq_handlers._timer1_vec
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sty enable_irq_handlers._timer1_vec+1
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plp
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rts
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}}
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}
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sub set_timer1(uword delay, bool keeprunning) {
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; -- set VIA1 timer1 to trigger after the given delay (cycles). Enables VIA timer1 irqs if delay>0, otherwise disables it.
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cx16.via1acr &= %00111111
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if keeprunning
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cx16.via1acr |= %01000000 ; continuous (free-run) mode
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cx16.via1ier = if delay==0 then %01000000 else %11000000
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cx16.via1t1lw = delay
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}
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inline asmsub disable_irq_handlers() {
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; back to the system default IRQ handler.
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@@ -1681,6 +1728,16 @@ asmsub restore_irq() clobbers(A) {
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and #%11110000 ; disable all Vera IRQs but the vsync
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ora #%00000001
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sta cx16.VERA_IEN
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lda #%01111111
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sta cx16.via1ier
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; set timer1 back to free running mode
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lda cx16.via1acr
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and %00111111
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ora %01000000
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sta cx16.via1acr
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lda #$ff
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sta cx16.via1t1ll
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sta cx16.via1t1lh
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plp
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rts
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.section BSS_NOCLEAR
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@@ -276,7 +276,7 @@ Here they are, all available in ``cx16``:
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by setting the various handlers), or pass false to not touch this.
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The handlers don't need to clear its ISR bit, but have to return 0 or 1 in A,
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where 1 means: continue with the system IRQ handler, 0 means: don't call that.
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The order in which the handlers are invoked if multiple interrupts occur simultaneously is: LINE, SPRCOL, AFLOW, VSYNC.
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The order in which the handlers are invoked if multiple interrupts occur simultaneously is: LINE, TIMER1(VIA1), VSYNC, SPRCOL, AFLOW.
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``set_vsync_irq_handler (uword address)``
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Sets the verical sync interrupt handler routine. Also enables VSYNC interrupts.
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@@ -294,5 +294,16 @@ Here they are, all available in ``cx16``:
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Note: the handler must fill the Vera's audio fifo buffer by itself with at least 25% worth of data (1 kb)
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otherwise the aflow irq keeps triggering.
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``set_timer1_irq_handler (uword address)``
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Sets the VIA1 TIMER1 irq handler to use with enable_irq_handlers(). Does not enable or disable VIA1 timer irqs setting.
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``disable_irq_handlers ()``
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Hand control back to the system default IRQ handler.
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And a utility method to set the VIA1 timer1 to trigger IRQs at regular intervals:
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``sub set_timer1 (uword delay, bool keeprunning)``
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Set VIA1 timer1 to trigger after the given delay (cycles).
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Enables VIA timer1 irqs if delay>0, otherwise disables it.
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If keeprunning then the timer keeps triggering, otherwise it stops after a single trigger.
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Note that the speed of the timer depends on the clock speed of the X16 (controlled by a jumper on the motherboard, usually 8 MHz).
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@@ -1,8 +1,6 @@
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TODO
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====
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- cx16: add support for VIA timer IRQ in the irq routines, example code for timer irqs see https://cx16forum.com/forum/viewtopic.php?p=37808
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Weird Heisenbug
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^^^^^^^^^^^^^^^
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- BUG: examples/cube3d-float crashes with div by zero error on C64 (works on cx16. ALready broken in v11, v10 still worked)
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133
examples/test.p8
133
examples/test.p8
@@ -1,129 +1,28 @@
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%import textio
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%zeropage basicsafe
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%option no_sysinit
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; C64: 160, 220, 164
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; C128: 167, 229, 171
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main {
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uword timercounter
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sub start() {
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ubyte char=0
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ubyte x,y
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str name = sc:"irmen"
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long setcc_time, setchr_time, setclr_time
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cx16.enable_irq_handlers(true)
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cx16.set_timer1_irq_handler(&timerhandler)
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cx16.set_timer1(1000*8, true) ; timer irq every 1000 milliseconds (assuming 8mhz clock rate)
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for x in 0 to 4
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txt.setcc(x+20, 19, name[x], x)
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txt.print("9 0 18 1 13 2 5 3 14 4\n")
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for x in 0 to 4 {
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txt.print_ub(txt.getchr(x+20, 19))
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txt.spc()
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txt.print_ub(txt.getclr(x+20, 19) & 15)
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txt.spc()
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}
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sys.wait(200)
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cbm.SETTIML(0)
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setchr()
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setchr_time = cbm.RDTIML()
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sys.wait(60)
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txt.cls()
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char = 0
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cbm.SETTIML(0)
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setcc()
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setcc_time = cbm.RDTIML()
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sys.wait(60)
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cbm.SETTIM(0,0,0)
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setclr()
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setclr_time = cbm.RDTIML()
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sys.wait(60)
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txt.cls()
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txt.print("setchr: ")
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txt.print_l(setchr_time)
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txt.print("\n setcc: ")
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txt.print_l(setcc_time)
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txt.print("\nsetclr: ")
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txt.print_l(setclr_time)
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txt.nl()
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repeat {}
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sub setchr() {
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repeat 30 {
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ubyte left = 0
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ubyte top = 0
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ubyte right = txt.width()-1
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ubyte bottom = txt.height()-1
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while top<bottom {
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for x in left to right
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txt.setchr(x,top,char)
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for y in top to bottom
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txt.setchr(right,y,char)
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for x in right downto left
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txt.setchr(x,bottom,char)
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for y in bottom downto top
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txt.setchr(left,y,char)
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char++
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left++
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top++
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right--
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bottom--
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}
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}
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while timercounter <= 10000 {
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sys.waitvsync()
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txt.home()
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txt.print("via timer counter: ")
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txt.print_uw(timercounter)
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}
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sub setcc() {
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repeat 30 {
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ubyte left = 0
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ubyte top = 0
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ubyte right = txt.width()-1
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ubyte bottom = txt.height()-1
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cx16.disable_irq_handlers()
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}
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while top<bottom {
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for x in left to right
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txt.setcc(x,top,char,5)
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for y in top to bottom
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txt.setcc(right,y,char,3)
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for x in right downto left
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txt.setcc(x,bottom,char,7)
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for y in bottom downto top
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txt.setcc(left,y,char,4)
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char++
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left++
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top++
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right--
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bottom--
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}
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}
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}
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sub setclr() {
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repeat 30 {
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ubyte left = 0
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ubyte top = 0
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ubyte right = txt.width()-1
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ubyte bottom = txt.height()-1
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while top<bottom {
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for x in left to right
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txt.setclr(x,top,char)
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for y in top to bottom
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txt.setclr(right,y,char)
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for x in right downto left
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txt.setclr(x,bottom,char)
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for y in bottom downto top
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txt.setclr(left,y,char)
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char++
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left++
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top++
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right--
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bottom--
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}
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}
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}
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sub timerhandler() -> bool {
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timercounter++
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return false
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}
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}
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