fix IR return type assignment error

codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt

@@ -109,9 +109,11 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
         }
 
         // build an assignment to store the value in the actual target.
+        // Use the return type for the register (matching the LOAD instruction), not the target type.
+        // translateRegularAssign will handle byte-to-word extension if needed.
         val assign = PtAssignment(target.position)
         assign.add(target)
-        assign.add(PtIrRegister(regNum, target.type, target.position))
+        assign.add(PtIrRegister(regNum, returns.type, target.position))
         result += translate(assign)
         return result
     }

examples/test.p8

@@ -4,35 +4,41 @@
 
 main {
     sub start() {
-        uword err1, err2
-        uword val
+        bool bb
+        ubyte ub
+        uword uw
 
-        err1 = eval1("42")
-        cx16.r0++
-        err1, val, err2 = eval(0)
-        if err1 == 0 {
-            val += 1
-        }
+        uw = 9999
+        txt.print_uw(uw)
+        txt.spc()
+        uw, void = thing2()
+        txt.print_uw(uw)
+        txt.nl()
 
-        txt.print(err1)
-        txt.nl()
-        txt.print(err2)
-        txt.nl()
-        txt.print_uw(val)
+        uw = 9999
+        txt.print_uw(uw)
+        txt.spc()
+        uw, bb = thing2()
+        txt.print_uw(uw)
         txt.nl()
+
+;        uw = 9999
+;        txt.print_uw(uw)
+;        txt.spc()
+;        uw, ub = thing2()
+;        txt.print_uw(uw)
+;        txt.nl()
     }
 
-    sub eval1(str expr) -> str {
-        if expr == 0 {
-            return "empty"
-        }
-        return 0
-    }
-
-    sub eval(str expr) -> str, uword, str {
-        if expr == 0 {
-            return "empty", 42, "empty2"
-        }
-        return 0, 42, 0
+    sub thing2() -> ubyte, bool {
+        cx16.r0L=42
+        return cx16.r0L, cx16.r0L==0
     }
+;    asmsub thing2() -> ubyte @A, bool @Pc {
+;        %asm {{
+;            lda  #42
+;            sec
+;            rts
+;        }}
+;    }
 }