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tweak IR
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f8084e7955
commit
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@ -330,7 +330,7 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
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changed = true
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} else if (previous.opcode in OpcodesThatSetStatusbitsButNotCarry) {
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val next = indexedInstructions[idx + 1].value
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if (next.opcode !in arrayOf(Opcode.BSTCC, Opcode.BSTCS, Opcode.BSTPOS, Opcode.BSTNEG)) {
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if (next.opcode !in OpcodesThatDependOnCarry) {
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chunk.instructions.removeAt(idx)
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changed = true
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}
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@ -18,6 +18,7 @@ Status flags: Carry, Zero, Negative. NOTE: status flags are only affected by t
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LOAD instructions DO affect the Z and N flags.
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INC/DEC instructions DO affect the Z and N flags,
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other instructions only affect Z an N flags if the value in a result register is written.
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See OpcodesThatSetStatusbits
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Instruction set is mostly a load/store architecture, there are few instructions operating on memory directly.
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@ -387,14 +388,14 @@ enum class Opcode {
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BREAKPOINT
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}
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val OpcodesThatJump = setOf(
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val OpcodesThatJump = arrayOf(
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Opcode.JUMP,
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Opcode.JUMPI,
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Opcode.RETURN,
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Opcode.RETURNR
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)
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val OpcodesThatBranch = setOf(
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val OpcodesThatBranch = arrayOf(
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Opcode.JUMP,
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Opcode.JUMPI,
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Opcode.RETURN,
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@ -424,11 +425,11 @@ val OpcodesThatBranch = setOf(
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Opcode.BLES
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)
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val OpcodesThatSetStatusbitsIncludingCarry = setOf(
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val OpcodesThatSetStatusbitsIncludingCarry = arrayOf(
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Opcode.CMP,
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Opcode.CMPI
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)
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val OpcodesThatSetStatusbitsButNotCarry = setOf(
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val OpcodesThatSetStatusbitsButNotCarry = arrayOf(
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Opcode.LOAD,
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Opcode.LOADM,
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Opcode.LOADI,
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@ -438,8 +439,29 @@ val OpcodesThatSetStatusbitsButNotCarry = setOf(
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Opcode.INC,
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Opcode.INCM,
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Opcode.DEC,
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Opcode.DECM
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Opcode.DECM,
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Opcode.ANDM,
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Opcode.ANDR,
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Opcode.AND,
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Opcode.ORM,
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Opcode.ORR,
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Opcode.OR,
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Opcode.XORM,
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Opcode.XORR,
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Opcode.XOR
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)
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val OpcodesThatDependOnCarry = arrayOf(
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Opcode.BSTCC,
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Opcode.BSTCS,
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Opcode.BSTPOS,
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Opcode.BSTNEG,
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Opcode.ROXL,
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Opcode.ROXLM,
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Opcode.ROXR,
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Opcode.ROXRM,
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)
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val OpcodesThatSetStatusbits = OpcodesThatSetStatusbitsButNotCarry + OpcodesThatSetStatusbitsIncludingCarry
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