Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2024-11-29 17:50:35 +00:00
Code Issues Projects Releases Wiki Activity

refactor IR returnregs 3

Browse Source
This commit is contained in:
Irmen de Jong 2023-03-13 03:20:06 +01:00
parent 03c5dab79d
commit 54dd3a00df
4 changed files with 179 additions and 176 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt
View File

@ -109,15 +109,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
// TODO let all funcs return ExpressionCodeResult as well // TODO let all funcs return ExpressionCodeResult as well
private fun funcCmp(call: PtBuiltinFunctionCall): IRCodeChunks { private fun funcCmp(call: PtBuiltinFunctionCall): IRCodeChunks {
val leftRegister = codeGen.registers.nextFree()
val rightRegister = codeGen.registers.nextFree()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
var tr = exprGen.translateExpression(call.args[0]) val leftTr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, leftRegister, -1) addToResult(result, leftTr, leftTr.resultReg, -1)
tr = exprGen.translateExpression(call.args[1]) val rightTr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, rightRegister, -1) require(leftTr.resultReg!=rightTr.resultReg)
addToResult(result, rightTr, rightTr.resultReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister) it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftTr.resultReg, reg2=rightTr.resultReg)
} }
return result return result
} }
@ -317,14 +316,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
} }
private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
val msbReg = codeGen.registers.nextFree()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
var tr = exprGen.translateExpression(call.args[0]) val msbTr = exprGen.translateExpression(call.args[0])
addToResult(result, tr, msbReg, -1) addToResult(result, msbTr, msbTr.resultReg, -1)
tr = exprGen.translateExpression(call.args[1]) val lsbTr = exprGen.translateExpression(call.args[1])
addToResult(result, tr, resultRegister, -1) require(lsbTr.resultReg!=msbTr.resultReg)
addToResult(result, lsbTr, resultRegister, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg) it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbTr.resultReg)
} }
return result return result
} }
@ -355,13 +354,13 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address) it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address)
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressTr = exprGen.translateExpression(call.args[0])
var tr = exprGen.translateExpression(call.args[0]) addToResult(result, addressTr, addressTr.resultReg, -1)
addToResult(result, tr, addressReg, -1) val valueTr = exprGen.translateExpression(call.args[1])
tr = exprGen.translateExpression(call.args[1]) require(valueTr.resultReg!=addressTr.resultReg)
addToResult(result, tr, valueReg, -1) addToResult(result, valueTr, valueReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg) it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressTr.resultReg)
} }
} }
} }
@ -394,13 +393,13 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address) it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address)
} }
} else { } else {
val addressReg = codeGen.registers.nextFree() val addressTr = exprGen.translateExpression(call.args[0])
var tr = exprGen.translateExpression(call.args[0]) addToResult(result, addressTr, addressTr.resultReg, -1)
addToResult(result, tr, addressReg, -1) val valueTr = exprGen.translateExpression(call.args[1])
tr = exprGen.translateExpression(call.args[1]) require(valueTr.resultReg!=addressTr.resultReg)
addToResult(result, tr, valueReg, -1) addToResult(result, valueTr, valueReg, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg) it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressTr.resultReg)
} }
} }
} }

235
codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
View File

@ -459,10 +459,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null) addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null)
} else { } else {
if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
var tr = translateExpression(binExpr.left) val leftTr = translateExpression(binExpr.right)
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, leftTr, SyscallRegisterBase, -1)
tr = translateExpression(binExpr.right) val rightTr = translateExpression(binExpr.right)
addToResult(result, tr, SyscallRegisterBase+1, -1) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, rightTr, SyscallRegisterBase+1, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number)
if(resultRegister!=0) if(resultRegister!=0)
@ -474,17 +475,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
IRInstruction(Opcode.SGTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1) IRInstruction(Opcode.SGTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1)
} }
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
val ins = if (signed) { val ins = if (signed) {
if (greaterEquals) Opcode.SGES else Opcode.SGTS if (greaterEquals) Opcode.SGES else Opcode.SGTS
} else { } else {
if (greaterEquals) Opcode.SGE else Opcode.SGT if (greaterEquals) Opcode.SGE else Opcode.SGT
} }
addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
} }
return result return result
@ -515,10 +516,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null) addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null)
} else { } else {
if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
var tr = translateExpression(binExpr.left) val leftTr = translateExpression(binExpr.right)
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, leftTr, SyscallRegisterBase, -1)
tr = translateExpression(binExpr.right) val rightTr = translateExpression(binExpr.right)
addToResult(result, tr, SyscallRegisterBase+1, -1) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, rightTr, SyscallRegisterBase+1, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number)
if(resultRegister!=0) if(resultRegister!=0)
@ -530,17 +532,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
IRInstruction(Opcode.SLTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1) IRInstruction(Opcode.SLTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1)
} }
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
val ins = if (signed) { val ins = if (signed) {
if (lessEquals) Opcode.SLES else Opcode.SLTS if (lessEquals) Opcode.SLES else Opcode.SLTS
} else { } else {
if (lessEquals) Opcode.SLE else Opcode.SLT if (lessEquals) Opcode.SLE else Opcode.SLT
} }
addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
} }
return result return result
@ -567,10 +569,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
} }
} else { } else {
if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
var tr = translateExpression(binExpr.left) val leftTr = translateExpression(binExpr.left)
addToResult(result, tr, SyscallRegisterBase, -1) addToResult(result, leftTr, SyscallRegisterBase, -1)
tr = translateExpression(binExpr.right) val rightTr = translateExpression(binExpr.right)
addToResult(result, tr, SyscallRegisterBase+1, -1) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, rightTr, SyscallRegisterBase+1, -1)
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number)
if(resultRegister!=0) if(resultRegister!=0)
@ -586,13 +589,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val opcode = if (notEquals) Opcode.SNZ else Opcode.SZ val opcode = if (notEquals) Opcode.SNZ else Opcode.SZ
addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = resultRegister), null) addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = resultRegister), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ
addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
} }
} }
@ -607,13 +610,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val opc = if (signed) Opcode.ASR else Opcode.LSR val opc = if (signed) Opcode.ASR else Opcode.LSR
addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister), null) addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
val opc = if (signed) Opcode.ASRN else Opcode.LSRN val opc = if (signed) Opcode.ASRN else Opcode.LSRN
addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
return result return result
} }
@ -647,12 +650,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.LSL, vmDt, reg1=resultRegister), null) addInstr(result, IRInstruction(Opcode.LSL, vmDt, reg1=resultRegister), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightResultReg), null) addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightTr.resultReg), null)
} }
return result return result
} }
@ -684,12 +687,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
return result return result
} }
@ -713,12 +716,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.AND, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) addInstr(result, IRInstruction(Opcode.AND, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.left)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr= translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
return result return result
} }
@ -742,12 +745,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.OR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) addInstr(result, IRInstruction(Opcode.OR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.left)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
return result return result
} }
@ -767,17 +770,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks { private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks {
require(vmDt!=IRDataType.FLOAT) {"floating-point modulo not supported ${binExpr.position}"} require(vmDt!=IRDataType.FLOAT) {"floating-point modulo not supported ${binExpr.position}"}
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
val rightResultReg = codeGen.registers.nextFree()
if(binExpr.right is PtNumber) { if(binExpr.right is PtNumber) {
val tr = translateExpression(binExpr.left) val tr = translateExpression(binExpr.left)
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.MOD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) addInstr(result, IRInstruction(Opcode.MOD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
} else { } else {
var tr = translateExpression(binExpr.left) val leftTr = translateExpression(binExpr.right)
addToResult(result, tr, resultRegister, -1) addToResult(result, leftTr, resultRegister, -1)
tr = translateExpression(binExpr.right) val rightTr = translateExpression(binExpr.right)
addToResult(result, tr, rightResultReg, -1) require(rightTr.resultReg!=leftTr.resultReg)
addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
return result return result
} }
@ -796,15 +799,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val factor = constFactorRight.number.toFloat() val factor = constFactorRight.number.toFloat()
result += codeGen.divideByConstFloat(resultFpRegister, factor) result += codeGen.divideByConstFloat(resultFpRegister, factor)
} else { } else {
val rightResultFpReg = codeGen.registers.nextFreeFloat() val leftTr = translateExpression(binExpr.left)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, resultFpRegister)
addToResult(result, tr, -1, resultFpRegister) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultFpReg!=leftTr.resultFpReg)
addToResult(result, tr, -1, rightResultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg)
addInstr(result, if(signed) addInstr(result, if(signed)
IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightTr.resultFpReg)
else else
IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightTr.resultFpReg)
, null) , null)
} }
} else { } else {
@ -814,7 +817,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val factor = constFactorRight.number.toInt() val factor = constFactorRight.number.toInt()
result += codeGen.divideByConst(vmDt, resultRegister, factor, signed) result += codeGen.divideByConst(vmDt, resultRegister, factor, signed)
} else { } else {
val rightResultReg = codeGen.registers.nextFree()
if(binExpr.right is PtNumber) { if(binExpr.right is PtNumber) {
val tr = translateExpression(binExpr.left) val tr = translateExpression(binExpr.left)
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
@ -824,14 +826,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
IRInstruction(Opcode.DIV, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()) IRInstruction(Opcode.DIV, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt())
, null) , null)
} else { } else {
var tr = translateExpression(binExpr.left) val leftTr = translateExpression(binExpr.left)
addToResult(result, tr, resultRegister, -1) addToResult(result, leftTr, resultRegister, -1)
tr = translateExpression(binExpr.right) val rightTr = translateExpression(binExpr.right)
addToResult(result, tr, rightResultReg, -1) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, if (signed) addInstr(result, if (signed)
IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg)
else else
IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg)
, null) , null)
} }
} }
@ -904,12 +907,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val factor = constFactorRight.number.toFloat() val factor = constFactorRight.number.toFloat()
result += codeGen.multiplyByConstFloat(resultFpRegister, factor) result += codeGen.multiplyByConstFloat(resultFpRegister, factor)
} else { } else {
val rightResultFpReg = codeGen.registers.nextFreeFloat() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, resultFpRegister)
addToResult(result, tr, -1, resultFpRegister) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultFpReg!=leftTr.resultFpReg)
addToResult(result, tr, -1, rightResultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg)
addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null)
} }
} else { } else {
if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) { if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) {
@ -923,12 +926,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val factor = constFactorRight.number.toInt() val factor = constFactorRight.number.toInt()
result += codeGen.multiplyByConst(vmDt, resultRegister, factor) result += codeGen.multiplyByConst(vmDt, resultRegister, factor)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
} }
return result return result
@ -981,12 +984,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, -1, resultFpRegister) addToResult(result, tr, -1, resultFpRegister)
addInstr(result, IRInstruction(Opcode.SUB, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null) addInstr(result, IRInstruction(Opcode.SUB, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null)
} else { } else {
val rightResultFpReg = codeGen.registers.nextFreeFloat() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, resultFpRegister)
addToResult(result, tr, -1, resultFpRegister) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultFpReg!=leftTr.resultFpReg)
addToResult(result, tr, -1, rightResultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg)
addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null)
} }
} }
} else { } else {
@ -1001,12 +1004,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.SUB, vmDt, reg1 = resultRegister, value = (binExpr.right as PtNumber).number.toInt()), null) addInstr(result, IRInstruction(Opcode.SUB, vmDt, reg1 = resultRegister, value = (binExpr.right as PtNumber).number.toInt()), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
} }
} }
@ -1072,12 +1075,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, -1, resultFpRegister) addToResult(result, tr, -1, resultFpRegister)
addInstr(result, IRInstruction(Opcode.ADD, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null) addInstr(result, IRInstruction(Opcode.ADD, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null)
} else { } else {
val rightResultFpReg = codeGen.registers.nextFreeFloat() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, resultFpRegister)
addToResult(result, tr, -1, resultFpRegister) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultFpReg!=leftTr.resultFpReg)
addToResult(result, tr, -1, rightResultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg)
addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null)
} }
} }
} else { } else {
@ -1097,12 +1100,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
addToResult(result, tr, resultRegister, -1) addToResult(result, tr, resultRegister, -1)
addInstr(result, IRInstruction(Opcode.ADD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) addInstr(result, IRInstruction(Opcode.ADD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
} else { } else {
val rightResultReg = codeGen.registers.nextFree() val leftTr = translateExpression(binExpr.right)
var tr = translateExpression(binExpr.left) addToResult(result, leftTr, resultRegister, -1)
addToResult(result, tr, resultRegister, -1) val rightTr = translateExpression(binExpr.right)
tr = translateExpression(binExpr.right) require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, tr, rightResultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
} }
} }
} }

69
codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt
View File

@ -517,8 +517,6 @@ class IRCodeGen(
val step = iterable.step.number.toInt() val step = iterable.step.number.toInt()
if (step==0) if (step==0)
throw AssemblyError("step 0") throw AssemblyError("step 0")
val indexReg = registers.nextFree()
val endvalueReg = registers.nextFree()
require(forLoop.variable.name == loopvar.scopedName) require(forLoop.variable.name == loopvar.scopedName)
val loopvarSymbol = forLoop.variable.name val loopvarSymbol = forLoop.variable.name
val loopvarDt = when(loopvar) { val loopvarDt = when(loopvar) {
@ -530,22 +528,23 @@ class IRCodeGen(
val loopLabel = createLabelName() val loopLabel = createLabelName()
val result = mutableListOf<IRCodeChunkBase>() val result = mutableListOf<IRCodeChunkBase>()
var tr = expressionEval.translateExpression(iterable.to) val toTr = expressionEval.translateExpression(iterable.to)
addToResult(result, tr, endvalueReg, -1) addToResult(result, toTr, toTr.resultReg, -1)
tr = expressionEval.translateExpression(iterable.from) val fromTr = expressionEval.translateExpression(iterable.from)
addToResult(result, tr, indexReg, -1) require(fromTr.resultReg!=toTr.resultReg)
addToResult(result, fromTr, fromTr.resultReg, -1)
val labelAfterFor = createLabelName() val labelAfterFor = createLabelName()
val greaterOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGTS else Opcode.BGT val greaterOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGTS else Opcode.BGT
addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, indexReg, endvalueReg, labelSymbol=labelAfterFor), null) addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, fromTr.resultReg, toTr.resultReg, labelSymbol=labelAfterFor), null)
addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=indexReg, labelSymbol=loopvarSymbol), null) addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=fromTr.resultReg, labelSymbol=loopvarSymbol), null)
result += labelFirstChunk(translateNode(forLoop.statements), loopLabel) result += labelFirstChunk(translateNode(forLoop.statements), loopLabel)
result += addConstMem(loopvarDtIr, null, loopvarSymbol, step) result += addConstMem(loopvarDtIr, null, loopvarSymbol, step)
addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol), null) addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = fromTr.resultReg, labelSymbol = loopvarSymbol), null)
// if endvalue >= index, iterate loop // if endvalue >= index, iterate loop
val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGES else Opcode.BGE val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGES else Opcode.BGE
addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=endvalueReg, reg2=indexReg, labelSymbol=loopLabel), null) addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=toTr.resultReg, reg2=fromTr.resultReg, labelSymbol=loopLabel), null)
result += IRCodeChunk(labelAfterFor, null) result += IRCodeChunk(labelAfterFor, null)
return result return result
@ -918,6 +917,7 @@ class IRCodeGen(
val leftTr = expressionEval.translateExpression(ifElse.condition.left) val leftTr = expressionEval.translateExpression(ifElse.condition.left)
addToResult(result, leftTr, -1, leftTr.resultFpReg) addToResult(result, leftTr, -1, leftTr.resultFpReg)
val rightTr = expressionEval.translateExpression(ifElse.condition.right) val rightTr = expressionEval.translateExpression(ifElse.condition.right)
require(rightTr.resultFpReg!=leftTr.resultFpReg)
addToResult(result, rightTr, -1, rightTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg)
result += IRCodeChunk(null,null).also { result += IRCodeChunk(null,null).also {
val compResultReg = registers.nextFree() val compResultReg = registers.nextFree()
@ -942,6 +942,7 @@ class IRCodeGen(
val leftTr = expressionEval.translateExpression(ifElse.condition.left) val leftTr = expressionEval.translateExpression(ifElse.condition.left)
addToResult(result, leftTr, leftTr.resultReg, -1) addToResult(result, leftTr, leftTr.resultReg, -1)
val rightTr = expressionEval.translateExpression(ifElse.condition.right) val rightTr = expressionEval.translateExpression(ifElse.condition.right)
require(rightTr.resultReg!=leftTr.resultReg)
addToResult(result, rightTr, rightTr.resultReg, -1) addToResult(result, rightTr, rightTr.resultReg, -1)
val opcode: Opcode val opcode: Opcode
val firstReg: Int val firstReg: Int
@ -1060,14 +1061,13 @@ class IRCodeGen(
val elseBranchSecondReg: Int val elseBranchSecondReg: Int
val branchDt: IRDataType val branchDt: IRDataType
if(irDtLeft==IRDataType.FLOAT) { if(irDtLeft==IRDataType.FLOAT) {
val leftFpRegNum = registers.nextFreeFloat() val leftTr = expressionEval.translateExpression(ifElse.condition.left)
val rightFpRegNum = registers.nextFreeFloat() addToResult(result, leftTr, -1, leftTr.resultFpReg)
val rightTr = expressionEval.translateExpression(ifElse.condition.right)
require(rightTr.resultFpReg!=leftTr.resultFpReg)
addToResult(result, rightTr, -1, rightTr.resultFpReg)
val compResultReg = registers.nextFree() val compResultReg = registers.nextFree()
var tr = expressionEval.translateExpression(ifElse.condition.left) addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
addToResult(result, tr, -1, leftFpRegNum)
tr = expressionEval.translateExpression(ifElse.condition.right)
addToResult(result, tr, -1, rightFpRegNum)
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null)
val elseBranch = when (ifElse.condition.operator) { val elseBranch = when (ifElse.condition.operator) {
"==" -> Opcode.BNZ "==" -> Opcode.BNZ
"!=" -> Opcode.BZ "!=" -> Opcode.BZ
@ -1096,46 +1096,45 @@ class IRCodeGen(
} else { } else {
// integer comparisons // integer comparisons
branchDt = irDtLeft branchDt = irDtLeft
val leftRegNum = registers.nextFree() val leftTr = expressionEval.translateExpression(ifElse.condition.left)
val rightRegNum = registers.nextFree() addToResult(result, leftTr, leftTr.resultReg, -1)
var tr = expressionEval.translateExpression(ifElse.condition.left) val rightTr = expressionEval.translateExpression(ifElse.condition.right)
addToResult(result, tr, leftRegNum, -1) require(rightTr.resultReg!=leftTr.resultReg)
tr = expressionEval.translateExpression(ifElse.condition.right) addToResult(result, rightTr, rightTr.resultReg, -1)
addToResult(result, tr, rightRegNum, -1)
when (ifElse.condition.operator) { when (ifElse.condition.operator) {
"==" -> { "==" -> {
elseBranchOpcode = Opcode.BNE elseBranchOpcode = Opcode.BNE
elseBranchFirstReg = leftRegNum elseBranchFirstReg = leftTr.resultReg
elseBranchSecondReg = rightRegNum elseBranchSecondReg = rightTr.resultReg
} }
"!=" -> { "!=" -> {
elseBranchOpcode = Opcode.BEQ elseBranchOpcode = Opcode.BEQ
elseBranchFirstReg = leftRegNum elseBranchFirstReg = leftTr.resultReg
elseBranchSecondReg = rightRegNum elseBranchSecondReg = rightTr.resultReg
} }
"<" -> { "<" -> {
// else part when left >= right // else part when left >= right
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
elseBranchFirstReg = leftRegNum elseBranchFirstReg = leftTr.resultReg
elseBranchSecondReg = rightRegNum elseBranchSecondReg = rightTr.resultReg
} }
">" -> { ">" -> {
// else part when left <= right --> right >= left // else part when left <= right --> right >= left
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
elseBranchFirstReg = rightRegNum elseBranchFirstReg = rightTr.resultReg
elseBranchSecondReg = leftRegNum elseBranchSecondReg = leftTr.resultReg
} }
"<=" -> { "<=" -> {
// else part when left > right // else part when left > right
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
elseBranchFirstReg = leftRegNum elseBranchFirstReg = leftTr.resultReg
elseBranchSecondReg = rightRegNum elseBranchSecondReg = rightTr.resultReg
} }
">=" -> { ">=" -> {
// else part when left < right --> right > left // else part when left < right --> right > left
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
elseBranchFirstReg = rightRegNum elseBranchFirstReg = rightTr.resultReg
elseBranchSecondReg = leftRegNum elseBranchSecondReg = leftTr.resultReg
} }
else -> throw AssemblyError("invalid comparison operator") else -> throw AssemblyError("invalid comparison operator")
} }

2
docs/source/todo.rst
View File

@ -3,9 +3,11 @@ TODO
For next minor release For next minor release
^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^
- fix VM bsieve not printing the last number and string correctly
- fix IR/VM crashing in bouncegfx and textelite - fix IR/VM crashing in bouncegfx and textelite
- reduce the usage of register.nextFree() in IR codegen - reduce the usage of register.nextFree() in IR codegen
- get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes... - get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes...
- get rid of all the require() checks that test result regs to be different
... ...