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https://github.com/irmen/prog8.git
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refactor IR returnregs 3
This commit is contained in:
Irmen de Jong
parent
03c5dab79d
commit
54dd3a00df
@ -109,15 +109,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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// TODO let all funcs return ExpressionCodeResult as well
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private fun funcCmp(call: PtBuiltinFunctionCall): IRCodeChunks {
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val leftRegister = codeGen.registers.nextFree()
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val rightRegister = codeGen.registers.nextFree()
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val result = mutableListOf<IRCodeChunkBase>()
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, leftRegister, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, rightRegister, -1)
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val leftTr = exprGen.translateExpression(call.args[0])
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val rightTr = exprGen.translateExpression(call.args[1])
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require(leftTr.resultReg!=rightTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister)
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it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftTr.resultReg, reg2=rightTr.resultReg)
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}
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return result
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}
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@ -317,14 +316,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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}
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private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
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val msbReg = codeGen.registers.nextFree()
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val result = mutableListOf<IRCodeChunkBase>()
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, msbReg, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, resultRegister, -1)
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val msbTr = exprGen.translateExpression(call.args[0])
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addToResult(result, msbTr, msbTr.resultReg, -1)
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val lsbTr = exprGen.translateExpression(call.args[1])
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require(lsbTr.resultReg!=msbTr.resultReg)
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addToResult(result, lsbTr, resultRegister, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg)
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbTr.resultReg)
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}
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return result
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}
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@ -355,13 +354,13 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address)
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, addressReg, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, valueReg, -1)
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val addressTr = exprGen.translateExpression(call.args[0])
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addToResult(result, addressTr, addressTr.resultReg, -1)
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val valueTr = exprGen.translateExpression(call.args[1])
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require(valueTr.resultReg!=addressTr.resultReg)
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addToResult(result, valueTr, valueReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg)
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it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressTr.resultReg)
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}
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}
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}
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@ -394,13 +393,13 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address)
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, addressReg, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, valueReg, -1)
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val addressTr = exprGen.translateExpression(call.args[0])
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addToResult(result, addressTr, addressTr.resultReg, -1)
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val valueTr = exprGen.translateExpression(call.args[1])
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require(valueTr.resultReg!=addressTr.resultReg)
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addToResult(result, valueTr, valueReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg)
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it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressTr.resultReg)
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}
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}
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}
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@ -459,10 +459,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null)
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} else {
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if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, SyscallRegisterBase, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, SyscallRegisterBase+1, -1)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, SyscallRegisterBase, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, SyscallRegisterBase+1, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number)
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if(resultRegister!=0)
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@ -474,17 +475,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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IRInstruction(Opcode.SGTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1)
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}
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val ins = if (signed) {
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if (greaterEquals) Opcode.SGES else Opcode.SGTS
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} else {
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if (greaterEquals) Opcode.SGE else Opcode.SGT
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}
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addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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}
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return result
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@ -515,10 +516,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null)
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} else {
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if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, SyscallRegisterBase, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, SyscallRegisterBase+1, -1)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, SyscallRegisterBase, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, SyscallRegisterBase+1, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number)
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if(resultRegister!=0)
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@ -530,17 +532,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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IRInstruction(Opcode.SLTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1)
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}
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val ins = if (signed) {
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if (lessEquals) Opcode.SLES else Opcode.SLTS
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} else {
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if (lessEquals) Opcode.SLE else Opcode.SLT
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}
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addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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}
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return result
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@ -567,10 +569,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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} else {
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if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, SyscallRegisterBase, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, SyscallRegisterBase+1, -1)
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val leftTr = translateExpression(binExpr.left)
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addToResult(result, leftTr, SyscallRegisterBase, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, SyscallRegisterBase+1, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number)
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if(resultRegister!=0)
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@ -586,13 +589,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val opcode = if (notEquals) Opcode.SNZ else Opcode.SZ
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addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = resultRegister), null)
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ
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addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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}
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}
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@ -607,13 +610,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val opc = if (signed) Opcode.ASR else Opcode.LSR
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addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister), null)
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val opc = if (signed) Opcode.ASRN else Opcode.LSRN
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addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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return result
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}
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@ -647,12 +650,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, tr, resultRegister, -1)
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addInstr(result, IRInstruction(Opcode.LSL, vmDt, reg1=resultRegister), null)
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightResultReg), null)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightTr.resultReg), null)
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}
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return result
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}
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@ -684,12 +687,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, tr, resultRegister, -1)
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addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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return result
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}
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@ -713,12 +716,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, tr, resultRegister, -1)
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addInstr(result, IRInstruction(Opcode.AND, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr= translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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val leftTr = translateExpression(binExpr.left)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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return result
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}
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@ -742,12 +745,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addToResult(result, tr, resultRegister, -1)
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addInstr(result, IRInstruction(Opcode.OR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
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} else {
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val rightResultReg = codeGen.registers.nextFree()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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val leftTr = translateExpression(binExpr.left)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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return result
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}
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@ -767,17 +770,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks {
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require(vmDt!=IRDataType.FLOAT) {"floating-point modulo not supported ${binExpr.position}"}
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val result = mutableListOf<IRCodeChunkBase>()
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val rightResultReg = codeGen.registers.nextFree()
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if(binExpr.right is PtNumber) {
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val tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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addInstr(result, IRInstruction(Opcode.MOD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
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} else {
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, resultRegister, -1)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, rightResultReg, -1)
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addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
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val leftTr = translateExpression(binExpr.right)
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addToResult(result, leftTr, resultRegister, -1)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultReg!=leftTr.resultReg)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
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}
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return result
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}
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@ -796,15 +799,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val factor = constFactorRight.number.toFloat()
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result += codeGen.divideByConstFloat(resultFpRegister, factor)
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} else {
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val rightResultFpReg = codeGen.registers.nextFreeFloat()
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var tr = translateExpression(binExpr.left)
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addToResult(result, tr, -1, resultFpRegister)
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tr = translateExpression(binExpr.right)
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addToResult(result, tr, -1, rightResultFpReg)
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val leftTr = translateExpression(binExpr.left)
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addToResult(result, leftTr, -1, resultFpRegister)
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val rightTr = translateExpression(binExpr.right)
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require(rightTr.resultFpReg!=leftTr.resultFpReg)
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addToResult(result, rightTr, -1, rightTr.resultFpReg)
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addInstr(result, if(signed)
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IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg)
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IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightTr.resultFpReg)
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else
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IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg)
|
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IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightTr.resultFpReg)
|
||||
, null)
|
||||
}
|
||||
} else {
|
||||
@ -814,7 +817,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
val factor = constFactorRight.number.toInt()
|
||||
result += codeGen.divideByConst(vmDt, resultRegister, factor, signed)
|
||||
} else {
|
||||
val rightResultReg = codeGen.registers.nextFree()
|
||||
if(binExpr.right is PtNumber) {
|
||||
val tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
@ -824,14 +826,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
IRInstruction(Opcode.DIV, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt())
|
||||
, null)
|
||||
} else {
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, rightResultReg, -1)
|
||||
val leftTr = translateExpression(binExpr.left)
|
||||
addToResult(result, leftTr, resultRegister, -1)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultReg!=leftTr.resultReg)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
addInstr(result, if (signed)
|
||||
IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightResultReg)
|
||||
IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg)
|
||||
else
|
||||
IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightResultReg)
|
||||
IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg)
|
||||
, null)
|
||||
}
|
||||
}
|
||||
@ -904,12 +907,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
val factor = constFactorRight.number.toFloat()
|
||||
result += codeGen.multiplyByConstFloat(resultFpRegister, factor)
|
||||
} else {
|
||||
val rightResultFpReg = codeGen.registers.nextFreeFloat()
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, -1, resultFpRegister)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, -1, rightResultFpReg)
|
||||
addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null)
|
||||
val leftTr = translateExpression(binExpr.right)
|
||||
addToResult(result, leftTr, -1, resultFpRegister)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultFpReg!=leftTr.resultFpReg)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null)
|
||||
}
|
||||
} else {
|
||||
if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) {
|
||||
@ -923,12 +926,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
val factor = constFactorRight.number.toInt()
|
||||
result += codeGen.multiplyByConst(vmDt, resultRegister, factor)
|
||||
} else {
|
||||
val rightResultReg = codeGen.registers.nextFree()
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, rightResultReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
|
||||
val leftTr = translateExpression(binExpr.right)
|
||||
addToResult(result, leftTr, resultRegister, -1)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultReg!=leftTr.resultReg)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
|
||||
}
|
||||
}
|
||||
return result
|
||||
@ -981,12 +984,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
addToResult(result, tr, -1, resultFpRegister)
|
||||
addInstr(result, IRInstruction(Opcode.SUB, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null)
|
||||
} else {
|
||||
val rightResultFpReg = codeGen.registers.nextFreeFloat()
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, -1, resultFpRegister)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, -1, rightResultFpReg)
|
||||
addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null)
|
||||
val leftTr = translateExpression(binExpr.right)
|
||||
addToResult(result, leftTr, -1, resultFpRegister)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultFpReg!=leftTr.resultFpReg)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null)
|
||||
}
|
||||
}
|
||||
} else {
|
||||
@ -1001,12 +1004,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
addInstr(result, IRInstruction(Opcode.SUB, vmDt, reg1 = resultRegister, value = (binExpr.right as PtNumber).number.toInt()), null)
|
||||
} else {
|
||||
val rightResultReg = codeGen.registers.nextFree()
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, rightResultReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
|
||||
val leftTr = translateExpression(binExpr.right)
|
||||
addToResult(result, leftTr, resultRegister, -1)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultReg!=leftTr.resultReg)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1072,12 +1075,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
addToResult(result, tr, -1, resultFpRegister)
|
||||
addInstr(result, IRInstruction(Opcode.ADD, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null)
|
||||
} else {
|
||||
val rightResultFpReg = codeGen.registers.nextFreeFloat()
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, -1, resultFpRegister)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, -1, rightResultFpReg)
|
||||
addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null)
|
||||
val leftTr = translateExpression(binExpr.right)
|
||||
addToResult(result, leftTr, -1, resultFpRegister)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultFpReg!=leftTr.resultFpReg)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null)
|
||||
}
|
||||
}
|
||||
} else {
|
||||
@ -1097,12 +1100,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
addInstr(result, IRInstruction(Opcode.ADD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null)
|
||||
} else {
|
||||
val rightResultReg = codeGen.registers.nextFree()
|
||||
var tr = translateExpression(binExpr.left)
|
||||
addToResult(result, tr, resultRegister, -1)
|
||||
tr = translateExpression(binExpr.right)
|
||||
addToResult(result, tr, rightResultReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null)
|
||||
val leftTr = translateExpression(binExpr.right)
|
||||
addToResult(result, leftTr, resultRegister, -1)
|
||||
val rightTr = translateExpression(binExpr.right)
|
||||
require(rightTr.resultReg!=leftTr.resultReg)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -517,8 +517,6 @@ class IRCodeGen(
|
||||
val step = iterable.step.number.toInt()
|
||||
if (step==0)
|
||||
throw AssemblyError("step 0")
|
||||
val indexReg = registers.nextFree()
|
||||
val endvalueReg = registers.nextFree()
|
||||
require(forLoop.variable.name == loopvar.scopedName)
|
||||
val loopvarSymbol = forLoop.variable.name
|
||||
val loopvarDt = when(loopvar) {
|
||||
@ -530,22 +528,23 @@ class IRCodeGen(
|
||||
val loopLabel = createLabelName()
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
|
||||
var tr = expressionEval.translateExpression(iterable.to)
|
||||
addToResult(result, tr, endvalueReg, -1)
|
||||
tr = expressionEval.translateExpression(iterable.from)
|
||||
addToResult(result, tr, indexReg, -1)
|
||||
val toTr = expressionEval.translateExpression(iterable.to)
|
||||
addToResult(result, toTr, toTr.resultReg, -1)
|
||||
val fromTr = expressionEval.translateExpression(iterable.from)
|
||||
require(fromTr.resultReg!=toTr.resultReg)
|
||||
addToResult(result, fromTr, fromTr.resultReg, -1)
|
||||
|
||||
val labelAfterFor = createLabelName()
|
||||
val greaterOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGTS else Opcode.BGT
|
||||
addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, indexReg, endvalueReg, labelSymbol=labelAfterFor), null)
|
||||
addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, fromTr.resultReg, toTr.resultReg, labelSymbol=labelAfterFor), null)
|
||||
|
||||
addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=indexReg, labelSymbol=loopvarSymbol), null)
|
||||
addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=fromTr.resultReg, labelSymbol=loopvarSymbol), null)
|
||||
result += labelFirstChunk(translateNode(forLoop.statements), loopLabel)
|
||||
result += addConstMem(loopvarDtIr, null, loopvarSymbol, step)
|
||||
addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol), null)
|
||||
addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = fromTr.resultReg, labelSymbol = loopvarSymbol), null)
|
||||
// if endvalue >= index, iterate loop
|
||||
val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGES else Opcode.BGE
|
||||
addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=endvalueReg, reg2=indexReg, labelSymbol=loopLabel), null)
|
||||
addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=toTr.resultReg, reg2=fromTr.resultReg, labelSymbol=loopLabel), null)
|
||||
|
||||
result += IRCodeChunk(labelAfterFor, null)
|
||||
return result
|
||||
@ -918,6 +917,7 @@ class IRCodeGen(
|
||||
val leftTr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, leftTr, -1, leftTr.resultFpReg)
|
||||
val rightTr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
require(rightTr.resultFpReg!=leftTr.resultFpReg)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
result += IRCodeChunk(null,null).also {
|
||||
val compResultReg = registers.nextFree()
|
||||
@ -942,6 +942,7 @@ class IRCodeGen(
|
||||
val leftTr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
require(rightTr.resultReg!=leftTr.resultReg)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
val opcode: Opcode
|
||||
val firstReg: Int
|
||||
@ -1060,14 +1061,13 @@ class IRCodeGen(
|
||||
val elseBranchSecondReg: Int
|
||||
val branchDt: IRDataType
|
||||
if(irDtLeft==IRDataType.FLOAT) {
|
||||
val leftFpRegNum = registers.nextFreeFloat()
|
||||
val rightFpRegNum = registers.nextFreeFloat()
|
||||
val leftTr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, leftTr, -1, leftTr.resultFpReg)
|
||||
val rightTr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
require(rightTr.resultFpReg!=leftTr.resultFpReg)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
val compResultReg = registers.nextFree()
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, tr, -1, leftFpRegNum)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
addToResult(result, tr, -1, rightFpRegNum)
|
||||
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null)
|
||||
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
|
||||
val elseBranch = when (ifElse.condition.operator) {
|
||||
"==" -> Opcode.BNZ
|
||||
"!=" -> Opcode.BZ
|
||||
@ -1096,46 +1096,45 @@ class IRCodeGen(
|
||||
} else {
|
||||
// integer comparisons
|
||||
branchDt = irDtLeft
|
||||
val leftRegNum = registers.nextFree()
|
||||
val rightRegNum = registers.nextFree()
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, tr, leftRegNum, -1)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
addToResult(result, tr, rightRegNum, -1)
|
||||
val leftTr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
require(rightTr.resultReg!=leftTr.resultReg)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
when (ifElse.condition.operator) {
|
||||
"==" -> {
|
||||
elseBranchOpcode = Opcode.BNE
|
||||
elseBranchFirstReg = leftRegNum
|
||||
elseBranchSecondReg = rightRegNum
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
"!=" -> {
|
||||
elseBranchOpcode = Opcode.BEQ
|
||||
elseBranchFirstReg = leftRegNum
|
||||
elseBranchSecondReg = rightRegNum
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
"<" -> {
|
||||
// else part when left >= right
|
||||
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
elseBranchFirstReg = leftRegNum
|
||||
elseBranchSecondReg = rightRegNum
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
">" -> {
|
||||
// else part when left <= right --> right >= left
|
||||
elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
elseBranchFirstReg = rightRegNum
|
||||
elseBranchSecondReg = leftRegNum
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
"<=" -> {
|
||||
// else part when left > right
|
||||
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
elseBranchFirstReg = leftRegNum
|
||||
elseBranchSecondReg = rightRegNum
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
">=" -> {
|
||||
// else part when left < right --> right > left
|
||||
elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
elseBranchFirstReg = rightRegNum
|
||||
elseBranchSecondReg = leftRegNum
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
}
|
||||
|
||||
@ -3,9 +3,11 @@ TODO
|
||||
|
||||
For next minor release
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
- fix VM bsieve not printing the last number and string correctly
|
||||
- fix IR/VM crashing in bouncegfx and textelite
|
||||
- reduce the usage of register.nextFree() in IR codegen
|
||||
- get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes...
|
||||
- get rid of all the require() checks that test result regs to be different
|
||||
|
||||
...
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user