fix cx16.r0 base address to be $04 on the C-64, and fix zeropage duplicate free addresses

codeCore/src/prog8/code/target/atari/AtariZeropage.kt

@@ -39,6 +39,10 @@ class AtariZeropage(options: CompilationOptions) : Zeropage(options) {
             }
         }
 
+        val distictFree = free.distinct()
+        free.clear()
+        free.addAll(distictFree)
+
         removeReservedFromFreePool()
     }
 

codeCore/src/prog8/code/target/c128/C128Zeropage.kt

@@ -38,6 +38,10 @@ class C128Zeropage(options: CompilationOptions) : Zeropage(options) {
             }
         }
 
+        val distictFree = free.distinct()
+        free.clear()
+        free.addAll(distictFree)
+
         removeReservedFromFreePool()
     }
 

codeCore/src/prog8/code/target/c64/C64Zeropage.kt

@@ -65,6 +65,10 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
             }
         }
 
+        val distictFree = free.distinct()
+        free.clear()
+        free.addAll(distictFree)
+
         removeReservedFromFreePool()
 
         if(options.zeropage==ZeropageType.FULL || options.zeropage==ZeropageType.KERNALSAFE) {
@@ -77,6 +81,7 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
         // Note: the 16 virtual registers R0-R15 are not regular allocated variables, they're *memory mapped* elsewhere to fixed addresses.
         // However, to be able for the compiler to "see" them as zero page variables, we have to register them here as well.
         // This is important because the compiler sometimes treats ZP variables more efficiently (for example if it's a pointer)
+        // The base addres is $04.  Unfortunately it cannot be the same as on the Commander X16 ($02).
         for(reg in 0..15) {
             allocatedVariables[listOf("cx16", "r${reg}")]   = ZpAllocation((4+reg*2).toUInt(), DataType.UWORD, 2)       // cx16.r0 .. cx16.r15
             allocatedVariables[listOf("cx16", "r${reg}s")]  = ZpAllocation((4+reg*2).toUInt(), DataType.WORD, 2)        // cx16.r0s .. cx16.r15s

codeCore/src/prog8/code/target/cx16/CX16Zeropage.kt

@@ -43,6 +43,10 @@ class CX16Zeropage(options: CompilationOptions) : Zeropage(options) {
                 else -> throw InternalCompilerException("for this machine target, zero page type 'floatsafe' is not available. ${options.zeropage}")
             }
 
+            val distictFree = free.distinct()
+            free.clear()
+            free.addAll(distictFree)
+
             removeReservedFromFreePool()
 
             allocateCx16VirtualRegisters()