Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2024-06-26 07:29:32 +00:00
Code Issues Projects Releases Wiki Activity

array in-place assignment problem

Browse Source
This commit is contained in:
Irmen de Jong 2023-03-10 01:02:25 +01:00
parent e779a07bce
commit 6c34672549
9 changed files with 71 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
codeGenCpu6502/src/prog8/codegen/cpu6502/AsmGen.kt
View File

@ -476,8 +476,8 @@ class AsmGen6502Internal (
internal fun assignExpressionToVariable(expr: PtExpression, asmVarName: String, dt: DataType, scope: IPtSubroutine?) =
assignmentAsmGen.assignExpressionToVariable(expr, asmVarName, dt, scope)
internal fun assignVariableToRegister(asmVarName: String, register: RegisterOrPair, signed: Boolean=false) =
assignmentAsmGen.assignVariableToRegister(asmVarName, register, signed)
internal fun assignVariableToRegister(asmVarName: String, register: RegisterOrPair, pos: Position, signed: Boolean=false) =
assignmentAsmGen.assignVariableToRegister(asmVarName, register, signed, pos)
internal fun assignRegister(reg: RegisterOrPair, target: AsmAssignTarget) {
when(reg) {
@ -597,11 +597,11 @@ class AsmGen6502Internal (
val name = asmVariableName(stmt.count as PtIdentifier)
when(vardecl.type) {
DataType.UBYTE, DataType.BYTE -> {
assignVariableToRegister(name, RegisterOrPair.Y)
assignVariableToRegister(name, RegisterOrPair.Y, stmt.count.position)
repeatCountInY(stmt, endLabel)
}
DataType.UWORD, DataType.WORD -> {
assignVariableToRegister(name, RegisterOrPair.AY)
assignVariableToRegister(name, RegisterOrPair.AY, stmt.count.position)
repeatWordCountInAY(endLabel, stmt)
}
else -> throw AssemblyError("invalid loop variable datatype $vardecl")
@ -3004,7 +3004,7 @@ $repeatLabel lda $counterVar
is PtVariable -> target.scopedName
else -> throw AssemblyError("weird target var")
}
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, this, target.type, scope, variableAsmName = asmVariableName(scopedName))
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, this, target.type, scope, target.position, variableAsmName = asmVariableName(scopedName))
if (dt in ByteDatatypes) {
out(" pla")
assignRegister(RegisterOrPair.A, tgt)

16
codeGenCpu6502/src/prog8/codegen/cpu6502/BuiltinFunctionsAsmGen.kt
View File

@ -246,9 +246,9 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
val src = AsmAssignSource(SourceStorageKind.EXPRESSION, program, asmgen, DataType.UWORD, expression = addressOf)
val target =
if(resultToStack)
AsmAssignTarget(TargetStorageKind.STACK, asmgen, DataType.UWORD, null)
AsmAssignTarget(TargetStorageKind.STACK, asmgen, DataType.UWORD, null, fcall.position)
else
AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, null, asmgen)
AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, fcall.position, null, asmgen)
val assign = AsmAssignment(src, target, program.memsizer, fcall.position)
asmgen.translateNormalAssignment(assign)
}
@ -259,7 +259,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
asmgen.out(" jsr prog8_lib.func_sqrt16_stack")
else {
asmgen.out(" jsr prog8_lib.func_sqrt16_into_A")
assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A)
}
}
@ -581,7 +581,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
DataType.FLOAT -> asmgen.out(" jsr floats.func_sign_f_into_A")
else -> throw AssemblyError("weird type $dt")
}
assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A)
}
}
@ -602,7 +602,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
DataType.ARRAY_F -> asmgen.out(" jsr floats.func_${fcall.name}_f_into_A | ldy #0")
else -> throw AssemblyError("weird type $dt")
}
assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, scope, asmgen), CpuRegister.A)
assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A)
}
}
@ -625,7 +625,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
DataType.WORD -> asmgen.out(" jsr prog8_lib.abs_w_into_AY")
else -> throw AssemblyError("weird type")
}
assignAsmGen.assignRegisterpairWord(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, scope, asmgen), RegisterOrPair.AY)
assignAsmGen.assignRegisterpairWord(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, fcall.position, scope, asmgen), RegisterOrPair.AY)
}
}
@ -1003,7 +1003,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
AsmAssignSource.fromAstSource(value, program, asmgen)
}
}
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, conv.dt, null, variableAsmName = varname)
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, conv.dt, null, value.position, variableAsmName = varname)
val assign = AsmAssignment(src, tgt, program.memsizer, value.position)
asmgen.translateNormalAssignment(assign)
}
@ -1021,7 +1021,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
AsmAssignSource.fromAstSource(value, program, asmgen)
}
}
val tgt = AsmAssignTarget.fromRegisters(conv.reg!!, false, null, asmgen)
val tgt = AsmAssignTarget.fromRegisters(conv.reg!!, false, value.position, null, asmgen)
val assign = AsmAssignment(src, tgt, program.memsizer, value.position)
asmgen.translateNormalAssignment(assign)
}

6
codeGenCpu6502/src/prog8/codegen/cpu6502/FunctionCallAsmGen.kt
View File

@ -200,14 +200,14 @@ internal class FunctionCallAsmGen(private val program: PtProgram, private val as
// we need to sign extend the source, do this via temporary word variable
asmgen.assignExpressionToVariable(value, "P8ZP_SCRATCH_W1", DataType.UBYTE, sub)
asmgen.signExtendVariableLsb("P8ZP_SCRATCH_W1", value.type)
asmgen.assignVariableToRegister("P8ZP_SCRATCH_W1", register)
asmgen.assignVariableToRegister("P8ZP_SCRATCH_W1", register, Position.DUMMY)
} else {
val target: AsmAssignTarget =
if(parameter.value.type in ByteDatatypes && (register==RegisterOrPair.AX || register == RegisterOrPair.AY || register==RegisterOrPair.XY || register in Cx16VirtualRegisters))
AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, parameter.value.type, sub, register = register)
AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, parameter.value.type, sub, value.position, register = register)
else {
val signed = parameter.value.type == DataType.BYTE || parameter.value.type == DataType.WORD
AsmAssignTarget.fromRegisters(register, signed, sub, asmgen)
AsmAssignTarget.fromRegisters(register, signed, value.position, sub, asmgen)
}
val src = if(value.type in PassByReferenceDatatypes) {
if(value is PtIdentifier) {

6
codeGenCpu6502/src/prog8/codegen/cpu6502/ProgramAndVarsGen.kt
View File

@ -339,7 +339,7 @@ internal class ProgramAndVarsGen(
asmgen.out("; simple int arg(s) passed via register(s)")
if(sub.parameters.size==1) {
val dt = sub.parameters[0].type
val target = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, sub, variableAsmName = sub.parameters[0].name)
val target = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, sub, sub.parameters[0].position, variableAsmName = sub.parameters[0].name)
if(dt in ByteDatatypes)
asmgen.assignRegister(RegisterOrPair.A, target)
else
@ -347,8 +347,8 @@ internal class ProgramAndVarsGen(
} else {
require(sub.parameters.size==2)
// 2 simple byte args, first in A, second in Y
val target1 = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, sub.parameters[0].type, sub, variableAsmName = sub.parameters[0].name)
val target2 = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, sub.parameters[1].type, sub, variableAsmName = sub.parameters[1].name)
val target1 = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, sub.parameters[0].type, sub, sub.parameters[0].position, variableAsmName = sub.parameters[0].name)
val target2 = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, sub.parameters[1].type, sub, sub.parameters[1].position, variableAsmName = sub.parameters[1].name)
asmgen.assignRegister(RegisterOrPair.A, target1)
asmgen.assignRegister(RegisterOrPair.Y, target2)
}

21
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AsmAssignment.kt
View File

@ -28,6 +28,7 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
private val asmgen: AsmGen6502Internal,
val datatype: DataType,
val scope: IPtSubroutine?,
val position: Position,
private val variableAsmName: String? = null,
val array: PtArrayIndexer? = null,
val memory: PtMemoryByte? = null,
@ -43,7 +44,7 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
asmgen.asmVariableName(array.variable)
}
lateinit var origAssign: AsmAssignmentBase
lateinit var origAssign: AsmAssignmentBase // TODO GET RID OF THIS
init {
if(register!=null && datatype !in NumericDatatypes)
@ -63,28 +64,28 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
if(reg.statusflag!=null)
throw AssemblyError("can't assign value to processor statusflag directly")
else
return AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, type, definingSub, register=reg.registerOrPair, origAstTarget = this)
return AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, type, definingSub, target.position, register=reg.registerOrPair, origAstTarget = this)
}
}
return AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, type, definingSub, variableAsmName = asmgen.asmVariableName(identifier!!), origAstTarget = this)
return AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, type, definingSub, target.position, variableAsmName = asmgen.asmVariableName(identifier!!), origAstTarget = this)
}
array != null -> return AsmAssignTarget(TargetStorageKind.ARRAY, asmgen, type, definingSub, array = array, origAstTarget = this)
memory != null -> return AsmAssignTarget(TargetStorageKind.MEMORY, asmgen, type, definingSub, memory = memory, origAstTarget = this)
array != null -> return AsmAssignTarget(TargetStorageKind.ARRAY, asmgen, type, definingSub, target.position, array = array, origAstTarget = this)
memory != null -> return AsmAssignTarget(TargetStorageKind.MEMORY, asmgen, type, definingSub, target.position, memory = memory, origAstTarget = this)
else -> throw AssemblyError("weird target")
}
}
}
fun fromRegisters(registers: RegisterOrPair, signed: Boolean, scope: IPtSubroutine?, asmgen: AsmGen6502Internal): AsmAssignTarget =
fun fromRegisters(registers: RegisterOrPair, signed: Boolean, pos: Position, scope: IPtSubroutine?, asmgen: AsmGen6502Internal): AsmAssignTarget =
when(registers) {
RegisterOrPair.A,
RegisterOrPair.X,
RegisterOrPair.Y -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.BYTE else DataType.UBYTE, scope, register = registers)
RegisterOrPair.Y -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.BYTE else DataType.UBYTE, scope, pos, register = registers)
RegisterOrPair.AX,
RegisterOrPair.AY,
RegisterOrPair.XY -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, register = registers)
RegisterOrPair.XY -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, pos, register = registers)
RegisterOrPair.FAC1,
RegisterOrPair.FAC2 -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, DataType.FLOAT, scope, register = registers)
RegisterOrPair.FAC2 -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, DataType.FLOAT, scope, pos, register = registers)
RegisterOrPair.R0,
RegisterOrPair.R1,
RegisterOrPair.R2,
@ -100,7 +101,7 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
RegisterOrPair.R12,
RegisterOrPair.R13,
RegisterOrPair.R14,
RegisterOrPair.R15 -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, register = registers)
RegisterOrPair.R15 -> AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, if(signed) DataType.WORD else DataType.UWORD, scope, pos, register = registers)
}
}
}

28
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AssignmentAsmGen.kt
View File

@ -318,7 +318,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
// array[x] = -value ... use a tempvar then store that back into the array.
val tempvar = asmgen.getTempVarName(assign.target.datatype)
val assignToTempvar = AsmAssignment(assign.source,
AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, assign.target.datatype, assign.target.scope,
AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, assign.target.datatype, assign.target.scope, assign.target.position,
variableAsmName=tempvar, origAstTarget = assign.target.origAstTarget), program.memsizer, assign.position)
asmgen.translateNormalAssignment(assignToTempvar)
when(assign.target.datatype) {
@ -818,7 +818,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
// use subroutine
assignExpressionToRegister(containment.element, RegisterOrPair.A, elementDt == DataType.BYTE)
asmgen.saveRegisterLocal(CpuRegister.A, containment.definingISub()!!)
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingISub(), "P8ZP_SCRATCH_W1"), varname)
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingISub(), symbol.astNode.position,"P8ZP_SCRATCH_W1"), varname)
asmgen.restoreRegisterLocal(CpuRegister.A)
val stringVal = (variable as PtVariable).value as PtString
asmgen.out(" ldy #${stringVal.value.length}")
@ -831,7 +831,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
DataType.ARRAY_B, DataType.ARRAY_UB -> {
assignExpressionToRegister(containment.element, RegisterOrPair.A, elementDt == DataType.BYTE)
asmgen.saveRegisterLocal(CpuRegister.A, containment.definingISub()!!)
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingISub(), "P8ZP_SCRATCH_W1"), varname)
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingISub(), symbol.astNode.position, "P8ZP_SCRATCH_W1"), varname)
asmgen.restoreRegisterLocal(CpuRegister.A)
asmgen.out(" ldy #$numElements")
asmgen.out(" jsr prog8_lib.containment_bytearray")
@ -839,7 +839,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
}
DataType.ARRAY_W, DataType.ARRAY_UW -> {
assignExpressionToVariable(containment.element, "P8ZP_SCRATCH_W1", elementDt, containment.definingISub())
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingISub(), "P8ZP_SCRATCH_W2"), varname)
assignAddressOf(AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UWORD, containment.definingISub(), symbol.astNode.position, "P8ZP_SCRATCH_W2"), varname)
asmgen.out(" ldy #$numElements")
asmgen.out(" jsr prog8_lib.containment_wordarray")
return
@ -1000,7 +1000,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
// have to typecast the float number on the fly down to an integer
assignExpressionToRegister(value, RegisterOrPair.FAC1, target.datatype in SignedDatatypes)
assignTypeCastedFloatFAC1("P8ZP_SCRATCH_W1", target.datatype)
assignVariableToRegister("P8ZP_SCRATCH_W1", target.register!!, target.datatype in SignedDatatypes)
assignVariableToRegister("P8ZP_SCRATCH_W1", target.register!!, target.datatype in SignedDatatypes, target.position)
return
} else {
if(!(valueDt isAssignableTo targetDt)) {
@ -1486,7 +1486,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
DataType.UBYTE, DataType.BYTE -> {
when(target.register!!) {
RegisterOrPair.A -> asmgen.out(" inx | lda P8ESTACK_LO,x")
RegisterOrPair.X -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
RegisterOrPair.X -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.position}")
RegisterOrPair.Y -> asmgen.out(" inx | ldy P8ESTACK_LO,x")
RegisterOrPair.AX -> asmgen.out(" inx | txy | ldx #0 | lda P8ESTACK_LO,y")
RegisterOrPair.AY -> asmgen.out(" inx | ldy #0 | lda P8ESTACK_LO,x")
@ -1505,9 +1505,9 @@ internal class AssignmentAsmGen(private val program: PtProgram,
}
DataType.UWORD, DataType.WORD, in PassByReferenceDatatypes -> {
when(target.register!!) {
RegisterOrPair.AX -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
RegisterOrPair.AX -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.position}")
RegisterOrPair.AY-> asmgen.out(" inx | ldy P8ESTACK_HI,x | lda P8ESTACK_LO,x")
RegisterOrPair.XY-> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
RegisterOrPair.XY-> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.position}")
in Cx16VirtualRegisters -> {
asmgen.out(
"""
@ -2054,7 +2054,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
// we make an exception in the type check for assigning something to a register pair AX, AY or XY
// these will be correctly typecasted from a byte to a word value here
if(target.register !in setOf(RegisterOrPair.AX, RegisterOrPair.AY, RegisterOrPair.XY))
require(target.datatype in ByteDatatypes) { "assign target must be byte type ${target.origAstTarget?.position ?: ""}"}
require(target.datatype in ByteDatatypes) { "assign target must be byte type ${target.position}"}
when(target.kind) {
TargetStorageKind.VARIABLE -> {
@ -2144,7 +2144,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
internal fun assignRegisterpairWord(target: AsmAssignTarget, regs: RegisterOrPair) {
require(target.datatype in NumericDatatypes || target.datatype in PassByReferenceDatatypes) {
"assign target must be word type ${target.origAstTarget?.position ?: ""}"
"assign target must be word type ${target.position}"
}
if(target.datatype==DataType.FLOAT)
throw AssemblyError("float value should be from FAC1 not from registerpair memory pointer")
@ -2828,7 +2828,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
internal fun assignExpressionToRegister(expr: PtExpression, register: RegisterOrPair, signed: Boolean) {
val src = AsmAssignSource.fromAstSource(expr, program, asmgen)
val tgt = AsmAssignTarget.fromRegisters(register, signed, null, asmgen)
val tgt = AsmAssignTarget.fromRegisters(register, signed, expr.position, null, asmgen)
val assign = AsmAssignment(src, tgt, program.memsizer, expr.position)
translateNormalAssignment(assign)
}
@ -2838,14 +2838,14 @@ internal class AssignmentAsmGen(private val program: PtProgram,
throw AssemblyError("can't directly assign a FLOAT expression to an integer variable $expr")
} else {
val src = AsmAssignSource.fromAstSource(expr, program, asmgen)
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, scope, variableAsmName = asmVarName)
val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, dt, scope, expr.position, variableAsmName = asmVarName)
val assign = AsmAssignment(src, tgt, program.memsizer, expr.position)
translateNormalAssignment(assign)
}
}
internal fun assignVariableToRegister(asmVarName: String, register: RegisterOrPair, signed: Boolean) {
val tgt = AsmAssignTarget.fromRegisters(register, signed, null, asmgen)
internal fun assignVariableToRegister(asmVarName: String, register: RegisterOrPair, signed: Boolean, pos: Position) {
val tgt = AsmAssignTarget.fromRegisters(register, signed, pos, null, asmgen)
val src = AsmAssignSource(SourceStorageKind.VARIABLE, program, asmgen, tgt.datatype, variableAsmName = asmVarName)
val assign = AsmAssignment(src, tgt, program.memsizer, Position.DUMMY)
translateNormalAssignment(assign)

22
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt
View File

@ -140,7 +140,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
}
else -> {
// TODO use some other evaluation here; don't use the estack to transfer the address to read/write from
asmgen.assignExpressionTo(memory.address, AsmAssignTarget(TargetStorageKind.STACK, asmgen, DataType.UWORD, memory.definingISub()))
asmgen.assignExpressionTo(memory.address, AsmAssignTarget(TargetStorageKind.STACK, asmgen, DataType.UWORD, memory.definingISub(), target.position))
asmgen.out(" jsr prog8_lib.read_byte_from_address_on_stack | sta P8ZP_SCRATCH_B1")
when {
valueLv != null -> inplaceModification_byte_litval_to_variable("P8ZP_SCRATCH_B1", DataType.UBYTE, operator, valueLv.toInt())
@ -207,10 +207,12 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
val tgt =
AsmAssignTarget.fromRegisters(
RegisterOrPair.A,
target.datatype == DataType.BYTE, null,
target.datatype == DataType.BYTE, target.position, null,
asmgen
)
val assign = AsmAssignment(target.origAssign.source, tgt, program.memsizer, value.position)
target.toAstExpression()
TODO("ORIGASSIGN IS AsmAugmentedAssignment CLASS: $target $operator= $value")
val assign = AsmAssignment(target.origAssign.source, tgt, program.memsizer, target.position)
assignmentAsmGen.translateNormalAssignment(assign)
assignmentAsmGen.assignRegisterByte(target, CpuRegister.A)
}
@ -218,10 +220,11 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
val tgt =
AsmAssignTarget.fromRegisters(
RegisterOrPair.AY,
target.datatype == DataType.WORD, null,
target.datatype == DataType.WORD, target.position, null,
asmgen
)
val assign = AsmAssignment(target.origAssign.source, tgt, program.memsizer, value.position)
TODO("ORIGASSIGN IS AsmAugmentedAssignment CLASS: $target $operator= $value")
val assign = AsmAssignment(target.origAssign.source, tgt, program.memsizer, target.position)
assignmentAsmGen.translateNormalAssignment(assign)
assignmentAsmGen.assignRegisterpairWord(target, RegisterOrPair.AY)
}
@ -229,10 +232,11 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
val tgt =
AsmAssignTarget.fromRegisters(
RegisterOrPair.FAC1,
true, null,
true, target.position, null,
asmgen
)
val assign = AsmAssignment(target.origAssign.source, tgt, program.memsizer, value.position)
TODO("ORIGASSIGN IS AsmAugmentedAssignment CLASS: $target $operator= $value")
val assign = AsmAssignment(target.origAssign.source, tgt, program.memsizer, target.position)
assignmentAsmGen.translateNormalAssignment(assign)
assignmentAsmGen.assignFAC1float(target)
}
@ -1672,7 +1676,7 @@ private fun AsmAssignSource.toAstExpression(scope: PtNamedNode): PtExpression {
private fun AsmAssignTarget.toAstExpression(): PtExpression {
return when(kind) {
TargetStorageKind.VARIABLE -> {
val ident = PtIdentifier((this.scope as PtNamedNode).scopedName + '.' + asmVarname, datatype, origAstTarget?.position ?: Position.DUMMY)
val ident = PtIdentifier((this.scope as PtNamedNode).scopedName + '.' + asmVarname, datatype, position)
ident.parent = this.scope
ident
}
@ -1680,7 +1684,7 @@ private fun AsmAssignTarget.toAstExpression(): PtExpression {
TargetStorageKind.MEMORY -> this.memory!!
TargetStorageKind.REGISTER -> {
if(register in Cx16VirtualRegisters) {
val ident = PtIdentifier("cx16.${register!!.name.lowercase()}", DataType.UWORD, position = this.origAssign.position)
val ident = PtIdentifier("cx16.${register!!.name.lowercase()}", DataType.UWORD, position)
ident.parent = (this.scope as? PtNamedNode) ?: this.origAstTarget!!
ident
} else {

2
docs/source/todo.rst
View File

@ -3,6 +3,8 @@ TODO
For next minor release
^^^^^^^^^^^^^^^^^^^^^^
- fix flakes2_yy[idx]+=10 and -=10 not working. Error is in line 205+ in AugmentableAssignmentAsmGen. Snow example in cx16 (balls as well?)
- try to get rid of AsmAssignTarget.origAssign
- fix Github issue with X register https://github.com/irmen/prog8/issues/94
- fix Github issue with array problems https://github.com/irmen/prog8/issues/99
- fix IR/VM: animals.p8 example is borked, it jumps straight to a suggestion and then somehow doesn't print the animal name correctly in the first question, and exits after 1 animal instead of looping

121
examples/test.p8
View File

@ -1,119 +1,22 @@
%import floats
%import textio
%option no_sysinit
%zeropage basicsafe
main {
uword b_wordvar
uword b_initwordvar = 12345
ubyte b_bb =123
float b_fl
ubyte[10] b_emptyarray
ubyte[10] b_filledarray = [1,2,3,4,5,6,7,8,9,10]
float[3] b_floatarray
uword[3] b_wordarray
sub start() {
uword wordvar
uword initwordvar = 12345
float fl
ubyte bb =123
ubyte[10] emptyarray
ubyte[10] filledarray = [1,2,3,4,5,6,7,8,9,10]
float[3] floatarray
uword[3] wordarray
uword slab1 = memory("slab1",400, 0)
uword slab2 = memory("slab2",200, $1000)
txt.print("**subroutine scope**\n")
txt.print("init wordvar=")
txt.print_uw(initwordvar)
txt.print("\ninit bb=")
txt.print_ub(bb)
txt.print("\nuninit wordvar=")
txt.print_uw(wordvar)
txt.print("\nuninit float=")
floats.print_f(fl)
txt.print("\nuninit emptyarray[2]=")
txt.print_ub(emptyarray[2])
txt.print("\nuninit wordarray[2]=")
txt.print_uw(wordarray[2])
txt.print("\nuninit floatarray[2]=")
floats.print_f(floatarray[2])
txt.print("\ninit filledarray[2]=")
txt.print_ub(filledarray[2])
txt.print("\n**block scope**\n")
txt.print("init wordvar=")
txt.print_uw(b_initwordvar)
txt.print("\ninit b_bb=")
txt.print_ub(b_bb)
txt.print("\nuninit b_wordvar=")
txt.print_uw(b_wordvar)
txt.print("\nuninit b_float=")
floats.print_f(b_fl)
txt.print("\nuninit b_emptyarray[2]=")
txt.print_ub(b_emptyarray[2])
txt.print("\nuninit b_wordarray[2]=")
txt.print_uw(b_wordarray[2])
txt.print("\nuninit b_floatarray[2]=")
floats.print_f(b_floatarray[2])
txt.print("\ninit b_filledarray[2]=")
txt.print_ub(b_filledarray[2])
txt.print("\n\nadding 42 to all values.\n")
wordvar += 42
bb += 42
fl += 42.42
floatarray[2] += 42.42
wordarray[2] += 42
emptyarray[2] += 42
filledarray[2] += 42
b_wordvar += 42
b_bb += 42
b_fl += 42.42
b_floatarray[2] += 42.42
b_wordarray[2] += 42
b_emptyarray[2] += 42
b_filledarray[2] += 42
txt.print("\n**subroutine scope**\n")
txt.print("uninit wordvar=")
txt.print_uw(wordvar)
txt.print("\nuninit float=")
floats.print_f(fl)
txt.print("\ninit bb=")
txt.print_ub(bb)
txt.print("\nuninit emptyarray[2]=")
txt.print_ub(emptyarray[2])
txt.print("\nuninit wordarray[2]=")
txt.print_uw(wordarray[2])
txt.print("\nuninit floatarray[2]=")
floats.print_f(floatarray[2])
txt.print("\ninit filledarray[2]=")
txt.print_ub(filledarray[2])
txt.print("\n**block scope**\n")
txt.print("uninit b_wordvar=")
txt.print_uw(b_wordvar)
txt.print("\nuninit b_float=")
floats.print_f(b_fl)
txt.print("\ninit b_bb=")
txt.print_ub(b_bb)
txt.print("\nuninit b_emptyarray[2]=")
txt.print_ub(b_emptyarray[2])
txt.print("\nuninit b_wordarray[2]=")
txt.print_uw(b_wordarray[2])
txt.print("\nuninit b_floatarray[2]=")
floats.print_f(b_floatarray[2])
txt.print("\ninit b_filledarray[2]=")
txt.print_ub(b_filledarray[2])
txt.print("\n\nrun again to see effect of re-init.\n")
txt.print_uwhex(slab1, true)
ubyte[] array= [1,2,3]
ubyte idx=1
txt.print_ub(array[idx])
txt.nl()
txt.print_uwhex(slab2, true)
array[idx]+=10
txt.print_ub(array[idx])
txt.nl()
idx=2
txt.print_ub(idx)
txt.nl()
idx+=10
txt.print_ub(idx)
txt.nl()
}
}