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vm postincrdecr on array done
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@ -386,7 +386,25 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
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code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
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code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg)
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code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg)
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} else if (array!=null) {
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} else if (array!=null) {
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TODO("postincrdecr array")
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val variable = array.variable.targetName
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var variableAddr = allocations.get(variable)
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val itemsize = program.memsizer.memorySize(array.type)
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val fixedIndex = (array.index as? PtNumber)?.number?.toInt()
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val memOp = when(postIncrDecr.operator) {
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"++" -> Opcode.INCM
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"--" -> Opcode.DECM
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else -> throw AssemblyError("weird operator")
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}
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if(fixedIndex!=null) {
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variableAddr += fixedIndex*itemsize
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code += VmCodeInstruction(memOp, vmDt, value=variableAddr)
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} else {
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val indexReg = vmRegisters.nextFree()
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code += expressionEval.translateExpression(array.index, indexReg)
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code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr)
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code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
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code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr)
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}
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} else
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} else
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throw AssemblyError("weird assigntarget")
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throw AssemblyError("weird assigntarget")
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@ -526,7 +544,7 @@ class CodeGen(internal val program: PtProgram,
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private var labelSequenceNumber = 0
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private var labelSequenceNumber = 0
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internal fun createLabelName(): List<String> {
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internal fun createLabelName(): List<String> {
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labelSequenceNumber++
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labelSequenceNumber++
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return listOf("generated$labelSequenceNumber")
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return listOf("prog8_label_gen_$labelSequenceNumber")
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}
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}
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internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk =
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internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk =
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@ -96,11 +96,12 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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val vmDt = codeGen.vmType(arrayIx.type)
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val vmDt = codeGen.vmType(arrayIx.type)
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val code = VmCodeChunk()
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val code = VmCodeChunk()
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val idxReg = codeGen.vmRegisters.nextFree()
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val idxReg = codeGen.vmRegisters.nextFree()
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// TODO: optimized code when the index is a constant value
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code += translateExpression(arrayIx.index, idxReg)
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code += translateExpression(arrayIx.index, idxReg)
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if(eltSize>1) {
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if(eltSize>1) {
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val factorReg = codeGen.vmRegisters.nextFree()
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val factorReg = codeGen.vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize)
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code += VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=factorReg)
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code += VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=idxReg, reg3=factorReg)
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}
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}
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val arrayLocation = codeGen.allocations.get(arrayIx.variable.targetName)
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val arrayLocation = codeGen.allocations.get(arrayIx.variable.targetName)
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code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation)
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code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation)
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@ -16,11 +16,12 @@ For next release
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can we make the code read the new layout from vera registers instead of hardcoding it?
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can we make the code read the new layout from vera registers instead of hardcoding it?
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- x16: optimize diskio load_raw because headerless files are now supported https://github.com/commanderx16/x16-rom/pull/216
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- x16: optimize diskio load_raw because headerless files are now supported https://github.com/commanderx16/x16-rom/pull/216
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note: must still work on c64/c128 that don't have this!
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note: must still work on c64/c128 that don't have this!
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- x16: cleanup references to r38/r39 in the docs and code
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- x16: fix the separate applications as well (assembler, ...)
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- vm codegen: When
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- vm codegen: When
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- vm codegen: Pipe expression
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- vm codegen: Pipe expression
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- vm codegen: validate that PtFunctionCall translation works okay with resultregister, and multiple paramsters in correct order
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- vm codegen: validate that PtFunctionCall translation works okay with resultregister, and multiple paramsters in correct order
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- vm codegen: postincrdecr arrayvalue
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- vm: support no globals re-init option
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- vm: support no globals re-init option
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- vm: how to remove all unused subroutines? (for asm, 64tass used to do this)
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- vm: how to remove all unused subroutines? (for asm, 64tass used to do this)
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- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks'
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- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks'
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@ -6,56 +6,31 @@ main {
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sub start() {
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sub start() {
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txt.clear_screen()
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txt.clear_screen()
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txt.print("Welcome to a prog8 pixel shader :-)\n")
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txt.print("Welcome to a prog8 pixel shader :-)\n")
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uword ww = 0
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ubyte bc
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uword wc
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for bc in "irmen" {
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byte[] barr = [-1,-2,-3]
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txt.chrout(bc)
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uword[] uwarr = [1111,2222,3333]
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ww++
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}
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txt.print_uw(ww) ; 5
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txt.nl()
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for bc in [10,11,12] {
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txt.print_b(barr[2])
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txt.print_ub(bc)
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txt.spc()
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txt.spc()
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ww++
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txt.print_uw(uwarr[2])
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}
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txt.print_uw(ww) ; 8
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txt.nl()
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txt.nl()
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txt.nl()
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for wc in [4097,8193,16385] {
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barr[2] --
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txt.print_uw(wc)
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uwarr[2] --
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txt.print_b(barr[2])
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txt.spc()
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txt.spc()
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ww++
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txt.print_uw(uwarr[2])
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}
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txt.print_uw(ww) ; 11
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txt.nl()
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txt.nl()
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ubyte rfrom = 10
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barr[2] ++
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ubyte rto = 17
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uwarr[2] ++
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for bc in rfrom to rto step 2 {
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txt.print_b(barr[2])
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; 10,12,14,16
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txt.print_ub(bc)
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txt.spc()
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txt.spc()
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ww++
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txt.print_uw(uwarr[2])
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}
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txt.print_uw(ww) ; 15
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txt.nl()
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txt.nl()
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for bc in 30 to 0 step -4 {
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; 30,26,22,18,14,10,6,2
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txt.print_ub(bc)
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txt.spc()
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ww++
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}
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txt.print_uw(ww) ; 23
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txt.nl()
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sys.exit(99)
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sys.exit(99)
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