mirror of
https://github.com/irmen/prog8.git
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vm: implemented in-memory bit shift instructions
This commit is contained in:
Irmen de Jong
parent
0a48ef3030
commit
b646f50265
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@ -90,6 +90,8 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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"|" -> return expressionEval.operatorOrInplace(address, vmDt, operand)
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"&" -> return expressionEval.operatorAndInplace(address, vmDt, operand)
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"^" -> return expressionEval.operatorXorInplace(address, vmDt, operand)
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"<<" -> return expressionEval.operatorShiftLeftInplace(address, vmDt, operand)
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">>" -> return expressionEval.operatorShiftRightInplace(address, vmDt, signed, operand)
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else -> {}
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}
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return fallbackAssign(origAssign)
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@ -446,21 +446,13 @@ class CodeGen(internal val program: PtProgram,
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val pow2 = powersOfTwo.indexOf(factor)
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if(pow2==1) {
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// just shift 1 bit
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// TODO use a memory shift instruction?
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val reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LSL, dt, reg1=reg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LSLM, dt, value = address)
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}
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else if(pow2>=1) {
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// just shift multiple bits
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// TODO use a memory shift instruction?
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val reg = vmRegisters.nextFree()
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val pow2reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)
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code += VmCodeInstruction(Opcode.LSLN, dt, reg1=reg, reg2=pow2reg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LSLNM, dt, reg1=pow2reg, value=address)
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} else {
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if (factor == 0) {
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code += VmCodeInstruction(Opcode.STOREZM, dt, value=address)
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@ -547,27 +539,19 @@ class CodeGen(internal val program: PtProgram,
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val pow2 = powersOfTwo.indexOf(factor)
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if(pow2==1) {
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// just shift 1 bit
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// TODO use memory-shift instruction?
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val reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=reg, value=address)
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code += if(signed)
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VmCodeInstruction(Opcode.ASR, dt, reg1=reg)
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VmCodeInstruction(Opcode.ASRM, dt, value=address)
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else
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VmCodeInstruction(Opcode.LSR, dt, reg1=reg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=reg, value=address)
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VmCodeInstruction(Opcode.LSRM, dt, value=address)
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}
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else if(pow2>=1) {
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// just shift multiple bits
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// TODO use memory-shift instruction?
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val reg = vmRegisters.nextFree()
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val pow2reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)
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code += if(signed)
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VmCodeInstruction(Opcode.ASRN, dt, reg1=reg, reg2=pow2reg)
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VmCodeInstruction(Opcode.ASRNM, dt, reg1=pow2reg, value=address)
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else
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VmCodeInstruction(Opcode.LSRN, dt, reg1=reg, reg2=pow2reg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=reg, value=address)
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VmCodeInstruction(Opcode.LSRNM, dt, reg1=pow2reg, value=address)
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} else {
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if (factor == 0) {
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val reg = vmRegisters.nextFree()
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@ -454,6 +454,20 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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}
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internal fun operatorShiftRightInplace(address: Int, vmDt: VmDataType, signed: Boolean, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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if(codeGen.isOne(operand)) {
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val opc = if (signed) Opcode.ASRM else Opcode.LSRM
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code += VmCodeInstruction(opc, vmDt, value=address)
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} else {
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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val opc = if (signed) Opcode.ASRNM else Opcode.LSRNM
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code += VmCodeInstruction(opc, vmDt, reg1 = operandReg, value=address)
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}
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return code
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}
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private fun operatorShiftLeft(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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if(codeGen.isOne(binExpr.right)){
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@ -468,6 +482,18 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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}
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internal fun operatorShiftLeftInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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if(codeGen.isOne(operand)){
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code += VmCodeInstruction(Opcode.LSLM, vmDt, value=address)
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} else {
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.LSLNM, vmDt, reg1=operandReg, value=address)
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}
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return code
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}
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private fun operatorXor(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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@ -435,16 +435,15 @@ internal fun asmGeneratorFor(program: Program,
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{
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if(options.experimentalCodegen) {
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if (options.compTarget.machine.cpu in arrayOf(CpuType.CPU6502, CpuType.CPU65c02)) {
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// TODO for now, use the new Intermediary Ast for this experimental codegen:
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val intermediateAst = IntermediateAstMaker(program).transform()
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return prog8.codegen.experimental.AsmGen(intermediateAst, symbolTable, options, errors)
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}
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} else {
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if (options.compTarget.machine.cpu in arrayOf(CpuType.CPU6502, CpuType.CPU65c02))
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// TODO rewrite 6502 codegen on new Intermediary Ast
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return prog8.codegen.cpu6502.AsmGen(program, symbolTable, options, errors)
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if (options.compTarget.name == VMTarget.NAME) {
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// TODO for now, use the new Intermediary Ast for this codegen:
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val intermediateAst = IntermediateAstMaker(program).transform()
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return prog8.codegen.virtual.CodeGen(intermediateAst, symbolTable, options, errors)
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}
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@ -119,9 +119,9 @@ class AstPreprocessor(val program: Program, val errors: IErrorReporter, val comp
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val newSegments = psrc.segments
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newSegments += pipe.segments.single()
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return listOf(IAstModification.ReplaceNode(pipe as Node, Pipe(newSource, newSegments, pipe.position), parent))
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}
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return process(pipe, parent)
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} else if(pipe.source is IPipe)
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throw InternalCompilerException("pipe source should have been adjusted to be a normal expression")
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return noModifications
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}
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override fun before(pipeExpr: PipeExpression, parent: Node): Iterable<IAstModification> {
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@ -132,46 +132,8 @@ class AstPreprocessor(val program: Program, val errors: IErrorReporter, val comp
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val newSegments = psrc.segments
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newSegments += pipeExpr.segments.single()
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return listOf(IAstModification.ReplaceNode(pipeExpr as Node, PipeExpression(newSource, newSegments, pipeExpr.position), parent))
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}
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return process(pipeExpr, parent)
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}
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private fun process(pipe: IPipe, parent: Node): Iterable<IAstModification> {
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if(pipe.source is IPipe)
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} else if(pipeExpr.source is IPipe)
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throw InternalCompilerException("pipe source should have been adjusted to be a normal expression")
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return noModifications
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// TODO don't use artifical inserted args, fix the places that check for arg numbers instead.
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// add the "missing" first argument to each function call in the pipe segments
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// so that all function call related checks just pass
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// might have to remove it again when entering code generation pass, or just replace it there
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// with the proper output value of the previous pipe segment.
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// val mutations = mutableListOf<IAstModification>()
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// var valueDt = pipe.source.inferType(program).getOrElse { throw FatalAstException("invalid dt") }
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// pipe.segments.forEach { call->
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// val dummyFirstArg = when (valueDt) {
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// DataType.UBYTE -> FunctionCallExpression(IdentifierReference(listOf("rnd"), pipe.position), mutableListOf(), pipe.position)
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// DataType.UWORD -> FunctionCallExpression(IdentifierReference(listOf("rndw"), pipe.position), mutableListOf(), pipe.position)
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// DataType.BYTE, DataType.WORD -> IdentifierReference(
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// getTempRegisterName(InferredTypes.InferredType.known(valueDt)),
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// pipe.position
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// ) // there's no builtin function we can abuse that returns a signed byte or word type // TODO maybe use a typecasted expression around rnd?
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// DataType.FLOAT -> FunctionCallExpression(IdentifierReference(listOf("rndf"), pipe.position), mutableListOf(), pipe.position)
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// else -> throw FatalAstException("invalid dt")
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// }
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//
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// mutations += IAstModification.SetExpression(
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// { newexpr -> call.args.add(0, newexpr) },
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// dummyFirstArg, parent
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// )
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//
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// if(call!==pipe.segments.last())
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// valueDt = call.inferType(program).getOrElse { throw FatalAstException("invalid dt") }
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// }
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// return mutations
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}
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}
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@ -227,11 +227,9 @@ internal class BeforeAsmAstChanger(val program: Program,
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// TODO: somehow figure out if the expr will result in stack-evaluation STILL after being split off,
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// in that case: do *not* split it off but just keep it as it is (otherwise code size increases)
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// TODO: this should be replaced by a general expression-evaluation optimization step.
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// the actual conditional expression in the statement should be no more than VARIABLE <COMPARISON-OPERATOR> SIMPLE-EXPRESSION
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// NOTE: do NOT move this to an earler ast transform phase (such as StatementReorderer or StatementOptimizer) - it WILL result in larger code.
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if(options.compTarget.name==VMTarget.NAME)
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if(options.compTarget.name==VMTarget.NAME) // don't apply this optimizer for Vm target
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return CondExprSimplificationResult(null, null, null, null)
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var leftAssignment: Assignment? = null
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@ -3,6 +3,7 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- vm: implement the 4 rol/ror memory in-place instructions
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...
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@ -34,29 +34,39 @@ main {
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sub start() {
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; mcCarthy()
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ubyte bb
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for bb in 250 to 255 {
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txt.print_ub(bb)
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txt.spc()
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}
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ubyte @shared bb = %10110001
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byte @shared sb = -99
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bb *= 2
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bb /= 2
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bb *= 8
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bb /= 8
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txt.print_ub(bb) ; 17
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txt.nl()
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sb *= 2
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sb /= 2
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sb *= 8
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sb /= 8
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txt.print_b(sb) ; -3
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txt.nl()
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; ; a "pixelshader":
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sys.gfx_enable(0) ; enable lo res screen
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ubyte shifter
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repeat {
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uword xx
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uword yy = 0
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repeat 240 {
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xx = 0
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repeat 320 {
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sys.gfx_plot(xx, yy, xx*yy + shifter as ubyte)
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xx++
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}
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yy++
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}
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shifter+=4
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}
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; sys.gfx_enable(0) ; enable lo res screen
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; ubyte shifter
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;
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; repeat {
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; uword xx
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; uword yy = 0
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; repeat 240 {
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; xx = 0
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; repeat 320 {
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; sys.gfx_plot(xx, yy, xx*yy + shifter as ubyte)
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; xx++
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; }
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; yy++
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; }
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; shifter+=4
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; }
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}
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}
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@ -8,7 +8,9 @@ class Assembler {
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private val placeholders = mutableMapOf<Int, String>()
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init {
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require(instructionFormats.size== Opcode.values().size)
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require(instructionFormats.size== Opcode.values().size) {
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"missing " + (Opcode.values().toSet() - instructionFormats.keys)
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}
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}
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fun initializeMemory(memsrc: String, memory: Memory) {
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@ -128,17 +128,23 @@ xorm reg1, address - memory = memory bitwise xor reg1
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not reg1 - reg1 = boolean not of reg1 (0->1 , ~0 -> 0)
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notm address - memory = boolean not of that memory (0->1 , ~0 -> 0)
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lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
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lsrnm reg1, address - multi-shift memoryright by reg1 bits + set Carry to shifted bit
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asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
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asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + set Carry to shifted bit
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lsln reg1, reg2 - reg1 = multi-shift reg1 left by reg2 bits + set Carry to shifted bit
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lslnm reg1, address - multi-shift memory left by reg1 bits + set Carry to shifted bit
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lsr reg1 - shift reg1 right by 1 bits + set Carry to shifted bit
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lsrm address - shift memory right by 1 bits + set Carry to shifted bit
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asr reg1 - shift reg1 right by 1 bits (signed) + set Carry to shifted bit
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asrm address - shift memory right by 1 bits (signed) + set Carry to shifted bit
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lsl reg1 - shift reg1 left by 1 bits + set Carry to shifted bit
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lslm address - shift memory left by 1 bits + set Carry to shifted bit
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ror reg1 - rotate reg1 right by 1 bits, not using carry + set Carry to shifted bit
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roxr reg1 - rotate reg1 right by 1 bits, using carry + set Carry to shifted bit
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rol reg1 - rotate reg1 left by 1 bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1 bits, using carry, + set Carry to shifted bit
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TODO: add memory-shift instructions?
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TODO: add memory-rotate instructions?
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FLOATING POINT CONVERSIONS AND FUNCTIONS
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@ -251,11 +257,17 @@ enum class Opcode {
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NOT,
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NOTM,
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ASRN,
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ASRNM,
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LSRN,
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LSRNM,
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LSLN,
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LSLNM,
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ASR,
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ASRM,
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LSR,
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LSRM,
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LSL,
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LSLM,
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ROR,
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ROXR,
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ROL,
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@ -310,7 +322,13 @@ val OpcodesWithAddress = setOf(
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Opcode.NOTM,
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Opcode.ORM,
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Opcode.XORM,
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Opcode.ANDM
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Opcode.ANDM,
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Opcode.ASRM,
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Opcode.LSRM,
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Opcode.LSLM,
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Opcode.LSLNM,
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Opcode.LSRNM,
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Opcode.ASRNM
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)
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@ -524,11 +542,17 @@ val instructionFormats = mutableMapOf(
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Opcode.NOT to InstructionFormat.from("BW,r1"),
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Opcode.NOTM to InstructionFormat.from("BW,v"),
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Opcode.ASRN to InstructionFormat.from("BW,r1,r2"),
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Opcode.ASRNM to InstructionFormat.from("BW,r1,v"),
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Opcode.LSRN to InstructionFormat.from("BW,r1,r2"),
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Opcode.LSRNM to InstructionFormat.from("BW,r1,v"),
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Opcode.LSLN to InstructionFormat.from("BW,r1,r2"),
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Opcode.LSLNM to InstructionFormat.from("BW,r1,v"),
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Opcode.ASR to InstructionFormat.from("BW,r1"),
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Opcode.ASRM to InstructionFormat.from("BW,v"),
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Opcode.LSR to InstructionFormat.from("BW,r1"),
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Opcode.LSRM to InstructionFormat.from("BW,v"),
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Opcode.LSL to InstructionFormat.from("BW,r1"),
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Opcode.LSLM to InstructionFormat.from("BW,v"),
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Opcode.ROR to InstructionFormat.from("BW,r1"),
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Opcode.ROXR to InstructionFormat.from("BW,r1"),
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Opcode.ROL to InstructionFormat.from("BW,r1"),
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@ -95,7 +95,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.STOREM -> InsSTOREM(ins)
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Opcode.STOREX -> InsSTOREX(ins)
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Opcode.STOREI -> InsSTOREI(ins)
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Opcode.STOREZM -> InsSTOREZ(ins)
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Opcode.STOREZM -> InsSTOREZM(ins)
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Opcode.STOREZX -> InsSTOREZX(ins)
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Opcode.STOREZI -> InsSTOREZI(ins)
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Opcode.JUMP -> InsJUMP(ins)
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@ -162,12 +162,18 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.XORM ->InsXORM(ins)
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Opcode.NOT -> InsNOT(ins)
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Opcode.NOTM -> InsNOTM(ins)
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Opcode.ASRN -> InsASRM(ins)
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Opcode.LSRN -> InsLSRM(ins)
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Opcode.LSLN -> InsLSLM(ins)
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Opcode.ASRN -> InsASRN(ins)
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Opcode.LSRN -> InsLSRN(ins)
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Opcode.LSLN -> InsLSLN(ins)
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Opcode.ASR -> InsASR(ins)
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Opcode.LSR -> InsLSR(ins)
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Opcode.LSL -> InsLSL(ins)
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Opcode.ASRNM -> InsASRNM(ins)
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Opcode.LSRNM -> InsLSRNM(ins)
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Opcode.LSLNM -> InsLSLNM(ins)
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Opcode.ASRM -> InsASRM(ins)
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Opcode.LSRM -> InsLSRM(ins)
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Opcode.LSLM -> InsLSLM(ins)
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Opcode.ROR -> InsROR(ins, false)
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Opcode.ROXR -> InsROR(ins, true)
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Opcode.ROL -> InsROL(ins, false)
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|
|
@ -334,7 +340,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsSTOREZ(i: Instruction) {
|
||||
private fun InsSTOREZM(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> memory.setUB(i.value!!, 0u)
|
||||
VmDataType.WORD -> memory.setUW(i.value!!, 0u)
|
||||
|
|
@ -1162,7 +1168,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsASRM(i: Instruction) {
|
||||
private fun InsASRN(i: Instruction) {
|
||||
val (left: Int, right: Int) = getLogicalOperandsS(i)
|
||||
statusCarry = (left and 1)!=0
|
||||
when(i.type!!) {
|
||||
|
|
@ -1173,6 +1179,25 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsASRNM(i: Instruction) {
|
||||
val address = i.value!!
|
||||
val operand = registers.getUB(i.reg1!!).toInt()
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val memvalue = memory.getSB(address).toInt()
|
||||
statusCarry = (memvalue and 1)!=0
|
||||
memory.setSB(address, (memvalue shr operand).toByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val memvalue = memory.getSW(address).toInt()
|
||||
statusCarry = (memvalue and 1)!=0
|
||||
memory.setSW(address, (memvalue shr operand).toShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsASR(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
|
|
@ -1190,7 +1215,25 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSRM(i: Instruction) {
|
||||
private fun InsASRM(i: Instruction) {
|
||||
val address = i.value!!
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = memory.getSB(address).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
memory.setSB(address, (value shr 1).toByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val value = memory.getSW(address).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
memory.setSW(address, (value shr 1).toShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSRN(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
statusCarry = (left and 1u)!=0u
|
||||
when(i.type!!) {
|
||||
|
|
@ -1201,6 +1244,25 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSRNM(i: Instruction) {
|
||||
val address = i.value!!
|
||||
val operand = registers.getUB(i.reg1!!).toInt()
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val memvalue = memory.getUB(address).toInt()
|
||||
statusCarry = (memvalue and 1)!=0
|
||||
memory.setUB(address, (memvalue shr operand).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val memvalue = memory.getUW(address).toInt()
|
||||
statusCarry = (memvalue and 1)!=0
|
||||
memory.setUW(address, (memvalue shr operand).toUShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSR(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
|
|
@ -1218,7 +1280,25 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSLM(i: Instruction) {
|
||||
private fun InsLSRM(i: Instruction) {
|
||||
val address = i.value!!
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = memory.getUB(address).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
memory.setUB(address, (value shr 1).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val value = memory.getUW(address).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
memory.setUW(address, (value shr 1).toUShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSLN(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
|
|
@ -1234,6 +1314,25 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSLNM(i: Instruction) {
|
||||
val address = i.value!!
|
||||
val operand = registers.getUB(i.reg1!!).toInt()
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val memvalue = memory.getUB(address).toInt()
|
||||
statusCarry = (memvalue and 0x80)!=0
|
||||
memory.setUB(address, (memvalue shl operand).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val memvalue = memory.getUW(address).toInt()
|
||||
statusCarry = (memvalue and 0x8000)!=0
|
||||
memory.setUW(address, (memvalue shl operand).toUShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSL(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
|
|
@ -1251,6 +1350,24 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSLM(i: Instruction) {
|
||||
val address = i.value!!
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = memory.getUB(address).toInt()
|
||||
statusCarry = (value and 0x80)!=0
|
||||
memory.setUB(address, (value shl 1).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val value = memory.getUW(address).toInt()
|
||||
statusCarry = (value and 0x8000)!=0
|
||||
memory.setUW(address, (value shl 1).toUShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsROR(i: Instruction, useCarry: Boolean) {
|
||||
val newStatusCarry: Boolean
|
||||
when (i.type!!) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user