Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2024-12-01 15:52:54 +00:00
Code Issues Projects Releases Wiki Activity

IR: fix comparison codegen errors in newexpr path

Browse Source
This commit is contained in:
Irmen de Jong 2023-04-05 00:15:09 +02:00
parent b6a837cbea
commit befe0fff2a
2 changed files with 30 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
View File

@ -1216,16 +1216,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
it += IRInstruction(Opcode.SEQ, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(Opcode.SEQ, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
} }
} else { } else {
// symbol = symbol == operand // symbol = symbol == operand
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
it += IRInstruction(Opcode.SEQ, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(Opcode.SEQ, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
} }
} }
return result return result
@ -1240,16 +1240,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
it += IRInstruction(Opcode.SNE, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(Opcode.SNE, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
} }
} else { } else {
// symbol = symbol != operand // symbol = symbol != operand
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
it += IRInstruction(Opcode.SNE, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(Opcode.SNE, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
} }
} }
return result return result
@ -1265,16 +1265,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
} }
} else { } else {
// symbol = symbol > operand // symbol = symbol > operand
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
} }
} }
return result return result
@ -1290,16 +1290,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
} }
} else { } else {
// symbol = symbol < operand // symbol = symbol < operand
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
} }
} }
return result return result
@ -1315,16 +1315,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
} }
} else { } else {
// symbol = symbol > operand // symbol = symbol > operand
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
} }
} }
return result return result
@ -1340,16 +1340,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
} }
} else { } else {
// symbol = symbol > operand // symbol = symbol > operand
val valueReg = codeGen.registers.nextFree() val valueReg = codeGen.registers.nextFree()
result += IRCodeChunk(null, null).also { result += IRCodeChunk(null, null).also {
it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol) it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg) it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
} }
} }
return result return result

7
docs/source/todo.rst
View File

@ -4,11 +4,16 @@ TODO
For next minor release For next minor release
^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^
newxpr vm: fix bouncegfx (crash), bsieve (loops), primes (way too many), textelite (map is wrong, incomplete planet info) newxpr vm: vm/bsieve.p8 has wrong result
once everything works, disable -newexpr option for IR/virtual target because that already works without eval stack
and creates far superior code without the newexpr flattening.
IR (normal): fix reg1 out of bounds crash in compiler/test/comparisons/test_compares.p8
... ...
For 9.0 major changes For 9.0 major changes
^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^
- get rid of the disknumber parameter everywhere in diskio, make it a configurable variable that defaults to 8. - get rid of the disknumber parameter everywhere in diskio, make it a configurable variable that defaults to 8.