mirror of
https://github.com/irmen/prog8.git
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adding setlsb() and setmsb() builtin functions to 6502 codegen
This commit is contained in:
Irmen de Jong
parent
a1874f6f00
commit
ccf6e32bf9
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@ -612,51 +612,82 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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}
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private fun funcSetLsbMsb(fcall: PtBuiltinFunctionCall, msb: Boolean) {
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asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A, false)
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val address: PtExpression
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val target: AsmAssignTarget
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when(fcall.args[0]) {
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is PtIdentifier -> {
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if(msb) {
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address = PtBinaryExpression("+", DataType.UWORD, fcall.args[0].position)
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val addressOf = PtAddressOf(fcall.position)
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addressOf.add(fcall.args[0])
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address.add(addressOf)
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address.add(PtNumber(address.type, 1.0, fcall.args[0].position))
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} else {
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address = PtAddressOf(fcall.position)
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address.add(fcall.args[0])
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}
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val varname = asmgen.asmVariableName(fcall.args[0] as PtIdentifier) + if(msb) "+1" else ""
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target = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UBYTE, fcall.definingSub(), fcall.position, variableAsmName = varname)
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}
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is PtNumber -> {
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val num = (fcall.args[0] as PtNumber).number + if(msb) 1 else 0
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address = PtNumber(fcall.args[0].type, num, fcall.args[0].position)
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val mem = PtMemoryByte(fcall.position)
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mem.add(PtNumber(DataType.UBYTE, num, fcall.position))
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target = AsmAssignTarget(TargetStorageKind.MEMORY, asmgen, DataType.UBYTE, fcall.definingSub(), fcall.position, memory = mem)
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}
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is PtAddressOf -> {
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val mem = PtMemoryByte(fcall.position)
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if(msb) {
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address = PtBinaryExpression("+", DataType.UWORD, fcall.args[0].position)
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val address = PtBinaryExpression("+", DataType.UWORD, fcall.args[0].position)
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address.add(fcall.args[0])
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address.add(PtNumber(address.type, 1.0, fcall.args[0].position))
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mem.add(address)
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} else {
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address = fcall.args[0]
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mem.add(fcall.args[0])
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}
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target = AsmAssignTarget(TargetStorageKind.MEMORY, asmgen, DataType.UBYTE, fcall.definingSub(), fcall.position, memory = mem)
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}
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is PtArrayIndexer -> {
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val indexer = fcall.args[0] as PtArrayIndexer
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require(!indexer.usesPointerVariable)
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val elementSize: Int
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val msbAdd: Int
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if(indexer.splitWords) {
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// lsb/msb in split arrays, element index 'size' is always 1
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TODO("setlsb/setmsb on split array element ${fcall.position}")
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val arrayVariable = indexer.variable
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indexer.children[0] = PtIdentifier(arrayVariable.name + if(msb) "_msb" else "_lsb", DataType.ARRAY_UB, arrayVariable.position)
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indexer.children[0].parent = indexer
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elementSize = 1
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msbAdd = 0
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} else {
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TODO("setlsb/setmsb on array element ${fcall.position}")
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elementSize = 2
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msbAdd = if(msb) 1 else 0
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}
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// double the index because of word array (if not split), add one if msb (if not split)
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val constIndexNum = (indexer.index as? PtNumber)?.number
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if(constIndexNum!=null) {
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indexer.children[1] = PtNumber(indexer.index.type, constIndexNum*elementSize + msbAdd, indexer.position)
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indexer.children[1].parent = indexer
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} else {
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val multipliedIndex: PtExpression
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if(elementSize==1) {
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multipliedIndex = indexer.index
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} else {
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multipliedIndex = PtBinaryExpression("<<", indexer.index.type, indexer.position)
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multipliedIndex.add(indexer.index)
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multipliedIndex.add(PtNumber(DataType.UBYTE, 1.0, indexer.position))
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}
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if(msbAdd>0) {
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val msbIndex = PtBinaryExpression("+", indexer.index.type, indexer.position)
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msbIndex.add(multipliedIndex)
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msbIndex.add(PtNumber(DataType.UBYTE, msbAdd.toDouble(), indexer.position))
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indexer.children[1] = msbIndex
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msbIndex.parent = indexer
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} else {
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indexer.children[1] = multipliedIndex
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multipliedIndex.parent=indexer
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}
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}
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target = AsmAssignTarget(TargetStorageKind.ARRAY, asmgen, DataType.UBYTE, fcall.definingSub(), fcall.position, array = indexer)
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}
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else -> throw AssemblyError("setlsb/setmsb on weird target ${fcall.args[0]}")
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}
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val mem = PtMemoryByte(fcall.position)
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mem.add(address)
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mem.parent = fcall
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assignAsmGen.storeRegisterAInMemoryAddress(mem) // TODO use assignRegisterByte()???, and assignConstantByte() if the value is contstant zero
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if(fcall.args[1].asConstInteger() == 0) {
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assignAsmGen.assignConstantByte(target, 0)
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} else {
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asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A, false)
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assignAsmGen.assignRegisterByte(target, CpuRegister.A, false)
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}
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}
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private fun funcSgn(fcall: PtBuiltinFunctionCall, resultRegister: RegisterOrPair?, scope: IPtSubroutine?) {
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@ -2717,68 +2717,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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TargetStorageKind.ARRAY -> {
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if(assignAsWord)
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TODO("assign register as word into Array not yet supported")
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if(target.array!!.splitWords)
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TODO("assign register into split words ${target.position}")
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if(assignsIndexedPointerVar(target)) {
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if (target.constArrayIndexValue!=null) {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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if(asmgen.isZpVar(target.origAstTarget!!.array!!.variable)) {
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asmgen.out(" ldy #${target.constArrayIndexValue} | sta (${target.asmVarname}),y")
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} else {
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asmgen.out("""
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ldy ${target.asmVarname}
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sty P8ZP_SCRATCH_W1
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ldy ${target.asmVarname}+1
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sty P8ZP_SCRATCH_W1+1
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ldy #${target.constArrayIndexValue}
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sta (P8ZP_SCRATCH_W1),y""")
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}
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}
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else {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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val indexVar = target.array.index as PtIdentifier
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if(asmgen.isZpVar(target.origAstTarget!!.array!!.variable)) {
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asmgen.out(" ldy ${asmgen.asmVariableName(indexVar)} | sta (${target.asmVarname}),y")
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} else {
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asmgen.out("""
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ldy ${target.asmVarname}
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sty P8ZP_SCRATCH_W1
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ldy ${target.asmVarname}+1
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sty P8ZP_SCRATCH_W1+1
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ldy ${asmgen.asmVariableName(indexVar)}
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sta (P8ZP_SCRATCH_W1),y""")
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}
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}
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return
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} else {
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// assign regular array indexing
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if (target.constArrayIndexValue!=null) {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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asmgen.out(" sta ${target.asmVarname}+${target.constArrayIndexValue}")
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}
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else {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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val indexVar = target.array.index as PtIdentifier
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asmgen.out(" ldy ${asmgen.asmVariableName(indexVar)} | sta ${target.asmVarname},y")
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}
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}
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TODO("assign register byte as word into Array not yet supported")
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assignRegisterByteToArray(target, register)
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}
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TargetStorageKind.REGISTER -> {
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when(register) {
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@ -2926,6 +2866,79 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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}
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private fun assignRegisterByteToArray(target: AsmAssignTarget, register: CpuRegister) {
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if(target.array!!.splitWords)
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throw AssemblyError("cannot assign byte to split word array here ${target.position}")
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if(assignsIndexedPointerVar(target)) {
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if (target.constArrayIndexValue!=null) {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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if(asmgen.isZpVar(target.origAstTarget!!.array!!.variable)) {
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asmgen.out(" ldy #${target.constArrayIndexValue} | sta (${target.asmVarname}),y")
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} else {
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asmgen.out("""
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ldy ${target.asmVarname}
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sty P8ZP_SCRATCH_W1
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ldy ${target.asmVarname}+1
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sty P8ZP_SCRATCH_W1+1
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ldy #${target.constArrayIndexValue}
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sta (P8ZP_SCRATCH_W1),y""")
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}
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}
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else {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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val indexVar = target.array.index as PtIdentifier
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if(asmgen.isZpVar(target.origAstTarget!!.array!!.variable)) {
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asmgen.out(" ldy ${asmgen.asmVariableName(indexVar)} | sta (${target.asmVarname}),y")
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} else {
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asmgen.out("""
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ldy ${target.asmVarname}
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sty P8ZP_SCRATCH_W1
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ldy ${target.asmVarname}+1
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sty P8ZP_SCRATCH_W1+1
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ldy ${asmgen.asmVariableName(indexVar)}
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sta (P8ZP_SCRATCH_W1),y""")
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}
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}
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return
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} else {
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// assign regular array indexing
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if (target.constArrayIndexValue!=null) {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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asmgen.out(" sta ${target.asmVarname}+${target.constArrayIndexValue}")
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}
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else {
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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val indexVar = target.array.index as? PtIdentifier
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if(indexVar!=null) {
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asmgen.out(" ldy ${asmgen.asmVariableName(indexVar)} | sta ${target.asmVarname},y")
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} else {
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require(target.array.index.type in ByteDatatypes)
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asmgen.saveRegisterStack(register, false)
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asmgen.assignExpressionToRegister(target.array.index, RegisterOrPair.Y, false)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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asmgen.out(" sta ${target.asmVarname},y")
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}
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}
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}
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}
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internal fun assignRegisterpairWord(target: AsmAssignTarget, regs: RegisterOrPair) {
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require(target.datatype in NumericDatatypes || target.datatype in PassByReferenceDatatypes) {
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"assign target must be word type ${target.position}"
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@ -3205,7 +3218,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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}
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private fun assignConstantByte(target: AsmAssignTarget, byte: Int) {
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internal fun assignConstantByte(target: AsmAssignTarget, byte: Int) {
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if(byte==0 && asmgen.isTargetCpu(CpuType.CPU65c02)) {
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// optimize setting zero value for this cpu
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when(target.kind) {
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@ -3233,14 +3246,14 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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return
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}
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if(target.array!!.splitWords)
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TODO("assign into split words ${target.position}")
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throw AssemblyError("cannot assign byte to split word array here ${target.position}")
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if (target.constArrayIndexValue!=null) {
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val indexValue = target.constArrayIndexValue!!
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asmgen.out(" stz ${target.asmVarname}+$indexValue")
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}
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else {
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asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UBYTE, CpuRegister.Y)
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asmgen.out(" lda #0 | sta ${target.asmVarname},y")
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asmgen.assignExpressionToRegister(target.array.index, RegisterOrPair.X, false)
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asmgen.out(" stz ${target.asmVarname},x")
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}
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}
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TargetStorageKind.REGISTER -> when(target.register!!) {
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@ -3306,17 +3319,11 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldx #${byte.toHex()}")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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in Cx16VirtualRegisters -> {
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asmgen.out(
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" lda #${byte.toHex()} | sta cx16.${
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target.register.toString().lowercase()
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}")
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asmgen.out(" lda #${byte.toHex()} | sta cx16.${target.register.toString().lowercase()}")
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz cx16.${target.register.toString().lowercase()}+1\n")
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else
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asmgen.out(
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" lda #0 | sta cx16.${
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target.register.toString().lowercase()
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}+1\n")
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asmgen.out(" lda #0 | sta cx16.${target.register.toString().lowercase()}+1\n")
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}
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else -> throw AssemblyError("weird register")
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}
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@ -581,66 +581,109 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcSetLsbMsb(call: PtBuiltinFunctionCall, msb: Boolean): ExpressionCodeResult {
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val result = mutableListOf<IRCodeChunkBase>()
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val target = call.args[0]
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val isConstZeroValue = call.args[1].asConstInteger()==0
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when(target) {
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is PtIdentifier -> {
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val valueTr = exprGen.translateExpression(call.args[1])
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addToResult(result, valueTr, valueTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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val pointerReg = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1=pointerReg, labelSymbol = target.name)
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if(msb)
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it += IRInstruction(Opcode.INC, IRDataType.WORD, reg1=pointerReg)
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it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=pointerReg)
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// TODO use STOREZI if the value is zero
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if(isConstZeroValue) {
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result += IRCodeChunk(null, null).also {
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val pointerReg = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1 = pointerReg, labelSymbol = target.name)
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if (msb)
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it += IRInstruction(Opcode.INC, IRDataType.WORD, reg1 = pointerReg)
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it += IRInstruction(Opcode.STOREZI, IRDataType.BYTE, reg1 = pointerReg)
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}
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} else {
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val valueTr = exprGen.translateExpression(call.args[1])
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addToResult(result, valueTr, valueTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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val pointerReg = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1 = pointerReg, labelSymbol = target.name)
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if (msb)
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it += IRInstruction(Opcode.INC, IRDataType.WORD, reg1 = pointerReg)
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it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueTr.resultReg, reg2 = pointerReg)
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}
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}
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}
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is PtArrayIndexer -> {
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require(!target.usesPointerVariable)
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if(target.splitWords) {
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// lsb/msb in split arrays, element index 'size' is always 1
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val varName = target.variable.name + if(msb) "_msb" else "_lsb"
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val valueTr = exprGen.translateExpression(call.args[1])
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addToResult(result, valueTr, valueTr.resultReg, -1)
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val constIndex = target.index.asConstInteger()
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if(constIndex!=null) {
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val offsetReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = constIndex)
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=offsetReg, labelSymbol = varName)
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// TODO: use STOREZX if the value is zero
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val varName = target.variable.name + if(msb) "_msb" else "_lsb"
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if(isConstZeroValue) {
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if(constIndex!=null) {
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val offsetReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = constIndex)
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it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1=offsetReg, labelSymbol = varName)
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}
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} else {
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val indexTr = exprGen.translateExpression(target.index)
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addToResult(result, indexTr, indexTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1=indexTr.resultReg, labelSymbol = varName)
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}
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}
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} else {
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val indexTr = exprGen.translateExpression(target.index)
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addToResult(result, indexTr, indexTr.resultReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=indexTr.resultReg, labelSymbol = varName)
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// TODO: use STOREZX if the value is zero
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val valueTr = exprGen.translateExpression(call.args[1])
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addToResult(result, valueTr, valueTr.resultReg, -1)
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if(constIndex!=null) {
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val offsetReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = constIndex)
|
||||
it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=offsetReg, labelSymbol = varName)
|
||||
}
|
||||
} else {
|
||||
val indexTr = exprGen.translateExpression(target.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=indexTr.resultReg, labelSymbol = varName)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
val valueTr = exprGen.translateExpression(call.args[1])
|
||||
addToResult(result, valueTr, valueTr.resultReg, -1)
|
||||
val eltSize = codeGen.program.memsizer.memorySize(target.type)
|
||||
val constIndex = target.index.asConstInteger()
|
||||
if(constIndex!=null) {
|
||||
val offsetReg = codeGen.registers.nextFree()
|
||||
val offset = eltSize*constIndex + if(msb) 1 else 0
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = offset)
|
||||
it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=offsetReg, labelSymbol = target.variable.name)
|
||||
// TODO: use STOREZX if the value is zero
|
||||
if(isConstZeroValue) {
|
||||
if(constIndex!=null) {
|
||||
val offsetReg = codeGen.registers.nextFree()
|
||||
val offset = eltSize*constIndex + if(msb) 1 else 0
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = offset)
|
||||
it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1=offsetReg, labelSymbol = target.variable.name)
|
||||
}
|
||||
} else {
|
||||
val indexTr = exprGen.translateExpression(target.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
if(eltSize>1)
|
||||
it += codeGen.multiplyByConst(IRDataType.BYTE, indexTr.resultReg, eltSize)
|
||||
if(msb)
|
||||
it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexTr.resultReg)
|
||||
it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1=indexTr.resultReg, labelSymbol = target.variable.name)
|
||||
}
|
||||
}
|
||||
} else {
|
||||
val indexTr = exprGen.translateExpression(target.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
if(eltSize>1)
|
||||
it += codeGen.multiplyByConst(IRDataType.BYTE, indexTr.resultReg, eltSize)
|
||||
if(msb)
|
||||
it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexTr.resultReg)
|
||||
it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=indexTr.resultReg, labelSymbol = target.variable.name)
|
||||
// TODO: use STOREZX if the value is zero
|
||||
val valueTr = exprGen.translateExpression(call.args[1])
|
||||
addToResult(result, valueTr, valueTr.resultReg, -1)
|
||||
if(constIndex!=null) {
|
||||
val offsetReg = codeGen.registers.nextFree()
|
||||
val offset = eltSize*constIndex + if(msb) 1 else 0
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = offset)
|
||||
it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=offsetReg, labelSymbol = target.variable.name)
|
||||
}
|
||||
} else {
|
||||
val indexTr = exprGen.translateExpression(target.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
if(eltSize>1)
|
||||
it += codeGen.multiplyByConst(IRDataType.BYTE, indexTr.resultReg, eltSize)
|
||||
if(msb)
|
||||
it += IRInstruction(Opcode.INC, IRDataType.BYTE, reg1=indexTr.resultReg)
|
||||
it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=indexTr.resultReg, labelSymbol = target.variable.name)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ TODO
|
|||
====
|
||||
|
||||
- allow taking address of array variable (now gives parser error)
|
||||
- ir: the @split arrays are currently also split in _lsb/_msb arrays in the IR, and operations take multiple (byte) instructions that may lead to verbose and slow operation and machine code generation down the line.
|
||||
|
||||
- [on branch: shortcircuit] investigate McCarthy evaluation again? this may also reduce code size perhaps for things like if a>4 or a<2 ....
|
||||
- IR: reduce the number of branch instructions such as BEQ, BEQR, etc (gradually), replace with CMP(I) + status branch instruction
|
||||
|
|
@ -38,7 +39,6 @@ Compiler:
|
|||
global initialization values are simply a list of LOAD instructions.
|
||||
Variables replaced include all subroutine parameters! So the only variables that remain as variables are arrays and strings.
|
||||
- ir: add more optimizations in IRPeepholeOptimizer
|
||||
- ir: the @split arrays are currently also split in _lsb/_msb arrays in the IR, and operations take multiple (byte) instructions that may lead to verbose and slow operation and machine code generation down the line.
|
||||
- ir: for expressions with array indexes that occur multiple times, can we avoid loading them into new virtualregs everytime and just reuse a single virtualreg as indexer? (simple form of common subexpression elimination)
|
||||
- PtAst/IR: more complex common subexpression eliminations
|
||||
- [problematic due to using 64tass:] better support for building library programs, where unused .proc shouldn't be deleted from the assembly?
|
||||
|
|
|
|||
|
|
@ -8,16 +8,16 @@ main {
|
|||
txt.nl()
|
||||
|
||||
;@(&zz) = $11
|
||||
setlsb(zz, $11)
|
||||
setlsb(zz, 0)
|
||||
txt.print_uwhex(zz, true)
|
||||
txt.nl()
|
||||
;@(&zz+1) = $22
|
||||
setmsb(zz, $22)
|
||||
setmsb(zz, 0)
|
||||
txt.print_uwhex(zz, true)
|
||||
txt.nl()
|
||||
txt.nl()
|
||||
|
||||
uword[] array = [$1234,$5678,$abcd] ; TODO also with @split
|
||||
uword[] @split array = [$1234,$5678,$abcd] ; TODO also with @split
|
||||
|
||||
ubyte one = 1
|
||||
ubyte two = 2
|
||||
|
|
@ -27,8 +27,8 @@ main {
|
|||
txt.nl()
|
||||
;@(&array+one*2) = $ff
|
||||
;@(&array+two*2+1) = $ff
|
||||
setlsb(array[one],$ff)
|
||||
setmsb(array[two],$00)
|
||||
setlsb(array[one],0)
|
||||
setmsb(array[two],0)
|
||||
txt.print_uwhex(array[1], true)
|
||||
txt.nl()
|
||||
txt.print_uwhex(array[2], true)
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
<Keywords name="Keywords1">void const
str
byte ubyte bool
word uword
float
zp shared split requirezp</Keywords>
|
||||
<Keywords name="Keywords2">%address
%asm
%ir
%asmbinary
%asminclude
%breakpoint
%import
%launcher
%option
%output
%zeropage
%zpreserved</Keywords>
|
||||
<Keywords name="Keywords3">inline sub asmsub romsub
clobbers
asm
if
when else
if_cc if_cs if_eq if_mi if_neg if_nz if_pl if_pos if_vc if_vs if_z
for in step do while repeat unroll
break return goto</Keywords>
|
||||
<Keywords name="Keywords4">abs all any callfar clamp cmp divmod len lsb lsl lsr memory mkword min max msb peek peekw poke pokew push pushw pop popw rsave rsavex rrestore rrestorex reverse rnd rndw rol rol2 ror ror2 sgn sizeof sort sqrtw swap</Keywords>
|
||||
<Keywords name="Keywords4">abs all any callfar clamp cmp divmod len lsb lsl lsr memory mkword min max msb peek peekw poke pokew push pushw pop popw rsave rsavex rrestore rrestorex reverse rnd rndw rol rol2 ror ror2 setlsb setmsb sgn sizeof sort sqrtw swap</Keywords>
|
||||
<Keywords name="Keywords5">true false
not and or xor
as to downto |></Keywords>
|
||||
<Keywords name="Keywords6"></Keywords>
|
||||
<Keywords name="Keywords7"></Keywords>
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ syn keyword prog8BuiltInFunc any all len reverse sort
|
|||
|
||||
" Miscellaneous functions
|
||||
syn keyword prog8BuiltInFunc cmp divmod lsb msb mkword min max peek peekw poke pokew push pushw pop popw rsave rsavex rrestore rrestorex
|
||||
syn keyword prog8BuiltInFunc rol rol2 ror ror2 sizeof
|
||||
syn keyword prog8BuiltInFunc rol rol2 ror ror2 sizeof setlsb setmsb
|
||||
syn keyword prog8BuiltInFunc swap memory callfar clamp
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user