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vm: fix repeat 256
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parent
04da44eb98
commit
d3f6415387
@ -1500,7 +1500,10 @@ class IRCodeGen(
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val result = mutableListOf<IRCodeChunkBase>()
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val countTr = expressionEval.translateExpression(repeat.count)
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addToResult(result, countTr, countTr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.BEQ, irDt, reg1=countTr.resultReg, immediate = 0, labelSymbol = skipRepeatLabel), null)
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if(constIntValue(repeat.count)==null) {
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// check if the counter is already zero
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addInstr(result, IRInstruction(Opcode.BEQ, irDt, reg1=countTr.resultReg, immediate = 0, labelSymbol = skipRepeatLabel), null)
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}
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result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.DEC, irDt, reg1 = countTr.resultReg)
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@ -215,7 +215,7 @@ main {
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var result = compileText(target, true, src, writeAssembly = true)!!
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var virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.stepCount shouldBe 37
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vm.stepCount shouldBe 36
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}
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result = compileText(target, false, src, writeAssembly = true)!!
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@ -363,4 +363,38 @@ main {
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}"""
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compileText(VMTarget(), false, text, writeAssembly = true) shouldNotBe null
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}
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test("repeat counts") {
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val src="""
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main {
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sub start() {
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cx16.r0 = 0
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repeat 255 {
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cx16.r0++
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}
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repeat 256 {
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cx16.r0++
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}
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repeat 257 {
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cx16.r0++
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}
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repeat 1023 {
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cx16.r0++
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}
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repeat 1024 {
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cx16.r0++
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}
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repeat 1025 {
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cx16.r0++
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}
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}
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}"""
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val result = compileText(VMTarget(), false, src, writeAssembly = true)!!
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val start = result.codegenAst!!.entrypoint()!!
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start.children.size shouldBe 8
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.memory.getUW(vm.cx16virtualregsBaseAddress) shouldBe 3840u
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}
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}
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})
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@ -3,17 +3,49 @@
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main {
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sub start() {
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byte[] foo = [ 1, 2, ; this comment is ok
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; but after this comment there's a syntax error
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3 ]
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byte bb
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for bb in foo {
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txt.print_b(bb)
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txt.nl()
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cx16.r0 = 0
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repeat 255 {
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cx16.r0++
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}
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txt.print_uw(255)
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txt.spc()
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txt.print_uw(cx16.r0)
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txt.nl()
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repeat 256 {
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cx16.r0++
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}
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txt.print_uw(255+256)
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txt.spc()
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txt.print_uw(cx16.r0)
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txt.nl()
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repeat 257 {
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cx16.r0++
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}
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txt.print_uw(255+256+257)
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txt.spc()
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txt.print_uw(cx16.r0)
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txt.nl()
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repeat 1023 {
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cx16.r0++
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}
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txt.print_uw(255+256+257+1023)
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txt.spc()
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txt.print_uw(cx16.r0)
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txt.nl()
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repeat 1024 {
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cx16.r0++
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}
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txt.print_uw(255+256+257+1023+1024)
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txt.spc()
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txt.print_uw(cx16.r0)
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txt.nl()
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repeat 1025 {
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cx16.r0++
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}
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txt.print_uw(255+256+257+1023+1024+1025)
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txt.spc()
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txt.print_uw(cx16.r0)
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txt.nl()
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}
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}
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@ -47,7 +47,7 @@ class VirtualMachine(irProgram: IRProgram) {
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var statusNegative = false
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internal var randomGenerator = Random(0xa55a7653)
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internal var randomGeneratorFloats = Random(0xc0d3dbad)
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private val cx16virtualregsBaseAddress: Int
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val cx16virtualregsBaseAddress: Int
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init {
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program = VmProgramLoader().load(irProgram, memory)
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