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https://github.com/irmen/prog8.git
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vm: implemented in-place bit rotate instructions
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Irmen de Jong
parent
b646f50265
commit
e09f054058
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@ -772,7 +772,6 @@ class CodeGen(internal val program: PtProgram,
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}
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private fun translate(sub: PtSub): VmCodeChunk {
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// TODO actually inline subroutines marked as inline (but at this time only asmsub can be inline)
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val code = VmCodeChunk()
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code += VmCodeComment("SUB: ${sub.scopedName} -> ${sub.returntype}")
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code += VmCodeLabel(sub.scopedName)
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@ -3,7 +3,6 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- vm: implement the 4 rol/ror memory in-place instructions
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...
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@ -120,31 +120,33 @@ LOGICAL/BITWISE
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All have type b or w.
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and reg1, reg2 - reg1 = reg1 bitwise and reg2
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andm reg1 address - memory = memory bitwise and reg1
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or reg1, reg2 - reg1 = reg1 bitwise or reg2
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orm reg1, address - memory = memory bitwise or reg1
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xor reg1, reg2 - reg1 = reg1 bitwise xor reg2
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xorm reg1, address - memory = memory bitwise xor reg1
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not reg1 - reg1 = boolean not of reg1 (0->1 , ~0 -> 0)
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notm address - memory = boolean not of that memory (0->1 , ~0 -> 0)
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lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
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lsrnm reg1, address - multi-shift memoryright by reg1 bits + set Carry to shifted bit
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asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
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asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + set Carry to shifted bit
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lsln reg1, reg2 - reg1 = multi-shift reg1 left by reg2 bits + set Carry to shifted bit
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lslnm reg1, address - multi-shift memory left by reg1 bits + set Carry to shifted bit
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lsr reg1 - shift reg1 right by 1 bits + set Carry to shifted bit
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lsrm address - shift memory right by 1 bits + set Carry to shifted bit
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asr reg1 - shift reg1 right by 1 bits (signed) + set Carry to shifted bit
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asrm address - shift memory right by 1 bits (signed) + set Carry to shifted bit
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lsl reg1 - shift reg1 left by 1 bits + set Carry to shifted bit
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lslm address - shift memory left by 1 bits + set Carry to shifted bit
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ror reg1 - rotate reg1 right by 1 bits, not using carry + set Carry to shifted bit
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roxr reg1 - rotate reg1 right by 1 bits, using carry + set Carry to shifted bit
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rol reg1 - rotate reg1 left by 1 bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1 bits, using carry, + set Carry to shifted bit
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TODO: add memory-rotate instructions?
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andm reg1 address - memory = memory bitwise and reg1
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orm reg1, address - memory = memory bitwise or reg1
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xorm reg1, address - memory = memory bitwise xor reg1
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notm address - memory = boolean not of that memory (0->1 , ~0 -> 0)
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lsrnm reg1, address - multi-shift memoryright by reg1 bits + set Carry to shifted bit
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asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + set Carry to shifted bit
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lslnm reg1, address - multi-shift memory left by reg1 bits + set Carry to shifted bit
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lsrm address - shift memory right by 1 bits + set Carry to shifted bit
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asrm address - shift memory right by 1 bits (signed) + set Carry to shifted bit
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lslm address - shift memory left by 1 bits + set Carry to shifted bit
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rorm address - rotate memory right by 1 bits, not using carry + set Carry to shifted bit
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roxrm address - rotate memory right by 1 bits, using carry + set Carry to shifted bit
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rolm address - rotate memory left by 1 bits, not using carry + set Carry to shifted bit
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roxlm address - rotate memory left by 1 bits, using carry, + set Carry to shifted bit
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FLOATING POINT CONVERSIONS AND FUNCTIONS
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@ -269,9 +271,13 @@ enum class Opcode {
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LSL,
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LSLM,
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ROR,
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RORM,
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ROXR,
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ROXRM,
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ROL,
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ROLM,
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ROXL,
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ROXLM,
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FFROMUB,
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FFROMSB,
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@ -328,7 +334,11 @@ val OpcodesWithAddress = setOf(
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Opcode.LSLM,
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Opcode.LSLNM,
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Opcode.LSRNM,
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Opcode.ASRNM
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Opcode.ASRNM,
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Opcode.ROLM,
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Opcode.RORM,
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Opcode.ROXLM,
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Opcode.ROXRM
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)
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@ -554,9 +564,13 @@ val instructionFormats = mutableMapOf(
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Opcode.LSL to InstructionFormat.from("BW,r1"),
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Opcode.LSLM to InstructionFormat.from("BW,v"),
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Opcode.ROR to InstructionFormat.from("BW,r1"),
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Opcode.RORM to InstructionFormat.from("BW,v"),
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Opcode.ROXR to InstructionFormat.from("BW,r1"),
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Opcode.ROXRM to InstructionFormat.from("BW,v"),
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Opcode.ROL to InstructionFormat.from("BW,r1"),
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Opcode.ROLM to InstructionFormat.from("BW,v"),
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Opcode.ROXL to InstructionFormat.from("BW,r1"),
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Opcode.ROXLM to InstructionFormat.from("BW,v"),
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Opcode.FFROMUB to InstructionFormat.from("F,fr1,r1"),
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Opcode.FFROMSB to InstructionFormat.from("F,fr1,r1"),
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@ -175,9 +175,13 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.LSRM -> InsLSRM(ins)
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Opcode.LSLM -> InsLSLM(ins)
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Opcode.ROR -> InsROR(ins, false)
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Opcode.RORM -> InsRORM(ins, false)
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Opcode.ROXR -> InsROR(ins, true)
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Opcode.ROXRM -> InsRORM(ins, true)
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Opcode.ROL -> InsROL(ins, false)
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Opcode.ROLM -> InsROLM(ins, false)
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Opcode.ROXL -> InsROL(ins, true)
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Opcode.ROXLM -> InsROLM(ins, true)
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Opcode.MSIG -> InsMSIG(ins)
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Opcode.CONCAT -> InsCONCAT(ins)
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Opcode.PUSH -> InsPUSH(ins)
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@ -1399,6 +1403,38 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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statusCarry = newStatusCarry
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}
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private fun InsRORM(i: Instruction, useCarry: Boolean) {
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val newStatusCarry: Boolean
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val address = i.value!!
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when (i.type!!) {
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VmDataType.BYTE -> {
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val orig = memory.getUB(address)
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newStatusCarry = (orig.toInt() and 1) != 0
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val rotated: UByte = if (useCarry) {
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val carry = if (statusCarry) 0x80u else 0x00u
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(orig.toUInt().rotateRight(1) or carry).toUByte()
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} else
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orig.rotateRight(1)
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memory.setUB(address, rotated)
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}
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VmDataType.WORD -> {
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val orig = memory.getUW(address)
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newStatusCarry = (orig.toInt() and 1) != 0
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val rotated: UShort = if (useCarry) {
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val carry = if (statusCarry) 0x8000u else 0x0000u
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(orig.toUInt().rotateRight(1) or carry).toUShort()
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} else
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orig.rotateRight(1)
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memory.setUW(address, rotated)
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}
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VmDataType.FLOAT -> {
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throw IllegalArgumentException("can't ROR a float")
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}
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}
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pc++
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statusCarry = newStatusCarry
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}
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private fun InsROL(i: Instruction, useCarry: Boolean) {
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val newStatusCarry: Boolean
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when (i.type!!) {
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@ -1430,6 +1466,38 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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statusCarry = newStatusCarry
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}
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private fun InsROLM(i: Instruction, useCarry: Boolean) {
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val address = i.value!!
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val newStatusCarry: Boolean
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when (i.type!!) {
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VmDataType.BYTE -> {
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val orig = memory.getUB(address)
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newStatusCarry = (orig.toInt() and 0x80) != 0
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val rotated: UByte = if (useCarry) {
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val carry = if (statusCarry) 1u else 0u
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(orig.toUInt().rotateLeft(1) or carry).toUByte()
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} else
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orig.rotateLeft(1)
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memory.setUB(address, rotated)
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}
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VmDataType.WORD -> {
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val orig = memory.getUW(address)
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newStatusCarry = (orig.toInt() and 0x8000) != 0
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val rotated: UShort = if (useCarry) {
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val carry = if (statusCarry) 1u else 0u
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(orig.toUInt().rotateLeft(1) or carry).toUShort()
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} else
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orig.rotateLeft(1)
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memory.setUW(address, rotated)
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}
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VmDataType.FLOAT -> {
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throw IllegalArgumentException("can't ROL a float")
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}
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}
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pc++
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statusCarry = newStatusCarry
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}
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private fun InsMSIG(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> {
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