mirror of
https://github.com/irmen/prog8.git
synced 2024-11-26 11:49:22 +00:00
working on vm
This commit is contained in:
Irmen de Jong
parent
3e1a7c6102
commit
f46300016d
@ -8,9 +8,9 @@ import prog8.vm.Opcode
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import prog8.vm.Syscall
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import prog8.vm.VmDataType
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internal class BuiltinFuncGen(val codeGen: CodeGen, val exprGen: ExpressionGen) {
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internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen: ExpressionGen) {
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fun translate(call: PtBuiltinFunctionCall, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
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fun translate(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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when(call.name) {
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"syscall" -> {
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@ -20,19 +20,19 @@ internal class BuiltinFuncGen(val codeGen: CodeGen, val exprGen: ExpressionGen)
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"syscall1" -> {
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code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
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val callNr = (call.args[0] as PtNumber).number.toInt()
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code += exprGen.translateExpression(call.args[1], 0, regUsage)
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code += exprGen.translateExpression(call.args[1], 0)
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code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
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code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
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}
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"syscall2" -> {
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code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
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code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 1))
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while(regUsage.firstFree<2) {
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regUsage.nextFree()
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while(codeGen.vmRegisters.peekNext()<2) {
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codeGen.vmRegisters.nextFree()
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}
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val callNr = (call.args[0] as PtNumber).number.toInt()
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code += exprGen.translateExpression(call.args[1], 0, regUsage)
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code += exprGen.translateExpression(call.args[2], 1, regUsage)
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code += exprGen.translateExpression(call.args[1], 0)
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code += exprGen.translateExpression(call.args[2], 1)
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code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
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code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 1))
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code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
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@ -41,25 +41,25 @@ internal class BuiltinFuncGen(val codeGen: CodeGen, val exprGen: ExpressionGen)
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code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
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code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 1))
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code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 2))
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while(regUsage.firstFree<3) {
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regUsage.nextFree()
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while(codeGen.vmRegisters.peekNext()<3) {
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codeGen.vmRegisters.nextFree()
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}
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val callNr = (call.args[0] as PtNumber).number.toInt()
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code += exprGen.translateExpression(call.args[1], 0, regUsage)
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code += exprGen.translateExpression(call.args[2], 1, regUsage)
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code += exprGen.translateExpression(call.args[3], 2, regUsage)
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code += exprGen.translateExpression(call.args[1], 0)
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code += exprGen.translateExpression(call.args[2], 1)
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code += exprGen.translateExpression(call.args[3], 2)
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code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
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code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 2))
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code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 1))
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code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
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}
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"msb" -> {
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code += exprGen.translateExpression(call.args.single(), resultRegister, regUsage)
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code += exprGen.translateExpression(call.args.single(), resultRegister)
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code += VmCodeInstruction(Instruction(Opcode.SWAP, VmDataType.BYTE, reg1 = resultRegister, reg2=resultRegister))
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// note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here.
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}
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"lsb" -> {
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code += exprGen.translateExpression(call.args.single(), resultRegister, regUsage)
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code += exprGen.translateExpression(call.args.single(), resultRegister)
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// note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here.
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}
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"memory" -> {
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@ -83,27 +83,27 @@ internal class BuiltinFuncGen(val codeGen: CodeGen, val exprGen: ExpressionGen)
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code += VmCodeInstruction(Instruction(Opcode.LOADR, VmDataType.BYTE, reg1=resultRegister, reg2=0))
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}
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"peek" -> {
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val addressReg = regUsage.nextFree()
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code += exprGen.translateExpression(call.args.single(), addressReg, regUsage)
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val addressReg = codeGen.vmRegisters.nextFree()
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code += exprGen.translateExpression(call.args.single(), addressReg)
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code += VmCodeInstruction(Instruction(Opcode.LOADI, VmDataType.BYTE, reg1 = resultRegister, reg2=addressReg))
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}
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"peekw" -> {
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val addressReg = regUsage.nextFree()
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code += exprGen.translateExpression(call.args.single(), addressReg, regUsage)
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val addressReg = codeGen.vmRegisters.nextFree()
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code += exprGen.translateExpression(call.args.single(), addressReg)
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code += VmCodeInstruction(Instruction(Opcode.LOADI, VmDataType.WORD, reg1 = resultRegister, reg2=addressReg))
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}
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"mkword" -> {
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val msbReg = regUsage.nextFree()
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val lsbReg = regUsage.nextFree()
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code += exprGen.translateExpression(call.args[0], msbReg, regUsage)
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code += exprGen.translateExpression(call.args[1], lsbReg, regUsage)
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val msbReg = codeGen.vmRegisters.nextFree()
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val lsbReg = codeGen.vmRegisters.nextFree()
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code += exprGen.translateExpression(call.args[0], msbReg)
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code += exprGen.translateExpression(call.args[1], lsbReg)
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code += VmCodeInstruction(Instruction(Opcode.CONCAT, VmDataType.BYTE, reg1=resultRegister, reg2=msbReg, reg3=lsbReg))
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}
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else -> {
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TODO("builtinfunc ${call.name}")
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// code += VmCodeInstruction(Instruction(Opcode.NOP))
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// for (arg in call.args) {
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// code += translateExpression(arg, resultRegister, regUsage)
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// code += translateExpression(arg, resultRegister)
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// code += when(arg.type) {
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// in ByteDatatypes -> VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1=resultRegister))
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// in WordDatatypes -> VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1=resultRegister))
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@ -7,6 +7,23 @@ import prog8.code.core.*
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import prog8.vm.Instruction
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import java.lang.Math.pow
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import kotlin.math.pow
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internal class VmRegisterPool() {
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private var firstFree: Int=3 // registers 0,1,2 are reserved
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fun peekNext() = firstFree
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fun nextFree(): Int {
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val result = firstFree
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firstFree++
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if(firstFree>65535)
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throw AssemblyError("out of virtual registers")
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return result
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}
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}
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class CodeGen(internal val program: PtProgram,
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@ -18,6 +35,7 @@ class CodeGen(internal val program: PtProgram,
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internal val allocations = VariableAllocator(symbolTable, program, errors)
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private val expressionEval = ExpressionGen(this)
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private val builtinFuncGen = BuiltinFuncGen(this, expressionEval)
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internal val vmRegisters = VmRegisterPool()
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init {
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if(options.dontReinitGlobals)
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@ -30,40 +48,39 @@ class CodeGen(internal val program: PtProgram,
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// collect global variables initializers
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program.allBlocks().forEach {
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val code = VmCodeChunk()
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it.children.filterIsInstance<PtAssignment>().forEach { assign -> code += translate(assign, RegisterUsage(0)) }
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it.children.filterIsInstance<PtAssignment>().forEach { assign -> code += translate(assign) }
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vmprog.addGlobalInits(code)
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}
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val regUsage = RegisterUsage(0)
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for (block in program.allBlocks()) {
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vmprog.addBlock(translate(block, regUsage))
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vmprog.addBlock(translate(block))
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}
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return vmprog
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}
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private fun translateNode(node: PtNode, regUsage: RegisterUsage): VmCodeChunk {
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private fun translateNode(node: PtNode): VmCodeChunk {
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val code = when(node) {
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is PtBlock -> translate(node, regUsage)
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is PtSub -> translate(node, regUsage)
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is PtBlock -> translate(node)
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is PtSub -> translate(node)
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is PtScopeVarsDecls -> VmCodeChunk() // vars should be looked up via symbol table
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is PtVariable -> VmCodeChunk() // var should be looked up via symbol table
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is PtMemMapped -> VmCodeChunk() // memmapped var should be looked up via symbol table
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is PtConstant -> VmCodeChunk() // constants have all been folded into the code
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is PtAssignment -> translate(node, regUsage)
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is PtNodeGroup -> translateGroup(node.children, regUsage)
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is PtBuiltinFunctionCall -> translateBuiltinFunc(node, regUsage.nextFree(), regUsage)
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is PtFunctionCall -> expressionEval.translate(node, regUsage.nextFree(), regUsage)
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is PtAssignment -> translate(node)
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is PtNodeGroup -> translateGroup(node.children)
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is PtBuiltinFunctionCall -> translateBuiltinFunc(node, 0)
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is PtFunctionCall -> expressionEval.translate(node, 0)
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is PtNop -> VmCodeChunk()
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is PtReturn -> translate(node)
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is PtJump -> translate(node)
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is PtWhen -> TODO("when")
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is PtPipe -> expressionEval.translate(node, regUsage.nextFree(), regUsage)
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is PtForLoop -> translate(node, regUsage)
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is PtIfElse -> translate(node, regUsage)
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is PtPostIncrDecr -> translate(node, regUsage)
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is PtRepeatLoop -> translate(node, regUsage)
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is PtPipe -> expressionEval.translate(node, 0)
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is PtForLoop -> translate(node)
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is PtIfElse -> translate(node)
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is PtPostIncrDecr -> translate(node)
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is PtRepeatLoop -> translate(node)
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is PtLabel -> VmCodeChunk(VmCodeLabel(node.scopedName))
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is PtBreakpoint -> VmCodeChunk(VmCodeInstruction(Instruction(Opcode.BREAKPOINT)))
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is PtAddressOf,
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@ -88,35 +105,113 @@ class CodeGen(internal val program: PtProgram,
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is PtConditionalBranch -> throw AssemblyError("conditional branches not supported in vm target due to lack of cpu flags ${node.position}")
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else -> TODO("missing codegen for $node")
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}
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code.lines.add(0, VmCodeComment(node.position.toString()))
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if(code.lines.isNotEmpty())
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code.lines.add(0, VmCodeComment(node.position.toString()))
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return code
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}
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private fun translate(forLoop: PtForLoop, regUsage: RegisterUsage): VmCodeChunk {
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private fun translate(forLoop: PtForLoop): VmCodeChunk {
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val loopvar = symbolTable.lookup(forLoop.variable.targetName) as StStaticVariable
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val iterable = forLoop.iterable
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val code = VmCodeChunk()
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when(iterable) {
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is PtRange -> {
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println("forloop ${loopvar.dt} ${loopvar.scopedName} in range ${iterable} ")
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TODO("forloop ${loopvar.dt} ${loopvar.scopedName} in range ${iterable} ")
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iterable.printIndented(0)
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TODO()
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TODO("forloop over range")
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}
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is PtIdentifier -> {
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val address = allocations.get(iterable.targetName)
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val variable = symbolTable.lookup(iterable.targetName) as StStaticVariable
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val length = variable.length!!
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println("forloop ${loopvar.dt} ${loopvar.scopedName} in $iterable @${address.toHex()} ${length}")
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val indexReg = regUsage.nextFree()
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val loopvarReg = regUsage.nextFree()
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TODO()
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val arrayAddress = allocations.get(iterable.targetName)
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val iterableVar = symbolTable.lookup(iterable.targetName) as StStaticVariable
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val loopvarAddress = allocations.get(loopvar.scopedName)
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val indexReg = vmRegisters.nextFree()
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val loopLabel = createLabelName()
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val endLabel = createLabelName()
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if(iterableVar.dt==DataType.STR) {
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// iterate over a zero-terminated string
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code += VmCodeInstruction(Instruction(Opcode.LOAD, VmDataType.BYTE, reg1=indexReg, value=0))
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code += VmCodeLabel(loopLabel)
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code += VmCodeInstruction(Instruction(Opcode.LOADX, VmDataType.BYTE, reg1=0, reg2=indexReg, value = arrayAddress))
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code += VmCodeInstruction(Instruction(Opcode.BZ, VmDataType.BYTE, reg1=0, symbol = endLabel))
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code += VmCodeInstruction(Instruction(Opcode.STOREM, VmDataType.BYTE, reg1=0, value = loopvarAddress))
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code += translateNode(forLoop.statements)
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code += VmCodeInstruction(Instruction(Opcode.INC, VmDataType.BYTE, reg1=indexReg))
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code += VmCodeInstruction(Instruction(Opcode.JUMP, symbol = loopLabel))
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code += VmCodeLabel(endLabel)
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} else {
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// iterate over array
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val elementDt = ArrayToElementTypes.getValue(iterable.type)
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val elementSize = program.memsizer.memorySize(elementDt).toUInt()
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val lengthBytes = iterableVar.length!! * elementSize.toInt()
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val lengthReg = vmRegisters.nextFree()
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/*
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index = 0
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_loop:
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if index==(length * <element_size>) goto _end
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loopvar = read_mem(iterable+index)
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<statements>
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index += <elementsize>
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goto _loop
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_end: ...
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*/
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code += VmCodeInstruction(Instruction(Opcode.LOAD, VmDataType.BYTE, reg1=indexReg, value=0))
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code += VmCodeInstruction(Instruction(Opcode.LOAD, VmDataType.BYTE, reg1=lengthReg, value=lengthBytes))
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code += VmCodeLabel(loopLabel)
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code += VmCodeInstruction(Instruction(Opcode.BEQ, VmDataType.BYTE, reg1=indexReg, reg2=lengthReg, symbol = endLabel))
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code += VmCodeInstruction(Instruction(Opcode.LOADX, vmType(elementDt), reg1=0, reg2=indexReg, value=arrayAddress))
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code += VmCodeInstruction(Instruction(Opcode.STOREM, vmType(elementDt), reg1=0, value = loopvarAddress))
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code += translateNode(forLoop.statements)
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code += addConst(VmDataType.BYTE, indexReg, elementSize)
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code += VmCodeInstruction(Instruction(Opcode.JUMP, symbol = loopLabel))
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code += VmCodeLabel(endLabel)
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}
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}
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else -> throw AssemblyError("weird for iterable")
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}
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return code
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}
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private fun translate(ifElse: PtIfElse, regUsage: RegisterUsage): VmCodeChunk {
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private fun addConst(dt: VmDataType, reg: Int, value: UInt): VmCodeChunk {
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val code = VmCodeChunk()
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when(value) {
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0u -> { /* do nothing */ }
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1u -> {
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code += VmCodeInstruction(Instruction(Opcode.INC, dt, reg1=reg))
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}
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else -> {
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val valueReg = vmRegisters.nextFree()
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code += VmCodeInstruction(Instruction(Opcode.LOAD, dt, reg1=valueReg, value=value.toInt()))
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code += VmCodeInstruction(Instruction(Opcode.ADD, dt, reg1=reg, reg2=reg, reg3=valueReg))
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}
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}
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return code
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}
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private val powersOfTwo = (0..16).map { 2.0.pow(it.toDouble()).toInt() }
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private fun multiplyByConst(dt: VmDataType, reg: Int, factor: UInt): VmCodeChunk {
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val code = VmCodeChunk()
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val pow2 = powersOfTwo.indexOf(factor.toInt())
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if(pow2>=1) {
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// just shift bits
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code += VmCodeInstruction(Instruction(Opcode.LSL, dt, reg1=reg, reg2=reg, reg3=pow2))
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} else {
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when(factor) {
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0u -> {
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code += VmCodeInstruction(Instruction(Opcode.LOAD, dt, reg1=reg, value=0))
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}
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1u -> { /* do nothing */ }
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else -> {
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val factorReg = vmRegisters.nextFree()
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code += VmCodeInstruction(Instruction(Opcode.LOAD, dt, reg1=factorReg, value=factor.toInt()))
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code += VmCodeInstruction(Instruction(Opcode.MUL, dt, reg1=reg, reg2=reg, reg3=factorReg))
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}
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}
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}
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return code
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}
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private fun translate(ifElse: PtIfElse): VmCodeChunk {
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var branch = Opcode.BZ
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var condition = ifElse.condition
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@ -133,31 +228,31 @@ class CodeGen(internal val program: PtProgram,
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}
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}
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val conditionReg = regUsage.nextFree()
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val conditionReg = vmRegisters.nextFree()
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val vmDt = vmType(condition.type)
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val code = VmCodeChunk()
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code += expressionEval.translateExpression(condition, conditionReg, regUsage)
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code += expressionEval.translateExpression(condition, conditionReg)
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if(ifElse.elseScope.children.isNotEmpty()) {
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// if and else parts
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val elseLabel = createLabelName()
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val afterIfLabel = createLabelName()
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code += VmCodeInstruction(Instruction(branch, vmDt, reg1=conditionReg, symbol = elseLabel))
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code += translateNode(ifElse.ifScope, regUsage)
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code += translateNode(ifElse.ifScope)
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code += VmCodeInstruction(Instruction(Opcode.JUMP, symbol = afterIfLabel))
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code += VmCodeLabel(elseLabel)
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code += translateNode(ifElse.elseScope, regUsage)
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code += translateNode(ifElse.elseScope)
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code += VmCodeLabel(afterIfLabel)
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} else {
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// only if part
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val afterIfLabel = createLabelName()
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code += VmCodeInstruction(Instruction(branch, vmDt, reg1=conditionReg, symbol = afterIfLabel))
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code += translateNode(ifElse.ifScope, regUsage)
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code += translateNode(ifElse.ifScope)
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code += VmCodeLabel(afterIfLabel)
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}
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return code
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}
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private fun translate(postIncrDecr: PtPostIncrDecr, regUsage: RegisterUsage): VmCodeChunk {
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private fun translate(postIncrDecr: PtPostIncrDecr): VmCodeChunk {
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val code = VmCodeChunk()
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val operation = when(postIncrDecr.operator) {
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"++" -> Opcode.INC
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@ -168,15 +263,15 @@ class CodeGen(internal val program: PtProgram,
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val memory = postIncrDecr.target.memory
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val array = postIncrDecr.target.array
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val vmDt = vmType(postIncrDecr.target.type)
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val resultReg = regUsage.nextFree()
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val resultReg = vmRegisters.nextFree()
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if(ident!=null) {
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val address = allocations.get(ident.targetName)
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code += VmCodeInstruction(Instruction(Opcode.LOADM, vmDt, reg1=resultReg, value = address))
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code += VmCodeInstruction(Instruction(operation, vmDt, reg1=resultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.STOREM, vmDt, reg1=resultReg, value = address))
|
||||
} else if(memory!=null) {
|
||||
val addressReg = regUsage.nextFree()
|
||||
code += expressionEval.translateExpression(memory.address, addressReg, regUsage)
|
||||
val addressReg = vmRegisters.nextFree()
|
||||
code += expressionEval.translateExpression(memory.address, addressReg)
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOADI, vmDt, reg1=resultReg, reg2=addressReg))
|
||||
code += VmCodeInstruction(Instruction(operation, vmDt, reg1=resultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg))
|
||||
@ -188,23 +283,23 @@ class CodeGen(internal val program: PtProgram,
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(repeat: PtRepeatLoop, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(repeat: PtRepeatLoop): VmCodeChunk {
|
||||
if((repeat.count as? PtNumber)?.number==0.0)
|
||||
return VmCodeChunk()
|
||||
if((repeat.count as? PtNumber)?.number==1.0)
|
||||
return translateGroup(repeat.children, regUsage)
|
||||
return translateGroup(repeat.children)
|
||||
if((repeat.count as? PtNumber)?.number==256.0) {
|
||||
// 256 iterations can still be done with just a byte counter if you set it to zero as starting value.
|
||||
repeat.children[0] = PtNumber(DataType.UBYTE, 0.0, repeat.count.position)
|
||||
}
|
||||
|
||||
val code = VmCodeChunk()
|
||||
val counterReg = regUsage.nextFree()
|
||||
val counterReg = vmRegisters.nextFree()
|
||||
val vmDt = vmType(repeat.count.type)
|
||||
code += expressionEval.translateExpression(repeat.count, counterReg, regUsage)
|
||||
code += expressionEval.translateExpression(repeat.count, counterReg)
|
||||
val repeatLabel = createLabelName()
|
||||
code += VmCodeLabel(repeatLabel)
|
||||
code += translateNode(repeat.statements, regUsage)
|
||||
code += translateNode(repeat.statements)
|
||||
code += VmCodeInstruction(Instruction(Opcode.DEC, vmDt, reg1=counterReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.BNZ, vmDt, reg1=counterReg, symbol = repeatLabel))
|
||||
return code
|
||||
@ -223,18 +318,18 @@ class CodeGen(internal val program: PtProgram,
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translateGroup(group: List<PtNode>, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translateGroup(group: List<PtNode>): VmCodeChunk {
|
||||
val code = VmCodeChunk()
|
||||
group.forEach { code += translateNode(it, regUsage) }
|
||||
group.forEach { code += translateNode(it) }
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(assignment: PtAssignment, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(assignment: PtAssignment): VmCodeChunk {
|
||||
// TODO can in-place assignments (assignment.augmentable = true) be optimized more?
|
||||
|
||||
val code = VmCodeChunk()
|
||||
val resultRegister = regUsage.nextFree()
|
||||
code += expressionEval.translateExpression(assignment.value, resultRegister, regUsage)
|
||||
val resultRegister = vmRegisters.nextFree()
|
||||
code += expressionEval.translateExpression(assignment.value, resultRegister)
|
||||
val ident = assignment.target.identifier
|
||||
val memory = assignment.target.memory
|
||||
val array = assignment.target.array
|
||||
@ -252,11 +347,11 @@ class CodeGen(internal val program: PtProgram,
|
||||
val vmDtArrayIdx = vmType(array.type)
|
||||
if(fixedIndex!=null) {
|
||||
variableAddr += fixedIndex*itemsize
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOADM, vmDtArrayIdx, reg1 = resultRegister, value=variableAddr))
|
||||
code += VmCodeInstruction(Instruction(Opcode.STOREM, vmDtArrayIdx, reg1 = resultRegister, value=variableAddr))
|
||||
} else {
|
||||
val indexReg = regUsage.nextFree()
|
||||
code += expressionEval.translateExpression(array.index, indexReg, regUsage)
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOADX, vmDtArrayIdx, reg1 = resultRegister, reg2=indexReg, value=variableAddr))
|
||||
val indexReg = vmRegisters.nextFree()
|
||||
code += expressionEval.translateExpression(array.index, indexReg)
|
||||
code += VmCodeInstruction(Instruction(Opcode.STOREX, vmDtArrayIdx, reg1 = resultRegister, reg2=indexReg, value=variableAddr))
|
||||
}
|
||||
}
|
||||
else if(memory!=null) {
|
||||
@ -264,8 +359,8 @@ class CodeGen(internal val program: PtProgram,
|
||||
if(memory.address is PtNumber) {
|
||||
Instruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=(memory.address as PtNumber).number.toInt())
|
||||
} else {
|
||||
val addressRegister = regUsage.nextFree()
|
||||
code += expressionEval.translateExpression(assignment.value, addressRegister, regUsage)
|
||||
val addressRegister = vmRegisters.nextFree()
|
||||
code += expressionEval.translateExpression(assignment.value, addressRegister)
|
||||
Instruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressRegister)
|
||||
}
|
||||
code += VmCodeInstruction(ins)
|
||||
@ -280,30 +375,30 @@ class CodeGen(internal val program: PtProgram,
|
||||
val value = ret.value
|
||||
if(value!=null) {
|
||||
// Call Convention: return value is always returned in r0
|
||||
code += expressionEval.translateExpression(value, 0, RegisterUsage(1))
|
||||
code += expressionEval.translateExpression(value, 0)
|
||||
}
|
||||
code += VmCodeInstruction(Instruction(Opcode.RETURN))
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(sub: PtSub, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(sub: PtSub): VmCodeChunk {
|
||||
// TODO actually inline subroutines marked as inline
|
||||
val code = VmCodeChunk()
|
||||
code += VmCodeComment("SUB: ${sub.scopedName} -> ${sub.returntype}")
|
||||
code += VmCodeLabel(sub.scopedName)
|
||||
for (child in sub.children) {
|
||||
code += translateNode(child, regUsage)
|
||||
code += translateNode(child)
|
||||
}
|
||||
code += VmCodeComment("SUB-END '${sub.name}'")
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(block: PtBlock, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(block: PtBlock): VmCodeChunk {
|
||||
val code = VmCodeChunk()
|
||||
code += VmCodeComment("BLOCK '${block.name}' addr=${block.address} lib=${block.library}")
|
||||
for (child in block.children) {
|
||||
if(child !is PtAssignment) // global variable initialization is done elsewhere
|
||||
code += translateNode(child, regUsage)
|
||||
code += translateNode(child)
|
||||
}
|
||||
code += VmCodeComment("BLOCK-END '${block.name}'")
|
||||
return code
|
||||
@ -327,6 +422,6 @@ class CodeGen(internal val program: PtProgram,
|
||||
return listOf("generated$labelSequenceNumber")
|
||||
}
|
||||
|
||||
internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk =
|
||||
builtinFuncGen.translate(call, resultRegister, regUsage)
|
||||
internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk =
|
||||
builtinFuncGen.translate(call, resultRegister)
|
||||
}
|
||||
|
||||
@ -12,18 +12,9 @@ import prog8.vm.Opcode
|
||||
import prog8.vm.VmDataType
|
||||
|
||||
|
||||
internal class RegisterUsage(var firstFree: Int=0) {
|
||||
fun nextFree(): Int {
|
||||
val result = firstFree
|
||||
firstFree++
|
||||
return result
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
fun translateExpression(expr: PtExpression, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
require(regUsage.firstFree > resultRegister)
|
||||
internal class ExpressionGen(private val codeGen: CodeGen) {
|
||||
fun translateExpression(expr: PtExpression, resultRegister: Int): VmCodeChunk {
|
||||
require(codeGen.vmRegisters.peekNext() > resultRegister)
|
||||
|
||||
val code = VmCodeChunk()
|
||||
val vmDt = codeGen.vmType(expr.type)
|
||||
@ -46,18 +37,18 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=mem))
|
||||
}
|
||||
is PtMemoryByte -> {
|
||||
val addressRegister = regUsage.nextFree()
|
||||
val addressExprCode = translateExpression(expr.address, addressRegister, regUsage)
|
||||
val addressRegister = codeGen.vmRegisters.nextFree()
|
||||
val addressExprCode = translateExpression(expr.address, addressRegister)
|
||||
code += addressExprCode
|
||||
}
|
||||
is PtTypeCast -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtPrefix -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtArrayIndexer -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtBinaryExpression -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtBuiltinFunctionCall -> code += codeGen.translateBuiltinFunc(expr, resultRegister, regUsage)
|
||||
is PtFunctionCall -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtContainmentCheck -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtPipe -> code += translate(expr, resultRegister, regUsage)
|
||||
is PtTypeCast -> code += translate(expr, resultRegister)
|
||||
is PtPrefix -> code += translate(expr, resultRegister)
|
||||
is PtArrayIndexer -> code += translate(expr, resultRegister)
|
||||
is PtBinaryExpression -> code += translate(expr, resultRegister)
|
||||
is PtBuiltinFunctionCall -> code += codeGen.translateBuiltinFunc(expr, resultRegister)
|
||||
is PtFunctionCall -> code += translate(expr, resultRegister)
|
||||
is PtContainmentCheck -> code += translate(expr, resultRegister)
|
||||
is PtPipe -> code += translate(expr, resultRegister)
|
||||
is PtRange,
|
||||
is PtArray,
|
||||
is PtString -> throw AssemblyError("range/arrayliteral/string should no longer occur as expression")
|
||||
@ -66,34 +57,34 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
return code
|
||||
}
|
||||
|
||||
internal fun translate(pipe: PtPipe, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
internal fun translate(pipe: PtPipe, resultRegister: Int): VmCodeChunk {
|
||||
TODO("Not yet implemented: pipe expression")
|
||||
}
|
||||
|
||||
private fun translate(check: PtContainmentCheck, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(check: PtContainmentCheck, resultRegister: Int): VmCodeChunk {
|
||||
val code = VmCodeChunk()
|
||||
code += translateExpression(check.element, resultRegister, regUsage) // load the element to check in resultRegister
|
||||
code += translateExpression(check.element, resultRegister) // load the element to check in resultRegister
|
||||
val iterable = codeGen.symbolTable.flat.getValue(check.iterable.targetName) as StStaticVariable
|
||||
when(iterable.dt) {
|
||||
DataType.STR -> {
|
||||
val call = PtFunctionCall(listOf("prog8_lib", "string_contains"), false, DataType.UBYTE, check.position)
|
||||
call.children.add(check.element)
|
||||
call.children.add(check.iterable)
|
||||
code += translate(call, resultRegister, regUsage)
|
||||
code += translate(call, resultRegister)
|
||||
}
|
||||
DataType.ARRAY_UB, DataType.ARRAY_B -> {
|
||||
val call = PtFunctionCall(listOf("prog8_lib", "bytearray_contains"), false, DataType.UBYTE, check.position)
|
||||
call.children.add(check.element)
|
||||
call.children.add(check.iterable)
|
||||
call.children.add(PtNumber(DataType.UBYTE, iterable.length!!.toDouble(), iterable.position))
|
||||
code += translate(call, resultRegister, regUsage)
|
||||
code += translate(call, resultRegister)
|
||||
}
|
||||
DataType.ARRAY_UW, DataType.ARRAY_W -> {
|
||||
val call = PtFunctionCall(listOf("prog8_lib", "wordarray_contains"), false, DataType.UBYTE, check.position)
|
||||
call.children.add(check.element)
|
||||
call.children.add(check.iterable)
|
||||
call.children.add(PtNumber(DataType.UBYTE, iterable.length!!.toDouble(), iterable.position))
|
||||
code += translate(call, resultRegister, regUsage)
|
||||
code += translate(call, resultRegister)
|
||||
}
|
||||
DataType.ARRAY_F -> TODO("containment check in float-array")
|
||||
else -> throw AssemblyError("weird iterable dt ${iterable.dt} for ${check.iterable.targetName}")
|
||||
@ -101,14 +92,14 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(arrayIx: PtArrayIndexer, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(arrayIx: PtArrayIndexer, resultRegister: Int): VmCodeChunk {
|
||||
val eltSize = codeGen.program.memsizer.memorySize(arrayIx.type)
|
||||
val vmDt = codeGen.vmType(arrayIx.type)
|
||||
val code = VmCodeChunk()
|
||||
val idxReg = regUsage.nextFree()
|
||||
code += translateExpression(arrayIx.index, idxReg, regUsage)
|
||||
val idxReg = codeGen.vmRegisters.nextFree()
|
||||
code += translateExpression(arrayIx.index, idxReg)
|
||||
if(eltSize>1) {
|
||||
val factorReg = regUsage.nextFree()
|
||||
val factorReg = codeGen.vmRegisters.nextFree()
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize))
|
||||
code += VmCodeInstruction(Instruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=factorReg))
|
||||
}
|
||||
@ -117,9 +108,9 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(expr: PtPrefix, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(expr: PtPrefix, resultRegister: Int): VmCodeChunk {
|
||||
val code = VmCodeChunk()
|
||||
code += translateExpression(expr.value, resultRegister, regUsage)
|
||||
code += translateExpression(expr.value, resultRegister)
|
||||
val vmDt = codeGen.vmType(expr.type)
|
||||
when(expr.operator) {
|
||||
"+" -> { }
|
||||
@ -127,7 +118,7 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
code += VmCodeInstruction(Instruction(Opcode.NEG, vmDt, reg1=resultRegister))
|
||||
}
|
||||
"~" -> {
|
||||
val regMask = regUsage.nextFree()
|
||||
val regMask = codeGen.vmRegisters.nextFree()
|
||||
val mask = if(vmDt==VmDataType.BYTE) 0x00ff else 0xffff
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=regMask, value=mask))
|
||||
code += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=regMask))
|
||||
@ -137,7 +128,7 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
code += VmCodeInstruction(Instruction(Opcode.BZ, vmDt, reg1=resultRegister, symbol = label))
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=1))
|
||||
code += VmCodeLabel(label)
|
||||
val regMask = regUsage.nextFree()
|
||||
val regMask = codeGen.vmRegisters.nextFree()
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=regMask, value=1))
|
||||
code += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=regMask))
|
||||
}
|
||||
@ -146,11 +137,11 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(cast: PtTypeCast, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(cast: PtTypeCast, resultRegister: Int): VmCodeChunk {
|
||||
val code = VmCodeChunk()
|
||||
if(cast.type==cast.value.type)
|
||||
return code
|
||||
code += translateExpression(cast.value, resultRegister, regUsage)
|
||||
code += translateExpression(cast.value, resultRegister)
|
||||
when(cast.type) {
|
||||
DataType.UBYTE -> {
|
||||
when(cast.value.type) {
|
||||
@ -223,14 +214,14 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(binExpr: PtBinaryExpression, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
private fun translate(binExpr: PtBinaryExpression, resultRegister: Int): VmCodeChunk {
|
||||
val code = VmCodeChunk()
|
||||
val leftResultReg = regUsage.nextFree()
|
||||
val rightResultReg = regUsage.nextFree()
|
||||
val leftResultReg = codeGen.vmRegisters.nextFree()
|
||||
val rightResultReg = codeGen.vmRegisters.nextFree()
|
||||
// TODO: optimized codegen when left or right operand is known 0 or 1 or whatever. But only if this would result in a different opcode such as ADD 1 -> INC, MUL 1 -> NOP
|
||||
// actually optimizing the code should not be done here but in a tailored code optimizer step.
|
||||
val leftCode = translateExpression(binExpr.left, leftResultReg, regUsage)
|
||||
val rightCode = translateExpression(binExpr.right, rightResultReg, regUsage)
|
||||
val leftCode = translateExpression(binExpr.left, leftResultReg)
|
||||
val rightCode = translateExpression(binExpr.right, rightResultReg)
|
||||
code += leftCode
|
||||
code += rightCode
|
||||
val vmDt = codeGen.vmType(binExpr.left.type)
|
||||
@ -294,12 +285,12 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
return code
|
||||
}
|
||||
|
||||
fun translate(fcall: PtFunctionCall, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
fun translate(fcall: PtFunctionCall, resultRegister: Int): VmCodeChunk {
|
||||
val subroutine = codeGen.symbolTable.flat.getValue(fcall.functionName) as StSub
|
||||
val code = VmCodeChunk()
|
||||
for ((arg, parameter) in fcall.args.zip(subroutine.parameters)) {
|
||||
val argReg = regUsage.nextFree()
|
||||
code += translateExpression(arg, argReg, regUsage)
|
||||
val argReg = codeGen.vmRegisters.nextFree()
|
||||
code += translateExpression(arg, argReg)
|
||||
val vmDt = codeGen.vmType(parameter.type)
|
||||
val mem = codeGen.allocations.get(fcall.functionName + parameter.name)
|
||||
code += VmCodeInstruction(Instruction(Opcode.STOREM, vmDt, reg1=argReg, value=mem))
|
||||
|
||||
@ -3,7 +3,7 @@ TODO
|
||||
|
||||
For next release
|
||||
^^^^^^^^^^^^^^^^
|
||||
- vm codegen: fix primes endless loop stuck on '2'
|
||||
- vm: memory: reading/writing of words seems buggy. add tests+fix
|
||||
- x16: check additional FP lib changes https://github.com/commanderx16/x16-rom/commit/ae608673f0210953172d6837acfbb231d62ddbd1
|
||||
and https://github.com/commanderx16/x16-docs/commit/21238aedc641da91df88e04c4ce9bf3324a3c12d
|
||||
- x16: check joystick support (petaxian, own stuff) because of api change in r39 kernal https://github.com/commanderx16/x16-docs/blob/master/Commander%20X16%20Programmer's%20Reference%20Guide.md#function-name-joystick_get
|
||||
|
||||
@ -4,39 +4,35 @@
|
||||
|
||||
main {
|
||||
sub start() {
|
||||
ubyte x1 = $ea
|
||||
ubyte x2 = $31
|
||||
uword uw = mkword(x1, $99)
|
||||
txt.print_uwhex(uw, true)
|
||||
txt.nl()
|
||||
uw = mkword(x1, x2)
|
||||
txt.print_uwhex(uw, true)
|
||||
txt.clear_screen()
|
||||
txt.print("Welcome to a prog8 pixel shader :-)\n")
|
||||
uword ww = 0
|
||||
ubyte bc
|
||||
uword wc
|
||||
|
||||
for bc in "irmen" {
|
||||
txt.chrout(bc)
|
||||
ww++
|
||||
}
|
||||
txt.print_uw(ww) ; 5
|
||||
txt.nl()
|
||||
|
||||
sys.exit(99)
|
||||
for bc in [10,11,12] {
|
||||
txt.print_ub(bc)
|
||||
txt.spc()
|
||||
ww++
|
||||
}
|
||||
txt.print_uw(ww) ; 8
|
||||
txt.nl()
|
||||
|
||||
for wc in [4096,8192,16384] {
|
||||
txt.print_uw(wc)
|
||||
txt.spc()
|
||||
ww++
|
||||
}
|
||||
txt.print_uw(ww) ; 11
|
||||
txt.nl()
|
||||
|
||||
; txt.clear_screen()
|
||||
; txt.print("Welcome to a prog8 pixel shader :-)\n")
|
||||
; uword ww = 0
|
||||
; ubyte bc
|
||||
; uword wc
|
||||
;
|
||||
; for bc in "irmen" {
|
||||
; ; +5 -> 17
|
||||
; txt.chrout(bc)
|
||||
; ww++
|
||||
; }
|
||||
; txt.print_uw(ww)
|
||||
; txt.nl()
|
||||
;
|
||||
; for wc in [1000,1111,1222] {
|
||||
; txt.print_uw(wc)
|
||||
; txt.spc()
|
||||
; ww++ ; +3 -> 20
|
||||
; }
|
||||
; txt.print_uw(ww)
|
||||
; txt.nl()
|
||||
;
|
||||
; for bc in 10 to 20 step 3 {
|
||||
; ; 10,13,16,19 -> 4
|
||||
; ww++
|
||||
@ -50,8 +46,8 @@ main {
|
||||
; txt.print_uw(ww)
|
||||
; txt.nl()
|
||||
;
|
||||
;
|
||||
; sys.exit(99)
|
||||
|
||||
sys.exit(99)
|
||||
|
||||
|
||||
; the "pixelshader":
|
||||
|
||||
@ -27,22 +27,22 @@ class Memory {
|
||||
}
|
||||
|
||||
fun getUW(address: Int): UShort {
|
||||
return (256u*mem[address] + mem[address+1]).toUShort()
|
||||
return (256u*mem[address+1] + mem[address]).toUShort()
|
||||
}
|
||||
|
||||
fun getSW(address: Int): Short {
|
||||
return (mem[address].toInt()*256 + mem[address+1].toInt()).toShort()
|
||||
return (mem[address+1].toInt()*256 + mem[address].toInt()).toShort()
|
||||
}
|
||||
|
||||
fun setUW(address: Int, value: UShort) {
|
||||
mem[address] = (value.toInt() ushr 8).toUByte()
|
||||
mem[address+1] = value.toUByte()
|
||||
mem[address+1] = (value.toInt() ushr 8).toUByte()
|
||||
mem[address] = value.toUByte()
|
||||
}
|
||||
|
||||
fun setSW(address: Int, value: Short) {
|
||||
val uv = value.toUShort()
|
||||
mem[address] = (uv.toInt() ushr 8).toUByte()
|
||||
mem[address+1] = uv.toUByte()
|
||||
mem[address+1] = (uv.toInt() ushr 8).toUByte()
|
||||
mem[address] = uv.toUByte()
|
||||
}
|
||||
|
||||
// for now, no LONG 32-bits and no FLOAT support.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user