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qasm
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fixed a few bugs, got more tests to pass, added some parms.json options

This commit is contained in:
Shawn Quick 2023-02-05 21:38:02 -08:00
parent 2f79abe461
commit 6e9eb6cfcc
23 changed files with 2547 additions and 2289 deletions
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11
.gitignore vendored
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@ -1,3 +1,14 @@
**/build **/build
**/testdata1
*.bin
*.BIN
*.a
*.so
Finder.Data
test.s
disk_commands.txt
.vscode/browse*
.vscode/book*
*.xcuserstate *.xcuserstate
*.xcbkptlist *.xcbkptlist

4314
asm.cpp
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File diff suppressed because it is too large Load Diff

28
asm.h
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@ -15,6 +15,8 @@
#define SYNTAX_MPW 0x08 #define SYNTAX_MPW 0x08
#define SYNTAX_ORCA 0x10 #define SYNTAX_ORCA 0x10
#define SYNTAX_CC65 0x20 #define SYNTAX_CC65 0x20
#define SYNTAX_LISA 0x40
#define SYNTAX_QASM (0x80 | SYNTAX_MERLIN) #define SYNTAX_QASM (0x80 | SYNTAX_MERLIN)
#define OPTION_ALLOW_A_OPERAND 0x0100 #define OPTION_ALLOW_A_OPERAND 0x0100
#define OPTION_ALLOW_LOCAL 0x0200 #define OPTION_ALLOW_LOCAL 0x0200
@ -23,7 +25,7 @@
#define OPTION_NO_REPSEP 0x1000 #define OPTION_NO_REPSEP 0x1000
#define OPTION_CFG_REPSEP 0x2000 #define OPTION_CFG_REPSEP 0x2000
#define OPTION_M32_VARS 0x4000 #define OPTION_M32_VARS 0x4000
#define OPTION_M16_PLUS 0x8000
#define FLAG_FORCELONG 0x01 #define FLAG_FORCELONG 0x01
#define FLAG_FORCEABS 0x02 #define FLAG_FORCEABS 0x02
@ -201,6 +203,7 @@ public:
std::string printoperand; std::string printoperand;
std::string opcode; std::string opcode;
std::string opcodelower; std::string opcodelower;
std::string orig_operand;
std::string operand; std::string operand;
std::string operand_expr; std::string operand_expr;
std::string operand_expr2; std::string operand_expr2;
@ -254,6 +257,7 @@ protected:
public: public:
uint32_t errorct; uint32_t errorct;
std::string filename; std::string filename;
uint32_t format_flags;
TFileProcessor(); TFileProcessor();
virtual ~TFileProcessor(); virtual ~TFileProcessor();
@ -267,18 +271,18 @@ public:
virtual void setSyntax(uint32_t syn); virtual void setSyntax(uint32_t syn);
}; };
class TImageProcessor : public TFileProcessor
{
protected:
std::vector<MerlinLine> lines;
public: #define CONVERT_NONE 0x00
TImageProcessor(); #define CONVERT_LF 0x01
virtual ~TImageProcessor(); #define CONVERT_CRLF 0x02
virtual int doline(int lineno, std::string line); #define CONVERT_COMPRESS 0x04
virtual void process(void); #define CONVERT_HIGH 0x08
virtual void complete(void); #define CONVERT_MERLIN (CONVERT_HIGH|CONVERT_COMPRESS)
}; #define CONVERT_LINUX (CONVERT_LF)
#define CONVERT_WINDOWS (CONVERT_CRLF)
#define CONVERT_APW (CONVERT_NONE)
#define CONVERT_MPW (CONVERT_NONE)
#define CONVERT_TEST (CONVERT_COMPRESS|CONVERT_LF)
class TMerlinConverter : public TFileProcessor class TMerlinConverter : public TFileProcessor
{ {

92
cider.cpp
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@ -1,3 +1,5 @@
#ifdef CIDERPRESS
#include "asm.h" #include "asm.h"
#include "eval.h" #include "eval.h"
#include "psuedo.h" #include "psuedo.h"
@ -7,6 +9,9 @@
#include <cider.h> #include <cider.h>
#include <DiskImg.h> #include <DiskImg.h>
#include <util.h>
#undef CLASS
#define CLASS CiderPress #define CLASS CiderPress
using namespace DiskImgLib; using namespace DiskImgLib;
@ -14,49 +19,76 @@ using DiskImgLib::DiskImg;
void dbgMessage(const char *file, int line, const char *msg) void dbgMessage(const char *file, int line, const char *msg)
{ {
if (isDebug()>0)
printf("DEBUG: %s\n",msg); {
printf("DEBUG: %s\n",msg);
}
} }
CLASS::CLASS() CLASS::CLASS() : TFileProcessor()
{ {
if (!Global::GetAppInitCalled()) if (!Global::GetAppInitCalled())
{ {
DiskImgLib::Global::SetDebugMsgHandler(dbgMessage); DiskImgLib::Global::SetDebugMsgHandler(dbgMessage);
DiskImgLib::Global::AppInit(); DiskImgLib::Global::AppInit();
} }
}
CLASS::~CLASS()
{
} }
int CLASS::RunScript(string path) int CLASS::RunScript(string path)
{ {
int res=-1; int res=-1;
return(res);
return(res);
} }
int CLASS::CreateVolume(string OSName, string VolName, uint64_t size, CIDER_VOLFORMAT format) int CLASS::CreateVolume(string OSName, string VolName, uint64_t size, CIDER_VOLFORMAT format)
{ {
int interr=-1; int interr=-1;
DIError err; DIError err;
DiskImg *img=new DiskImg(); DiskImg *img=new DiskImg();
if (format==CP_PRODOS) if (format==CP_PRODOS)
{ {
err=img->CreateImage(OSName.c_str(),VolName.c_str(), err=img->CreateImage(OSName.c_str(),VolName.c_str(),
DiskImg::kOuterFormatNone, DiskImg::kOuterFormatNone,
DiskImg::kFileFormat2MG, DiskImg::kFileFormat2MG,
DiskImg::kPhysicalFormatSectors, DiskImg::kPhysicalFormatSectors,
NULL, NULL,
DiskImg::kSectorOrderProDOS, DiskImg::kSectorOrderProDOS,
DiskImg::kFormatGenericProDOSOrd, DiskImg::kFormatGenericProDOSOrd,
size/256, size/256,
false false
); );
printf("create error: %d\n",err); printf("create error: %d\n",err);
if (err== kDIErrNone ) if (err== kDIErrNone )
interr=0; {
} interr=0;
return (interr); }
}
return (interr);
} }
int CLASS::doline(int lineno, std::string line)
{
printf("%05d: %s\n",lineno,line.c_str());
return(0);
}
void CLASS::process(void)
{
}
void CLASS::complete(void)
{
}
#undef CLASS
#endif

22
cider.h
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@ -1,3 +1,4 @@
#ifdef CIDERPRESS
#pragma once #pragma once
#include "asm.h" #include "asm.h"
@ -10,13 +11,20 @@
#define CLASS CiderPress #define CLASS CiderPress
enum CIDER_VOLFORMAT {CP_PRODOS,CP_HFS}; enum CIDER_VOLFORMAT {CP_PRODOS,CP_HFS};
class CLASS class CLASS : public TFileProcessor
{ {
public: protected:
CLASS(); std::vector<MerlinLine> lines;
int CreateVolume(string OSName, string VolName, uint64_t size, CIDER_VOLFORMAT format); public:
int RunScript(string path); CLASS();
virtual ~CLASS();
int CreateVolume(string OSName, string VolName, uint64_t size, CIDER_VOLFORMAT format);
int RunScript(string path);
virtual int doline(int lineno, std::string line);
virtual void process(void);
virtual void complete(void);
}; };
#undef CLASS #undef CLASS
#endif

2
eval.cpp
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@ -607,7 +607,7 @@ int CLASS::evaluate(std::string & e, int64_t &res, uint8_t &_shiftmode)
std::string expr = Poco::trim(e); std::string expr = Poco::trim(e);
expr += " "; // add a space at end to make parsing easier expr += " "; // add a space at end to make parsing easier
if (isDebug() >= 4) if (isDebug() >= 1)
{ {
printf("eval: expression: |%s|\n", expr.c_str()); printf("eval: expression: |%s|\n", expr.c_str());
} }

4
merlintests.sh
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@ -22,7 +22,9 @@ for S in $SRC ; do
S1=${S1/.s/} S1=${S1/.s/}
cd ./testdata cd ./testdata
merlin32$X . $S 2>/dev/null >/dev/null #merlin32$X . $S 2>/dev/null >/dev/null
merlin32$X -V . $S
#merlin32 . $S 2>/dev/null #merlin32 . $S 2>/dev/null
R=?$ R=?$

5
opcodes.cpp
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@ -12,6 +12,7 @@ void CLASS::setOpcode(MerlinLine &line, uint8_t op)
uint8_t m = opCodeCompatibility[op]; uint8_t m = opCodeCompatibility[op];
if ((m > 0) && (cpumode < MODE_65C02)) // if the instruction is non-zero, and we are in 6502 base mode, error if ((m > 0) && (cpumode < MODE_65C02)) // if the instruction is non-zero, and we are in 6502 base mode, error
{ {
//printf("incompatable: %02X %02X\n",op,m);
if (line.errorcode == 0) // don't replace other errors if (line.errorcode == 0) // don't replace other errors
{ {
line.setError(errIncompatibleOpcode); line.setError(errIncompatibleOpcode);
@ -706,7 +707,8 @@ int CLASS::doBase6502(MerlinLine & line, TSymbol & sym)
if (err) // not a 6502 address mode if (err) // not a 6502 address mode
{ {
if (cpumode >= MODE_65816) //if (cpumode >= MODE_65816)
if (cpumode >= MODE_65C02)
{ {
cc = 0x03; cc = 0x03;
err = false; err = false;
@ -950,6 +952,7 @@ void CLASS::insertOpcodes(void)
pushopcode("MVP", 0x01, 0, OPHANDLER(&CLASS::doMVN)); pushopcode("MVP", 0x01, 0, OPHANDLER(&CLASS::doMVN));
pushopcode("NOP", 0xEA, 0, OPHANDLER(&CLASS::doBYTE)); pushopcode("NOP", 0xEA, 0, OPHANDLER(&CLASS::doBYTE));
pushopcode("ORA", 0x00, OP_STD | OP_A, OPHANDLER(&CLASS::doBase6502)); pushopcode("ORA", 0x00, OP_STD | OP_A, OPHANDLER(&CLASS::doBase6502));
pushopcode("PEA", 0xF4, 2, OPHANDLER(&CLASS::doAddress)); pushopcode("PEA", 0xF4, 2, OPHANDLER(&CLASS::doAddress));
pushopcode("PEI", 0xD4, 1, OPHANDLER(&CLASS::doAddress)); pushopcode("PEI", 0xD4, 1, OPHANDLER(&CLASS::doAddress));
pushopcode("PER", 0x62, 2, OPHANDLER(&CLASS::doPER)); pushopcode("PER", 0x62, 2, OPHANDLER(&CLASS::doPER));

28
parms.json
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@ -1,6 +1,7 @@
{ {
"version": "1.1", "version": "1.1",
"general": { "general": {
"color_output": true,
"prefix": [ "prefix": [
{ {
"0": "${PWD}" "0": "${PWD}"
@ -16,16 +17,27 @@
} }
] ]
}, },
"assembler": { "asm": {
"cpu_default": "6502", "syntax": "merlin16plus", //merlin8, merlin16, merlin16plus,merlin32
"syntax": "merlin", "cpu": "M6502",
"listmode": "on" "startmx": 3,
"listmode": "on",
"casesend": true,
"lst": false,
"showmx": true,
"allowduplicate": true,
"trackrep": false,
"merlinerrors": true,
"m32vars": false,
"allowA": true,
"allowLocal": true,
"allowColon": true,
"repsep": "force", //force,no,cfg
"linebytes": 4,
"line2bytes": 8
}, },
"linker": {}, "linker": {},
"format": { "format": {
"tabs": "12,18,30" "tabs": "12,18,30,48"
},
"diskimg": {
"script": "./disk_commands.txt"
} }
} }

4
psuedo.cpp
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@ -944,6 +944,10 @@ int CLASS::doASC(T65816Asm &a, MerlinLine &line, TSymbol &opinfo)
if (dci && (i == lastdelimidx)) if (dci && (i == lastdelimidx))
{ {
// SGQ BUG - Merlin16+ does it like Merlin32 and now does the last
// byte not the way merlin816 and earlier do it documented below.
// use OPTION_M16_PLUS when implemented.
//lr - Merlin only toggles the high bit of string chars, not hex values //lr - Merlin only toggles the high bit of string chars, not hex values
// 8D,'Hello',8D,'there',8D becomes 8D 48 65 6C 6C 6F 8D 74 68 65 72 E5 // 8D,'Hello',8D,'there',8D becomes 8D 48 65 6C 6C 6F 8D 74 68 65 72 E5
// //

54
qasm.cpp
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@ -20,7 +20,7 @@ programOption PAL::appOptions[] =
{ "debug", "d", "enable debug info (repeat for more verbosity)", "", false, true}, { "debug", "d", "enable debug info (repeat for more verbosity)", "", false, true},
#endif #endif
//{ "config", "f", "load configuration data from a <file>", "<file>", false, false}, //{ "config", "f", "load configuration data from a <file>", "<file>", false, false},
{ "exec", "x", "execute a command [asm, link, reformat, script] default=asm", "<command>", false, false}, { "exec", "x", "execute a command [asm, link, format, script] default=asm", "<command>", false, false},
{ "objfile", "o", "write output to file", "<file>", false, false}, { "objfile", "o", "write output to file", "<file>", false, false},
{ "syntax", "s", "enforce syntax of other assembler [qasm, merlin, merlin32, ORCA, APW, MPW, CC65]", "<syntax>", false, false}, { "syntax", "s", "enforce syntax of other assembler [qasm, merlin, merlin32, ORCA, APW, MPW, CC65]", "<syntax>", false, false},
@ -101,7 +101,7 @@ int CLASS::runCommandLineApp(void)
syn=Poco::toUpper(syn); syn=Poco::toUpper(syn);
syn=Poco::trim(syn); syn=Poco::trim(syn);
syntax=SYNTAX_QASM; syntax=SYNTAX_QASM;
if ((syn=="MERLIN") || (syn=="MERLIN16") || (syn=="MERLIN8") || (syn=="MERLIN16+")) if ((syn=="MERLIN") || (syn=="MERLIN16") || (syn=="MERLIN8") || (syn=="MERLIN16PLUS"))
{ {
syntax=SYNTAX_MERLIN; syntax=SYNTAX_MERLIN;
} }
@ -130,7 +130,7 @@ int CLASS::runCommandLineApp(void)
syntax=SYNTAX_CC65; syntax=SYNTAX_CC65;
} }
printf("SYNTAX: |%s|\n",syn.c_str()); //printf("SYNTAX: |%s|\n",syn.c_str());
try try
{ {
@ -148,6 +148,7 @@ int CLASS::runCommandLineApp(void)
for (ArgVec::const_iterator it = commandargs.begin(); it != commandargs.end(); ++it) for (ArgVec::const_iterator it = commandargs.begin(); it != commandargs.end(); ++it)
{ {
int32_t format_flags=CONVERT_LINUX;
Poco::File fn(*it); Poco::File fn(*it);
int x; int x;
std::string p = fn.path(); std::string p = fn.path();
@ -158,10 +159,50 @@ int CLASS::runCommandLineApp(void)
std::string cmd = Poco::toUpper(getConfig("option.exec", "asm")); std::string cmd = Poco::toUpper(getConfig("option.exec", "asm"));
//printf("DEBUG=%d\n",isDebug()); Poco::StringTokenizer toks(cmd,"-");
if (toks.count()>1)
{
if (toks[0]=="FORMAT")
{
if (toks[1]=="LINUX")
{
format_flags=CONVERT_LINUX;
}
else if (toks[1]=="WINDOWS")
{
format_flags=CONVERT_WINDOWS;
}
else if (toks[1]=="MERLIN")
{
format_flags=CONVERT_MERLIN;
}
else if (toks[1]=="APW")
{
format_flags=CONVERT_APW;
}
else if (toks[1]=="MPW")
{
format_flags=CONVERT_MPW;
}
else if (toks[1]=="MAC")
{
format_flags=CONVERT_LINUX;
}
else if (toks[1]=="CC65")
{
format_flags=CONVERT_LINUX;
}
else if (toks[1]=="COMPRESS")
{
format_flags=CONVERT_TEST;
}
cmd=toks[0];
}
}
if (cmd.length() > 0) if (cmd.length() > 0)
{ {
if (cmd == "REFORMAT") if (cmd == "FORMAT")
{ {
res = 0; res = 0;
t = new TMerlinConverter(); t = new TMerlinConverter();
@ -171,6 +212,7 @@ int CLASS::runCommandLineApp(void)
{ {
t->init(); t->init();
t->setSyntax(syntax); t->setSyntax(syntax);
t->format_flags=format_flags;
std::string f = path.toString(); std::string f = path.toString();
t->filename = f; t->filename = f;
@ -233,7 +275,7 @@ int CLASS::runCommandLineApp(void)
else if (cmd == "SCRIPT") else if (cmd == "SCRIPT")
{ {
res = 0; res = 0;
t = new TImageProcessor(); t = new CiderPress();
if (t!=NULL) if (t!=NULL)
{ {
try try

4
testdata/1000-allops-value-65816.S vendored
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@ -2,6 +2,10 @@
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
xc off
xc
xc
mx %00
ZP EQU $FF ZP EQU $FF
ABS EQU $FEFF ABS EQU $FEFF
LONG EQU $FDFEFF LONG EQU $FDFEFF

4
testdata/1001-allops-zero-65816.S vendored
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@ -3,6 +3,10 @@
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
xc off
xc
xc
mx %00
ZP EQU $00 ZP EQU $00
ABS EQU $0000 ABS EQU $0000
LONG EQU $000000 LONG EQU $000000

196
testdata/1002-embedded-instructions.S vendored
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@ -1,110 +1,114 @@
; Copyright 2018 faddenSoft. All Rights Reserved. ; Copyright 2018 faddenSoft. All Rights Reserved.
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
org $1000 xc off
xc
xc
mx %11
org $1000
; 65816 mode with short regs ; 65816 mode with short regs
clc clc
xce xce
sep #$30 sep #$30
mx %11 mx %11
jsr test1 jsr test1
jsr test2 jsr test2
jsr test3 jsr test3
jsr test4 jsr test4
jsr test5 jsr test5
rts rts
; TEST #1: simple example ; TEST #1: simple example
test1 lda #$00 test1 lda #$00
dfb $2c ;BIT abs dfb $2c ;BIT abs
:inner lda #$01 :inner lda #$01
beq :inner beq :inner
rts rts
; TEST #2: embedded with break path ; TEST #2: embedded with break path
; ;
; Example inspired by incorrect analysis... ; Example inspired by incorrect analysis...
; ;
; The code analyzer sees: ; The code analyzer sees:
; beq {+03} ;jumps to the $8f ; beq {+03} ;jumps to the $8f
; lda #$00 ; lda #$00
; brk $8f ; brk $8f
; and stops, then pursues the branch. If we try to walk from top ; and stops, then pursues the branch. If we try to walk from top
; to bottom, skipping forward by the full length of an instruction, ; to bottom, skipping forward by the full length of an instruction,
; we'll appear to find ourselves in the middle of an embedded ; we'll appear to find ourselves in the middle of an embedded
; instruction. ; instruction.
; ;
; This is different from the typical embedded instruction, ; This is different from the typical embedded instruction,
; where the inner is contained entirely within the outer. ; where the inner is contained entirely within the outer.
test2 sep #$30 ;short regs test2 sep #$30 ;short regs
mx %00 ;pretend they're long mx %00 ;pretend they're long
lda $00 ;load something to scramble flags lda $00 ;load something to scramble flags
beq :store beq :store
lda #$0000 lda #$0000
:store stal $012345 :store stal $012345
rts rts
; TEST #3: embedded with non-instruction byte ; TEST #3: embedded with non-instruction byte
; ;
; The code analyzer sees two paths, involving the three bytes. ; The code analyzer sees two paths, involving the three bytes.
; The first is the three-byte JSR, the second is the one-byte ; The first is the three-byte JSR, the second is the one-byte
; RTS. The third NOP byte is never "executed" by the analyzer, ; RTS. The third NOP byte is never "executed" by the analyzer,
; but because of the way we display embedded instructions it ; but because of the way we display embedded instructions it
; gets put on its own line. Since it's not an instruction start ; gets put on its own line. Since it's not an instruction start
; or a data item, things get confused. (This is referred to as ; or a data item, things get confused. (This is referred to as
; an "embedded orphan" in the code.) ; an "embedded orphan" in the code.)
test3 dfb $20 ;JSR test3 dfb $20 ;JSR
:mid dfb $60 ;RTS :mid dfb $60 ;RTS
dfb $ea ;NOP dfb $ea ;NOP
bra :mid bra :mid
; TEST #4: overlapping chain ; TEST #4: overlapping chain
; ;
; Each BIT instruction is three bytes, and each byte is a branch target, ; Each BIT instruction is three bytes, and each byte is a branch target,
; so we get a string of embedded instructions. ; so we get a string of embedded instructions.
test4 test4
:bits hex 2c2c2c2c2c2c2c2c2ceaea :bits hex 2c2c2c2c2c2c2c2c2ceaea
asl asl
bcc :bits bcc :bits
asl asl
bcc :bits+1 bcc :bits+1
asl asl
bcc :bits+2 bcc :bits+2
asl asl
bcc :bits+3 bcc :bits+3
asl asl
bcc :bits+4 bcc :bits+4
asl asl
bcc :bits+5 bcc :bits+5
asl asl
bcc :bits+6 bcc :bits+6
asl asl
bcc :bits+7 bcc :bits+7
asl asl
bcc :bits+8 bcc :bits+8
asl asl
bcc :bits+9 bcc :bits+9
rts rts
; TEST #5: another overlap ; TEST #5: another overlap
; ;
; Trying to be a little different. ; Trying to be a little different.
test5 dfb $2c test5 dfb $2c
:mid1 nop :mid1 nop
hex ad hex ad
:mid2 lda $00 :mid2 lda $00
asl asl
bcc :mid1 bcc :mid1
asl asl
bcc :mid2 bcc :mid2
; TEST #6: "embedded" off the end of the file ; TEST #6: "embedded" off the end of the file
dfb $af ;ldal dfb $af ;ldal

4
testdata/1003-flags-and-branches.S vendored
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@ -2,7 +2,9 @@
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
xc off
xc
xc
org $1000 org $1000
clc clc
xce xce

10
testdata/2000-allops-value-6502.S vendored
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@ -1,8 +1,8 @@
; Copyright 2018 faddenSoft. All Rights Reserved. ; Copyright 2018 faddenSoft. All Rights Reserved.
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
xc off
ZP EQU $FF ZP EQU $FF
ABS EQU $FEFF ABS EQU $FEFF

4
testdata/2002-allops-value-65C02.S vendored
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@ -2,7 +2,9 @@
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
xc off
xc
;xc
ZP EQU $FF ZP EQU $FF
ABS EQU $FEFF ABS EQU $FEFF

4
testdata/2003-allops-zero-65C02.S vendored
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@ -2,7 +2,9 @@
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
xc off
xc
ZP EQU $00 ZP EQU $00
ABS EQU $0000 ABS EQU $0000

1
testdata/3008-macro-strings.S vendored
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@ -12,3 +12,4 @@ xx mac
xx "hello" xx "hello"
xx 'abc',00 xx 'abc',00
xx ff xx ff

42
testdata/allops-common-6502.S vendored
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@ -1,7 +1,7 @@
; Copyright 2018 faddenSoft. All Rights Reserved. ; Copyright 2018 faddenSoft. All Rights Reserved.
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
; ;
; Assembler: Merlin 32 ; Assembler: Merlin 32
ORG $1000 ORG $1000
@ -24,7 +24,7 @@
NOP NOP
NOP NOP
NOP NOP
BRK ZP ;$00 BRK ZP ;$00
PostBRK ORA (ZP,X) PostBRK ORA (ZP,X)
DFB $02 DFB $02
PostH02 DFB $03,ZP PostH02 DFB $03,ZP
@ -40,7 +40,7 @@ PostH02 DFB $03,ZP
ORA: ABS ORA: ABS
ASL: ABS ASL: ABS
DFB $0F,#<ABS,#>ABS DFB $0F,#<ABS,#>ABS
BPL PostBPL ;$10 BPL PostBPL ;$10
PostBPL ORA (ZP),Y PostBPL ORA (ZP),Y
DFB $12 DFB $12
PostH12 DFB $13,ZP PostH12 DFB $13,ZP
@ -56,7 +56,7 @@ PostH12 DFB $13,ZP
ORA: ABS,X ORA: ABS,X
ASL: ABS,X ASL: ABS,X
DFB $1F,#<ABS,#>ABS DFB $1F,#<ABS,#>ABS
JSR ABS ;$20 JSR ABS ;$20
AND (ZP,X) AND (ZP,X)
DFB $22 DFB $22
PostH22 DFB $23,ZP PostH22 DFB $23,ZP
@ -72,7 +72,7 @@ PostH22 DFB $23,ZP
AND: ABS AND: ABS
ROL: ABS ROL: ABS
DFB $2F,#<ABS,#>ABS DFB $2F,#<ABS,#>ABS
BMI PostBMI ;$30 BMI PostBMI ;$30
PostBMI AND (ZP),Y PostBMI AND (ZP),Y
DFB $32 DFB $32
PostH32 DFB $33,ZP PostH32 DFB $33,ZP
@ -84,11 +84,11 @@ PostH32 DFB $33,ZP
AND: ABS,Y AND: ABS,Y
DFB $3A DFB $3A
DFB $3B,#<ABS,#>ABS DFB $3B,#<ABS,#>ABS
BIT: ABS,X ;BIT: ABS,X // not available on standard 6502 (but is on 65C02)
AND: ABS,X AND: ABS,X
ROL: ABS,X ROL: ABS,X
DFB $3F,#<ABS,#>ABS DFB $3F,#<ABS,#>ABS
RTI ;$40 RTI ;$40
PostRTI EOR (ZP,X) PostRTI EOR (ZP,X)
DFB $42 DFB $42
PostH42 DFB $43,ZP PostH42 DFB $43,ZP
@ -104,7 +104,7 @@ PostH42 DFB $43,ZP
PostJMP EOR: ABS PostJMP EOR: ABS
LSR: ABS LSR: ABS
DFB $4f,#<ABS,#>ABS DFB $4f,#<ABS,#>ABS
BVC PostBVC ;$50 BVC PostBVC ;$50
PostBVC EOR (ZP),Y PostBVC EOR (ZP),Y
DFB $52 DFB $52
PostH52 DFB $53,ZP PostH52 DFB $53,ZP
@ -120,7 +120,7 @@ PostH52 DFB $53,ZP
EOR: ABS,X EOR: ABS,X
LSR: ABS,X LSR: ABS,X
DFB $5F,#<ABS,#>ABS DFB $5F,#<ABS,#>ABS
RTS ;$60 RTS ;$60
PostRTS ADC (ZP,X) PostRTS ADC (ZP,X)
DFB $62 DFB $62
PostH62 DFB $63,ZP PostH62 DFB $63,ZP
@ -136,7 +136,7 @@ PostH62 DFB $63,ZP
PostJMPI ADC: ABS PostJMPI ADC: ABS
ROR: ABS ROR: ABS
DFB $6F,#<ABS,#>ABS DFB $6F,#<ABS,#>ABS
BVS PostBVS ;$70 BVS PostBVS ;$70
PostBVS ADC (ZP),Y PostBVS ADC (ZP),Y
DFB $72 DFB $72
PostH72 DFB $73,ZP PostH72 DFB $73,ZP
@ -152,7 +152,7 @@ PostH72 DFB $73,ZP
ADC: ABS,X ADC: ABS,X
ROR: ABS,X ROR: ABS,X
DFB $7F,#<ABS,#>ABS DFB $7F,#<ABS,#>ABS
DFB $80,ZP ;$80 DFB $80,ZP ;$80
STA (ZP,X) STA (ZP,X)
DFB $82,ZP DFB $82,ZP
DFB $83,ZP DFB $83,ZP
@ -168,7 +168,7 @@ PostH72 DFB $73,ZP
STA: ABS STA: ABS
STX: ABS STX: ABS
DFB $8F,#<ABS,#>ABS DFB $8F,#<ABS,#>ABS
BCC PostBCC ;$90 BCC PostBCC ;$90
PostBCC STA (ZP),Y PostBCC STA (ZP),Y
DFB $92 DFB $92
PostH92 DFB $93,ZP PostH92 DFB $93,ZP
@ -184,7 +184,7 @@ PostH92 DFB $93,ZP
STA: ABS,X STA: ABS,X
DFB $9E,#<ABS,#>ABS DFB $9E,#<ABS,#>ABS
DFB $9F,#<ABS,#>ABS DFB $9F,#<ABS,#>ABS
LDY #ZP ;$A0 LDY #ZP ;$A0
LDA (ZP,X) LDA (ZP,X)
LDX #ZP LDX #ZP
DFB $A3,ZP DFB $A3,ZP
@ -200,7 +200,7 @@ PostH92 DFB $93,ZP
LDA: ABS LDA: ABS
LDX: ABS LDX: ABS
DFB $AF,#<ABS,#>ABS DFB $AF,#<ABS,#>ABS
BCS PostBCS ;$B0 BCS PostBCS ;$B0
PostBCS LDA (ZP),Y PostBCS LDA (ZP),Y
DFB $B2 DFB $B2
PostHB2 DFB $B3,ZP PostHB2 DFB $B3,ZP
@ -216,7 +216,7 @@ PostHB2 DFB $B3,ZP
LDA: ABS,X LDA: ABS,X
LDX: ABS,Y LDX: ABS,Y
DFB $BF,#<ABS,#>ABS DFB $BF,#<ABS,#>ABS
CPY #ZP ;$C0 CPY #ZP ;$C0
CMP (ZP,X) CMP (ZP,X)
DFB $C2,ZP DFB $C2,ZP
DFB $C3,ZP DFB $C3,ZP
@ -232,7 +232,7 @@ PostHB2 DFB $B3,ZP
CMP: ABS CMP: ABS
DEC: ABS DEC: ABS
DFB $CF,#<ABS,#>ABS DFB $CF,#<ABS,#>ABS
BNE PostBNE ;$D0 BNE PostBNE ;$D0
PostBNE CMP (ZP),Y PostBNE CMP (ZP),Y
DFB $D2 DFB $D2
PostHD2 DFB $D3,ZP PostHD2 DFB $D3,ZP
@ -248,7 +248,7 @@ PostHD2 DFB $D3,ZP
L11FC CMP: ABS,X L11FC CMP: ABS,X
DEC: ABS,X DEC: ABS,X
DFB $DF,#<ABS,#>ABS DFB $DF,#<ABS,#>ABS
CPX #ZP ;$E0 CPX #ZP ;$E0
SBC (ZP,X) SBC (ZP,X)
DFB $E2,ZP DFB $E2,ZP
DFB $E3,ZP DFB $E3,ZP
@ -264,7 +264,7 @@ L11FC CMP: ABS,X
SBC: ABS SBC: ABS
INC: ABS INC: ABS
DFB $EF,#<ABS,#>ABS DFB $EF,#<ABS,#>ABS
BEQ PostBEQ ;$F0 BEQ PostBEQ ;$F0
PostBEQ SBC (ZP),Y PostBEQ SBC (ZP),Y
DFB $F2 DFB $F2
PostHF2 DFB $F3,ZP PostHF2 DFB $F3,ZP

1
testdata/allops-common-65816.S vendored
View File

@ -5,6 +5,7 @@
ORG $1000 ORG $1000
mx %00
SEC SEC
XCE XCE
JSR L101F JSR L101F

1
testdata/allops-common-65C02.S vendored
View File

@ -1,6 +1,5 @@
; Copyright 2018 faddenSoft. All Rights Reserved. ; Copyright 2018 faddenSoft. All Rights Reserved.
; See the LICENSE.txt file for distribution terms (Apache 2.0). ; See the LICENSE.txt file for distribution terms (Apache 2.0).
;
; Assembler: Merlin 32 ; Assembler: Merlin 32
ORG $1000 ORG $1000

1
util.cpp
View File

@ -9,3 +9,4 @@ bool isMerlin816(void)
{ {
return(true); return(true);
} }