mirror of
https://github.com/a2-4am/4cade.git
synced 2024-11-26 17:49:43 +00:00
factor out more FX routines, and fix some RAM bank confusion now that launcher code extends below E000
This commit is contained in:
parent
90a6f55ddf
commit
d75c1cc039
@ -39,10 +39,15 @@ FirstMover
|
||||
;
|
||||
; If there is no stack to restore, this exits via SearchMode.
|
||||
;
|
||||
; in: none
|
||||
; in: LC RAM bank 1 or 2 must be banked in for reading because that's where
|
||||
; this code lives
|
||||
; out: see above
|
||||
;------------------------------------------------------------------------------
|
||||
Reenter
|
||||
; ensure that this code is high enough that it can function with
|
||||
; either LC RAM bank 1 or 2 banked in, because we might switch banks
|
||||
; during the routine
|
||||
!if (RELBASE != $2000) and (* < $E000) { !serious "Reenter is too low" }
|
||||
cld
|
||||
sta $C000 ; Turn 80STORE switch off
|
||||
ldx #$ff
|
||||
@ -157,6 +162,7 @@ gGlobalPrefsStore
|
||||
+DEFINE_INDIRECT_VECTOR iRippleCoordinates3Bit, RippleCoordinates3Bit
|
||||
+DEFINE_INDIRECT_VECTOR iReverseCoordinates3Bit, ReverseCoordinates3Bit
|
||||
+DEFINE_INDIRECT_VECTOR iSetupPrecomputed3Bit, SetupPrecomputed3Bit
|
||||
+DEFINE_INDIRECT_VECTOR iHGRPrecomputed2Bit, HGRPrecomputed2Bit
|
||||
+DEFINE_INDIRECT_VECTOR iRippleCoordinates2Bit, RippleCoordinates2Bit
|
||||
+DEFINE_INDIRECT_VECTOR iReverseCoordinates2Bit, ReverseCoordinates2Bit
|
||||
+DEFINE_INDIRECT_VECTOR iBuildDHGRSparseBitmasks2Bit, BuildDHGRSparseBitmasks2Bit
|
||||
|
181
src/4cade.init.a
181
src/4cade.init.a
@ -7,7 +7,7 @@
|
||||
; .SYSTEM file is loaded
|
||||
;
|
||||
|
||||
!src "src/4cade.init.machine.a"
|
||||
!src "src/4cade.init.machine.a" ; exits with ROM read, no write
|
||||
!src "src/4cade.init.screen.a"
|
||||
|
||||
; print text title in same place as graphical title will appear
|
||||
@ -21,7 +21,8 @@
|
||||
}
|
||||
|
||||
jsr Has64K ; check for 64K (required)
|
||||
bcc +
|
||||
; exits with ROM read, no write
|
||||
bcc @enough_mem
|
||||
|
||||
ldy #@no64Klen
|
||||
- lda @s_no64K,y
|
||||
@ -32,26 +33,30 @@
|
||||
@s_no64K !scrxor $80,"REQUIRES 64K"
|
||||
@no64Klen=(*-@s_no64K)-1
|
||||
|
||||
+
|
||||
@enough_mem
|
||||
lda #0
|
||||
sta zpMachineStatus
|
||||
sta SETC3ROM
|
||||
jsr HasVidHDCard ; check for VidHD card (allows super hi-res artwork even on non-IIgs machines)
|
||||
; does not rely on ROM
|
||||
sta CLRC3ROM
|
||||
ror zpMachineStatus
|
||||
lda ROM_MACHINEID
|
||||
lda ROM_MACHINEID ; requires ROM read
|
||||
cmp #$06
|
||||
bne @NotGS
|
||||
sec
|
||||
jsr $FE1F ; check for IIgs (allows super hi-res artwork)
|
||||
; requires ROM read
|
||||
bcs @NotGS
|
||||
sec
|
||||
+HIDE_NEXT_BYTE
|
||||
@NotGS clc
|
||||
ror zpMachineStatus
|
||||
jsr Has128K ; check for 128K (allows DHGR slideshows and 128K games)
|
||||
; exits with ROM read, no write
|
||||
ror zpMachineStatus
|
||||
jsr HasJoystick ; check for joystick (absence is OK but we filter out some games that require a joystick)
|
||||
; requires ROM read
|
||||
ror zpMachineStatus
|
||||
; now bit 4 = 1 if VidHD
|
||||
; bit 5 = 1 if IIgs
|
||||
@ -83,7 +88,7 @@
|
||||
+
|
||||
|
||||
; accommodate uppercase-only machines (64K ][ and ][+ are supported)
|
||||
lda ROM_MACHINEID
|
||||
lda ROM_MACHINEID ; requires ROM read
|
||||
cmp #$A0
|
||||
beq + ; Spectrum ED
|
||||
cmp #$06
|
||||
@ -98,14 +103,14 @@
|
||||
; print version or build number in lower right corner
|
||||
ldx #28
|
||||
ldy #23
|
||||
jsr SetCursorPosition
|
||||
jsr SetCursorPosition ; requires ROM read
|
||||
+LDADDR LoadingVersion
|
||||
jsr LoadingPrint
|
||||
jsr LoadingPrint ; requires ROM read
|
||||
!ifndef RELEASE {
|
||||
lda LoadingBuild
|
||||
ldx LoadingBuild+1
|
||||
ldy #0
|
||||
jsr PrintAsDecimal
|
||||
jsr PrintAsDecimal ; requires ROM read
|
||||
}
|
||||
|
||||
; set up text window so it only covers lower left corner
|
||||
@ -117,7 +122,7 @@
|
||||
; print machine configuration in lower left corner
|
||||
ldx #0
|
||||
ldy #23
|
||||
jsr SetCursorPosition
|
||||
jsr SetCursorPosition ; requires ROM read
|
||||
|
||||
; if zpMachineStatus AND IS_IIGS then print 'IIgs'
|
||||
; else if zpMachineStatus AND HAS_128K then print '128K'
|
||||
@ -135,21 +140,21 @@
|
||||
+
|
||||
+LDADDR Loading64K
|
||||
@printMem
|
||||
jsr LoadingPrint
|
||||
jsr LoadingPrint ; requires ROM read
|
||||
|
||||
; if zpMachineStatus AND HAS_JOYSTICK then CR & print 'joystick'
|
||||
lda zpMachineStatus
|
||||
and #HAS_JOYSTICK
|
||||
beq +
|
||||
+LDADDR LoadingJoystick
|
||||
jsr LoadingPrint
|
||||
jsr LoadingPrint ; requires ROM read
|
||||
+
|
||||
; if zpMachineStatus AND HAS_VIDHD then CR & print 'VidHD'
|
||||
lda zpMachineStatus
|
||||
and #HAS_VIDHD
|
||||
beq +
|
||||
+LDADDR LoadingVidHD
|
||||
jsr LoadingPrint
|
||||
jsr LoadingPrint ; requires ROM read
|
||||
+
|
||||
|
||||
@Relocate
|
||||
@ -159,30 +164,24 @@
|
||||
and #IS_IIGS
|
||||
beq +
|
||||
jsr HackThaCFFA
|
||||
|
||||
+
|
||||
; initialize and relocate ProRWTS2 to $D400 in LC RAM bank 2
|
||||
+READ_ROM_WRITE_RAM2
|
||||
jsr init ; initialize and relocate ProRWTS2 to $D400 in RAM bank 2
|
||||
; ProRWTS2 disk-data live at $D000-D3FF
|
||||
sei ; we're about to overwrite ProDOS's IRQ handler
|
||||
jsr init ; requires RAM2 write
|
||||
|
||||
; overwrite ProDOS IRQ handler
|
||||
sei
|
||||
lda #<NOIRQ
|
||||
sta $3FE
|
||||
lda #>NOIRQ ; in case another routine re-enables them
|
||||
lda #>NOIRQ
|
||||
sta $3FF
|
||||
cli
|
||||
ldx #$00 ; relocate program code to top of language card
|
||||
; since we end at $0000 now, adjust low offset to avoid destroying zpage
|
||||
@FM lda FirstMover - (RELBASE & $FF),x
|
||||
sta RELBASE & $FF00,x
|
||||
inx
|
||||
bne @FM
|
||||
inc @FM+2
|
||||
inc @FM+5
|
||||
bne @FM
|
||||
|
||||
; relocate pseudo-ProDOS to LC RAM bank 2
|
||||
ldx #$00
|
||||
ldy #>(255 + EvenLasterMover - LastMover)
|
||||
@LM lda COPYSRC,x ; relocate pseudo-ProDOS to RAM bank 2
|
||||
sta COPYDST,x
|
||||
@LM lda COPYSRC, x
|
||||
sta COPYDST, x ; requires RAM2 write
|
||||
inx
|
||||
bne @LM
|
||||
inc @LM+2
|
||||
@ -190,10 +189,35 @@
|
||||
dey
|
||||
bne @LM
|
||||
|
||||
+READ_RAM1_WRITE_RAM1
|
||||
jsr BuildAcceleratorFunction ; requires ROM read
|
||||
+ST16 @accelSrc
|
||||
dex
|
||||
-
|
||||
@accelSrc=*+1
|
||||
lda $FDFD,x ; copy (de)acceleration functions to LC RAM bank 2
|
||||
sta DisableAccelerator,x ; requires RAM2 write
|
||||
dex
|
||||
bpl -
|
||||
; X=FF
|
||||
|
||||
; relocate program code to LC RAM bank 1
|
||||
; since we end at $0000 now, we adjust low offset to avoid destroying zpage
|
||||
+READ_ROM_WRITE_RAM1
|
||||
inx
|
||||
;X=0
|
||||
@FM lda FirstMover - (RELBASE & $FF), x
|
||||
sta RELBASE & $FF00, x ; requires RAM1 write
|
||||
inx
|
||||
bne @FM
|
||||
inc @FM+2
|
||||
inc @FM+5
|
||||
bne @FM
|
||||
;X=0
|
||||
|
||||
; relocate font data to LC RAM bank 1
|
||||
ldy #4
|
||||
@ELM lda FONTSRC,x ; relocate font data to $D100/LC1
|
||||
sta FONTDST,x
|
||||
@ELM lda FONTSRC, x
|
||||
sta FONTDST, x ; requires RAM1 write
|
||||
inx
|
||||
bne @ELM
|
||||
inc @ELM+2
|
||||
@ -201,30 +225,19 @@
|
||||
dey
|
||||
bne @ELM
|
||||
|
||||
+READ_ROM_NO_WRITE
|
||||
jsr BuildAcceleratorFunction
|
||||
+READ_RAM2_WRITE_RAM2
|
||||
+ST16 @accelSrc
|
||||
dex
|
||||
-
|
||||
@accelSrc=*+1
|
||||
lda $FDFD,x ; copy (de)acceleration functions to RAM bank 2
|
||||
sta DisableAccelerator,x
|
||||
dex
|
||||
bpl -
|
||||
|
||||
+READ_ROM_WRITE_RAM2
|
||||
jsr BuildVBLFunction
|
||||
+DISABLE_ACCEL ; cycle counting in Mockingboard detection requires 1MHz
|
||||
|
||||
; /!\ macro exits with ROM read, no write
|
||||
+LDADDR FoundMockingboardCallback
|
||||
jsr GetMockingboardStuff
|
||||
+READ_RAM2_WRITE_RAM2
|
||||
stx MockingboardStuff ; save mockingboard slot and type in LC RAM
|
||||
+READ_ROM_NO_WRITE
|
||||
jsr GetMockingboardStuff ; requires ROM read
|
||||
; /!\ exits with ROM read, no write
|
||||
+READ_ROM_WRITE_RAM1
|
||||
stx MockingboardStuff ; save mockingboard slot and type
|
||||
; requires RAM1 write
|
||||
|
||||
jsr BuildVBLFunction ; requires ROM read, RAM1 write
|
||||
|
||||
txa
|
||||
beq +
|
||||
beq @done_with_mb
|
||||
and #HAS_STEREO
|
||||
beq @mb_mono
|
||||
+LDADDR LoadingMockingboardStereo
|
||||
@ -232,18 +245,18 @@
|
||||
@mb_mono
|
||||
+LDADDR LoadingMockingboardStereo
|
||||
@mb_print
|
||||
jsr LoadingPrint
|
||||
jsr LoadingPrint ; requires ROM read
|
||||
|
||||
; if Mockingboard AND HAS_SPEECH then print CR & '...and it talks!'
|
||||
txa
|
||||
and #HAS_SPEECH
|
||||
beq +
|
||||
beq @done_with_mb
|
||||
+LDADDR LoadingMockingboardSpeech
|
||||
jsr LoadingPrint
|
||||
jsr LoadingPrint ; requires ROM read
|
||||
|
||||
+
|
||||
+READ_RAM2_WRITE_RAM2
|
||||
jsr EnableAccelerator
|
||||
@done_with_mb
|
||||
+READ_RAM2_NO_WRITE
|
||||
jsr EnableAccelerator ; requires RAM2 read
|
||||
jmp OneTimeSetup
|
||||
|
||||
; ProRWTS2 has its own function to relocate itself
|
||||
@ -347,8 +360,10 @@ PrintAsDecimal
|
||||
!source "src/parse.common.a"
|
||||
|
||||
OneTimeSetup
|
||||
+READ_ROM_WRITE_RAM1
|
||||
lda zpMachineStatus
|
||||
sta MachineStatus ; save machine status in LC RAM
|
||||
sta MachineStatus ; save machine status
|
||||
; requires RAM1 write
|
||||
and #IS_IIGS
|
||||
beq @NotGSOS
|
||||
!cpu 65816
|
||||
@ -358,33 +373,39 @@ OneTimeSetup
|
||||
jsr PrepareGSOS
|
||||
@NotGSOS
|
||||
|
||||
; initialize ProDOS shim
|
||||
+READ_RAM2_WRITE_RAM2
|
||||
ldy #$0b
|
||||
CopyDevs
|
||||
lda $BF13,y
|
||||
sta promote + $13,y
|
||||
- lda $BF13, y
|
||||
sta promote + $13, y ; requires RAM2 write
|
||||
dey
|
||||
bpl CopyDevs
|
||||
|
||||
bpl -
|
||||
; save unit in LC bank 2 while overriding !pseudopc
|
||||
lda $BF30
|
||||
sta promote + ProDOS_unit - $bf00
|
||||
; save unit in LC bank 2 while overriding !pseudopc
|
||||
sta promote + ProDOS_unit - $bf00 ; requires RAM2 write
|
||||
|
||||
lda hddopendir+1 ; save current directory as 'root'
|
||||
ldy hddopendir+3
|
||||
sta gRootDirectory+1
|
||||
sty gRootDirectory+3
|
||||
jsr SwitchToBank1
|
||||
; save current directory as 'root'
|
||||
lda hddopendir+1 ; requires RAM2 read
|
||||
ldy hddopendir+3 ; requires RAM2 read
|
||||
sta gRootDirectory+1 ; requires RAM2 write
|
||||
sty gRootDirectory+3 ; requires RAM2 write
|
||||
|
||||
jsr LoadFile ; load preferences file into $8000
|
||||
; load raw preferences file into $8000
|
||||
+READ_RAM1_WRITE_RAM1
|
||||
jsr LoadFile ; requires RAM1 read
|
||||
; exits with RAM1 read/write
|
||||
!word kRootDirectory
|
||||
!word kGlobalPrefsFilename
|
||||
- !word $8000
|
||||
jsr ParseKeyValueList ; parse contents into OKVS data structure into LC RAM bank
|
||||
|
||||
; parse raw preferences file into OKVS data structure
|
||||
jsr ParseKeyValueList ; requires RAM1 write because that's where gGlobalPrefsStore is
|
||||
!word gGlobalPrefsStore
|
||||
!word -
|
||||
!byte 16
|
||||
|
||||
jsr pref_get ; see if cheats are enabled by default
|
||||
; see if cheats are enabled by default
|
||||
jsr pref_get ; requires RAM1 read
|
||||
; sets PTR -> cheat pref value as length-prefixed string '1' or '0'
|
||||
!word kCheat
|
||||
!word 0
|
||||
@ -394,8 +415,9 @@ CopyDevs
|
||||
asl
|
||||
asl
|
||||
asl ; A = #$08 or #$00
|
||||
ora MachineStatus
|
||||
ora MachineStatus ; requires RAM1 read
|
||||
sta MachineStatus ; set bit 3 of MachineStatus
|
||||
; requires RAM1 write
|
||||
|
||||
rol
|
||||
rol
|
||||
@ -405,9 +427,10 @@ CopyDevs
|
||||
tax ; X in (0,2,4,6)
|
||||
ldy kGameCounts, x
|
||||
sty GameCount ; store total game count based on based on (has-joystick) X (has-128K)
|
||||
; requires RAM1 write
|
||||
sty SAVE
|
||||
ldy kGameCounts+1, x
|
||||
sty GameCount+1
|
||||
sty GameCount+1 ; requires RAM1 write
|
||||
sty SAVE+1
|
||||
lsr
|
||||
tax ; X in (0,1,2,3)
|
||||
@ -422,10 +445,10 @@ CopyDevs
|
||||
ldy #5
|
||||
@searchIndexSrc
|
||||
lda $FDFD, y ; SMC
|
||||
sta kSearchIndexRecord, y
|
||||
sta kSearchIndexRecord, y ; requires RAM1 write
|
||||
@searchCacheSrc
|
||||
lda $FDFD, y
|
||||
sta kSearchCacheRecord, y
|
||||
sta kSearchCacheRecord, y ; requires RAM1 write
|
||||
dey
|
||||
bpl @searchIndexSrc
|
||||
|
||||
@ -453,13 +476,13 @@ CopyDevs
|
||||
sta SAVE
|
||||
pla
|
||||
ora #$30
|
||||
sta VisibleGameCount,y
|
||||
sta VisibleGameCount,y ; requires RAM1 write
|
||||
iny
|
||||
cpy #$03
|
||||
bcc @outer
|
||||
|
||||
bit CLEARKBD
|
||||
jmp Reenter
|
||||
jmp Reenter ; requires RAM1 or RAM2 read
|
||||
|
||||
@kPowersOfTen
|
||||
!byte 100
|
||||
|
@ -197,7 +197,8 @@ iBuildHGRSparseBitmasks2Bit = iHGRPrecomputed1Bit-3
|
||||
iBuildDHGRSparseBitmasks2Bit = iBuildHGRSparseBitmasks2Bit-3
|
||||
iReverseCoordinates2Bit = iBuildDHGRSparseBitmasks2Bit-3
|
||||
iRippleCoordinates2Bit = iReverseCoordinates2Bit-3
|
||||
iSetupPrecomputed3Bit = iRippleCoordinates2Bit-3
|
||||
iHGRPrecomputed2Bit = iRippleCoordinates2Bit-3
|
||||
iSetupPrecomputed3Bit = iHGRPrecomputed2Bit-3
|
||||
iReverseCoordinates3Bit = iSetupPrecomputed3Bit-3
|
||||
iRippleCoordinates3Bit = iReverseCoordinates3Bit-3
|
||||
|
||||
|
122
src/fx.lib.a
122
src/fx.lib.a
@ -30,6 +30,7 @@
|
||||
; - BuildDHGRSparseBitmasks2Bit
|
||||
; - ReverseCoordinates2Bit
|
||||
; - RippleCoordinates2Bit
|
||||
; - HGRPrecomputed2Bit
|
||||
|
||||
; - SetupPrecomputed3Bit
|
||||
; - ReverseCoordinates3Bit
|
||||
@ -428,70 +429,70 @@ HGRPrecomputed1Bit
|
||||
jsr BuildHGRMirrorTables
|
||||
jsr BuildHGRMirrorCols
|
||||
jsr BuildHGRSparseBitmasks1Bit
|
||||
+COPY_TO_0 start, end
|
||||
jmp InputLoop
|
||||
start
|
||||
+COPY_TO_0 .start, .end
|
||||
jmp .InputLoop
|
||||
.start
|
||||
!pseudopc 0 {
|
||||
Exit1Bit rts
|
||||
InputLoop
|
||||
.Exit1Bit rts
|
||||
.InputLoop
|
||||
ldy #0
|
||||
input=*+1
|
||||
.input=*+1
|
||||
ldx Coordinates1Bit ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
bmi .Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES .src1, .src2, .dest1, .dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES .mirror_src1, .mirror_src2, .mirror_dest1, .mirror_dest2
|
||||
|
||||
inc input
|
||||
lda (input), y
|
||||
+HIGH_3_LOW_5 input
|
||||
inc .input
|
||||
lda (.input), y
|
||||
+HIGH_3_LOW_5 .input
|
||||
|
||||
; main 1x2 block in top-left quadrant
|
||||
src1=*+1
|
||||
.src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<dest1), y
|
||||
eor (<.dest1), y
|
||||
and copymasks1bit, x
|
||||
eor (<dest1), y
|
||||
dest1=*+1
|
||||
eor (<.dest1), y
|
||||
.dest1=*+1
|
||||
sta $FDFD, y
|
||||
src2=*+1
|
||||
.src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<dest2), y
|
||||
eor (<.dest2), y
|
||||
and copymasks1bit, x
|
||||
eor (<dest2), y
|
||||
dest2=*+1
|
||||
eor (<.dest2), y
|
||||
.dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 1x2 block in top-right quadrant (same row, opposite column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT src1, dest1, mirror_copymasks1bit
|
||||
+COPY_BIT src2, dest2, mirror_copymasks1bit
|
||||
+COPY_BIT .src1, .dest1, mirror_copymasks1bit
|
||||
+COPY_BIT .src2, .dest2, mirror_copymasks1bit
|
||||
|
||||
; corresponding 1x2 block in bottom-right quadrant (opposite row, opposite column)
|
||||
mirror_src1=*+1
|
||||
.mirror_src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<mirror_dest1), y
|
||||
eor (<.mirror_dest1), y
|
||||
and mirror_copymasks1bit, x
|
||||
eor (<mirror_dest1), y
|
||||
mirror_dest1=*+1
|
||||
eor (<.mirror_dest1), y
|
||||
.mirror_dest1=*+1
|
||||
sta $FDFD, y
|
||||
mirror_src2=*+1
|
||||
.mirror_src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<mirror_dest2), y
|
||||
eor (<.mirror_dest2), y
|
||||
and mirror_copymasks1bit, x
|
||||
eor (<mirror_dest2), y
|
||||
mirror_dest2=*+1
|
||||
eor (<.mirror_dest2), y
|
||||
.mirror_dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 1x2 block in bottom-left quadrant (opposite row, original column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT mirror_src1, mirror_dest1, copymasks1bit
|
||||
+COPY_BIT mirror_src2, mirror_dest2, copymasks1bit
|
||||
+COPY_BIT .mirror_src1, .mirror_dest1, copymasks1bit
|
||||
+COPY_BIT .mirror_src2, .mirror_dest2, copymasks1bit
|
||||
|
||||
+INC_INPUT_AND_LOOP InputLoop
|
||||
+INC_INPUT_AND_LOOP .input, .InputLoop
|
||||
}
|
||||
end
|
||||
.end
|
||||
}
|
||||
|
||||
BuildHGRSparseBitmasks2Bit
|
||||
@ -737,6 +738,59 @@ RippleCoordinates2Bit
|
||||
!word 2194, 6582
|
||||
@zerotbl !byte $f0, $f2, $ca, $d2, $d8, $e0, $e2, $e6, $ea, $ee
|
||||
|
||||
!zone {
|
||||
HGRPrecomputed2Bit
|
||||
jsr BuildHGRTables
|
||||
jsr BuildHGRMirrorCols
|
||||
jsr BuildHGRSparseBitmasks2Bit
|
||||
+COPY_TO_0 .start, .end
|
||||
jmp .InputLoop
|
||||
.start
|
||||
!pseudopc 0 {
|
||||
.Exit2Bit rts
|
||||
.InputLoop
|
||||
ldy #0
|
||||
.input=*+1
|
||||
ldx Coordinates2Bit ; first value: HGR row + 1
|
||||
beq .Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES .src1, .src2, .dest1, .dest2
|
||||
|
||||
inc <.input
|
||||
lda (<.input), y
|
||||
+HIGH_3_LOW_5 .input
|
||||
|
||||
; main 2x2 block in left half
|
||||
.src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<.dest1), y
|
||||
and copymasks2bit, x
|
||||
eor (<.dest1), y
|
||||
.dest1=*+1
|
||||
sta $FDFD, y
|
||||
.src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<.dest2), y
|
||||
and copymasks2bit, x
|
||||
eor (<.dest2), y
|
||||
.dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 2x2 block in right half (same row, opposite column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT .src1, .dest1, mirror_copymasks2bit
|
||||
+COPY_BIT .src2, .dest2, mirror_copymasks2bit
|
||||
|
||||
inc <.input
|
||||
bne .InputLoop
|
||||
bit KBD
|
||||
bmi .Exit2Bit
|
||||
inc <.input+1
|
||||
bne .InputLoop ; always branches
|
||||
}
|
||||
.end
|
||||
}
|
||||
|
||||
SetupPrecomputed3Bit
|
||||
; build regular HGR lookup tables, then split them
|
||||
jsr BuildHGRTables
|
||||
|
@ -51,7 +51,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -67,7 +67,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -77,7 +77,7 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -93,7 +93,7 @@ LoopTL ; top-left quadrant
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -103,7 +103,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -121,7 +121,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -131,7 +131,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -149,7 +149,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -44,8 +44,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -83,8 +83,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -19,8 +19,8 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
|
||||
inc input
|
||||
lda (input), y
|
||||
@ -90,7 +90,7 @@ y=*+1
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
|
||||
+INC_INPUT_AND_LOOP InputLoop
|
||||
+INC_INPUT_AND_LOOP input, InputLoop
|
||||
}
|
||||
end
|
||||
}
|
||||
@ -147,8 +147,8 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
|
||||
iny
|
||||
lda (input), y
|
||||
|
@ -18,7 +18,7 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
|
||||
inc <input
|
||||
lda (<input), y
|
||||
@ -131,7 +131,7 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
|
||||
iny
|
||||
lda (<input), y
|
||||
|
@ -34,7 +34,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -50,7 +50,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -60,7 +60,7 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -76,7 +76,7 @@ LoopTL ; top-left quadrant
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -86,7 +86,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -104,7 +104,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -114,7 +114,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -132,7 +132,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -29,8 +29,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -68,8 +68,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -37,8 +37,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -76,8 +76,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUBBLES.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUTTERFLY.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUTTERFLY.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUTTERFLY.DATA"
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "CORNER4.DATA"
|
||||
|
@ -50,13 +50,13 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT_DITHER mirror_src1, mirror_dest1, copymasks1bit, oddrow_ptr
|
||||
+COPY_BIT_DITHER mirror_src2, mirror_dest2, copymasks1bit, evenrow_ptr
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -66,13 +66,13 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT_DITHER src1, dest1, copymasks1bit, evenrow_ptr
|
||||
+COPY_BIT_DITHER src2, dest2, copymasks1bit, oddrow_ptr
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -82,7 +82,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -90,7 +90,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
tay
|
||||
+COPY_BIT_DITHER src1, dest1, mirror_copymasks1bit, evenrow_ptr
|
||||
+COPY_BIT_DITHER src2, dest2, mirror_copymasks1bit, oddrow_ptr
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -100,7 +100,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -108,7 +108,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
tay
|
||||
+COPY_BIT_DITHER mirror_src1, mirror_dest1, mirror_copymasks1bit, oddrow_ptr
|
||||
+COPY_BIT_DITHER mirror_src2, mirror_dest2, mirror_copymasks1bit, evenrow_ptr
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -43,8 +43,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -62,8 +62,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "HEART.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "HEART.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "HEART.DATA"
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "IRIS.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "MAPLE.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "MAPLE.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "MAPLE.DATA"
|
||||
|
@ -90,8 +90,8 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
|
||||
iny
|
||||
lda (<input), y
|
||||
|
@ -20,24 +20,6 @@
|
||||
|
||||
!source "src/fx/macros.a"
|
||||
|
||||
!macro ROW_X_TO_2BIT_BASE_ADDRESSES {
|
||||
; X = $01..$C0, mapping to row 0..191
|
||||
lda hgrlo-1, x
|
||||
sta <dest1
|
||||
sta <src1
|
||||
lda hgr1hi-1, x
|
||||
sta <dest1+1
|
||||
eor #$60
|
||||
sta <src1+1
|
||||
lda hgrlo, x
|
||||
sta <dest2
|
||||
sta <src2
|
||||
lda hgr1hi, x
|
||||
sta <dest2+1
|
||||
eor #$60
|
||||
sta <src2+1
|
||||
}
|
||||
|
||||
!macro FX_INITONCE_2BIT .CoordinatesFile, .Start {
|
||||
InitOnce
|
||||
bit .Start
|
||||
@ -52,58 +34,6 @@ InitOnce
|
||||
sta EndCoordinates2Bit
|
||||
}
|
||||
|
||||
!macro FX_PRECOMPUTED_2BIT .coords {
|
||||
jsr iBuildHGRTables
|
||||
jsr iBuildHGRMirrorCols
|
||||
jsr iBuildHGRSparseBitmasks2Bit
|
||||
+COPY_TO_0 start, end
|
||||
jmp InputLoop
|
||||
start
|
||||
!pseudopc 0 {
|
||||
Exit2Bit rts
|
||||
InputLoop
|
||||
ldy #0
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
|
||||
inc <input
|
||||
lda (<input), y
|
||||
+HIGH_3_LOW_5 input
|
||||
|
||||
; main 2x2 block in left half
|
||||
src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<dest1), y
|
||||
and copymasks2bit, x
|
||||
eor (<dest1), y
|
||||
dest1=*+1
|
||||
sta $FDFD, y
|
||||
src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<dest2), y
|
||||
and copymasks2bit, x
|
||||
eor (<dest2), y
|
||||
dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 2x2 block in right half (same row, opposite column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT src1, dest1, mirror_copymasks2bit
|
||||
+COPY_BIT src2, dest2, mirror_copymasks2bit
|
||||
|
||||
inc <input
|
||||
bne InputLoop
|
||||
bit KBD
|
||||
bmi Exit2Bit
|
||||
inc <input+1
|
||||
bne InputLoop ; always branches
|
||||
}
|
||||
end
|
||||
}
|
||||
|
||||
!macro FX_PRECOMPUTED_2BIT_DITHER .coords, .endcoords {
|
||||
jsr iBuildHGRDitherMasks
|
||||
jsr iBuildHGRTables
|
||||
@ -158,7 +88,7 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
|
||||
iny
|
||||
lda (<input), y
|
||||
|
@ -34,13 +34,13 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT mirror_src1, mirror_dest1, copymasks1bit
|
||||
+COPY_BIT mirror_src2, mirror_dest2, copymasks1bit
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -50,13 +50,13 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT src1, dest1, copymasks1bit
|
||||
+COPY_BIT src2, dest2, copymasks1bit
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -66,7 +66,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -74,7 +74,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
tay
|
||||
+COPY_BIT src1, dest1, mirror_copymasks1bit
|
||||
+COPY_BIT src2, dest2, mirror_copymasks1bit
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -84,7 +84,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -92,7 +92,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
tay
|
||||
+COPY_BIT mirror_src1, mirror_dest1, mirror_copymasks1bit
|
||||
+COPY_BIT mirror_src2, mirror_dest2, mirror_copymasks1bit
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -28,8 +28,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -47,8 +47,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -35,8 +35,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -54,8 +54,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SLOW.STAR.DATA"
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SNOWFLAKE.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SOFT.IRIS.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SOFT.IRIS.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.DATA"
|
||||
|
@ -1,5 +1,5 @@
|
||||
;license:MIT
|
||||
;(c) 2019 by 4am
|
||||
;(c) 2019-2024 by 4am/qkumba
|
||||
;
|
||||
!cpu 6502
|
||||
!to "build/FX.INDEXED/STAR.BLOOM",plain
|
||||
@ -7,11 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.2bit.a"
|
||||
|
||||
+FX_PRECOMPUTED_2BIT Coordinates
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
!if * and 1 {
|
||||
!byte 0
|
||||
}
|
||||
Coordinates
|
||||
!source "src/fx/fx.hgr.star.bloom.data.a"
|
||||
!byte $00
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.BLOOM.DATA"
|
||||
|
@ -1,3 +1,6 @@
|
||||
!cpu 6502
|
||||
!to "build/FX/STAR.BLOOM.DATA",plain
|
||||
*=$8100
|
||||
!byte $A5,%01000000
|
||||
!byte $01,%00100010
|
||||
!byte $B3,%00100010
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR7.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR7.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR7.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "WAVY.IRIS.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "W.IR.BLOOM.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "W.IR.BLOOM.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "WAVY.IRIS.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "WAVY.IRIS.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "W.IR.BLOOM.DATA"
|
||||
|
@ -67,38 +67,56 @@
|
||||
sta CopyMaskAddr+1
|
||||
}
|
||||
|
||||
!macro ROW_X_TO_BASE_ADDRESSES {
|
||||
!macro ROW_X_TO_BASE_ADDRESSES .src1, .src2, .dest1, .dest2 {
|
||||
lda hgrlo, x
|
||||
sta <dest1
|
||||
sta <src1
|
||||
sta <.dest1
|
||||
sta <.src1
|
||||
lda hgr1hi, x
|
||||
sta <dest1+1
|
||||
sta <.dest1+1
|
||||
eor #$60
|
||||
sta <src1+1
|
||||
sta <.src1+1
|
||||
lda hgrlo+1, x
|
||||
sta <dest2
|
||||
sta <src2
|
||||
sta <.dest2
|
||||
sta <.src2
|
||||
lda hgr1hi+1, x
|
||||
sta <dest2+1
|
||||
sta <.dest2+1
|
||||
eor #$60
|
||||
sta <src2+1
|
||||
sta <.src2+1
|
||||
}
|
||||
|
||||
!macro ROW_X_TO_MIRROR_ADDRESSES {
|
||||
!macro ROW_X_TO_MIRROR_ADDRESSES .mirror_src1, .mirror_src2, .mirror_dest1, .mirror_dest2 {
|
||||
lda hgrlomirror, x
|
||||
sta <mirror_dest1
|
||||
sta <mirror_src1
|
||||
sta <.mirror_dest1
|
||||
sta <.mirror_src1
|
||||
lda hgr1himirror, x
|
||||
sta <mirror_dest1+1
|
||||
sta <.mirror_dest1+1
|
||||
eor #$60
|
||||
sta <mirror_src1+1
|
||||
sta <.mirror_src1+1
|
||||
lda hgrlomirror+1, x
|
||||
sta <mirror_dest2
|
||||
sta <mirror_src2
|
||||
sta <.mirror_dest2
|
||||
sta <.mirror_src2
|
||||
lda hgr1himirror+1, x
|
||||
sta <mirror_dest2+1
|
||||
sta <.mirror_dest2+1
|
||||
eor #$60
|
||||
sta <mirror_src2+1
|
||||
sta <.mirror_src2+1
|
||||
}
|
||||
|
||||
!macro ROW_X_TO_2BIT_BASE_ADDRESSES .src1, .src2, .dest1, .dest2 {
|
||||
; X = $01..$C0, mapping to row 0..191
|
||||
lda hgrlo-1, x
|
||||
sta <.dest1
|
||||
sta <.src1
|
||||
lda hgr1hi-1, x
|
||||
sta <.dest1+1
|
||||
eor #$60
|
||||
sta <.src1+1
|
||||
lda hgrlo, x
|
||||
sta <.dest2
|
||||
sta <.src2
|
||||
lda hgr1hi, x
|
||||
sta <.dest2+1
|
||||
eor #$60
|
||||
sta <.src2+1
|
||||
}
|
||||
|
||||
!macro HGR_CALC_ROUTINES {
|
||||
|
@ -53,25 +53,25 @@
|
||||
bne -
|
||||
}
|
||||
|
||||
!macro INC_INPUT_AND_LOOP .loop {
|
||||
inc <input
|
||||
!macro INC_INPUT_AND_LOOP .input, .loop {
|
||||
inc <.input
|
||||
beq +
|
||||
jmp .loop
|
||||
+ bit KBD
|
||||
bmi +
|
||||
inc <input+1
|
||||
inc <.input+1
|
||||
jmp .loop
|
||||
+ rts
|
||||
}
|
||||
|
||||
!macro DEC_INPUT_AND_LOOP .loop {
|
||||
lda input
|
||||
!macro DEC_INPUT_AND_LOOP .input, .loop {
|
||||
lda .input
|
||||
php
|
||||
dec input
|
||||
dec input
|
||||
dec .input
|
||||
dec .input
|
||||
plp
|
||||
bne +
|
||||
dec input+1
|
||||
dec .input+1
|
||||
bit KBD
|
||||
bpl .loop
|
||||
bmi ++
|
||||
|
@ -142,7 +142,7 @@ zc_enable = $C05B
|
||||
iobase = $C000 ; easily confused with kbd
|
||||
|
||||
BuildAcceleratorFunction
|
||||
; in: none
|
||||
; in: ROM banked in for reading
|
||||
; out: A/Y points to lo/hi address of code block
|
||||
; X contains length of code block
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
; HasJoystick
|
||||
; Checks whether computer has joystick connected
|
||||
;
|
||||
; in: none
|
||||
; in: ROM banked in for reading
|
||||
; out: C set if joystick found
|
||||
; C clear if no joystick found
|
||||
; other flags clobbered
|
||||
@ -16,14 +16,14 @@
|
||||
; Fastchip firmware 0.4b-compatibility fix by Frank M. (0.5b seems unaffected)
|
||||
;------------------------------------------------------------------------------
|
||||
HasJoystick
|
||||
lda $FBB3
|
||||
lda ROM_MACHINEID ; requires ROM read
|
||||
cmp #$06
|
||||
bne ++
|
||||
lda $FBC0
|
||||
cmp #$E0
|
||||
beq + ; test for Fastchip on enhanced //e
|
||||
beq + ; test for Fastchip on enhanced //e
|
||||
cmp #$EA
|
||||
beq + ; test for Fastchip on non-enhanced //e
|
||||
beq + ; test for Fastchip on non-enhanced //e
|
||||
jmp ++
|
||||
|
||||
+ ; FASTChip
|
||||
@ -31,12 +31,12 @@ fc_lock = $C06A
|
||||
fc_enable = $C06B
|
||||
fc_config = $C06E
|
||||
fc_data = $C06F
|
||||
FC_UNLOCK = $6A ; write 4 times
|
||||
FC_UNLOCK = $6A ; write 4 times
|
||||
FC_LOCK = $A6
|
||||
FC_SPKR = 2 ; speaker delay register
|
||||
FC_HIFI = 4 ; set to 'HIFI'
|
||||
FC_JOY = 3 ; joystick delay register
|
||||
FC_LONG = 2 ; set to 'LONG'
|
||||
FC_SPKR = 2 ; speaker delay register
|
||||
FC_HIFI = 4 ; set to 'HIFI'
|
||||
FC_JOY = 3 ; joystick delay register
|
||||
FC_LONG = 2 ; set to 'LONG'
|
||||
|
||||
lda #FC_UNLOCK
|
||||
sta fc_lock
|
||||
|
@ -17,6 +17,7 @@
|
||||
; (this will be called before the speech detection routine, and
|
||||
; (zp$81 will contain the slot in form $Cx)
|
||||
; /!\ ALL ACCELERATORS MUST BE OFF OR SET TO 1 MHZ
|
||||
; ROM must be banked in for reading
|
||||
; out: if card was found, X = #$?n where n is the slot number of the card, otherwise #$00
|
||||
; and bit 5 = 0 if Mockingboard Sound I found
|
||||
; or bit 5 = 1 if Mockingboard Sound II or "A"-"D" found
|
||||
@ -25,6 +26,7 @@
|
||||
; flags clobbered
|
||||
; zp $80-$82 clobbered
|
||||
; A/Y clobbered
|
||||
; ROM banked in, no write
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
MAGIC_Z80_LOCATION=$FFD
|
||||
|
@ -15,6 +15,7 @@ ROMID_IIECARD = 2
|
||||
idroutine = $FE1F ; SEC, JSR $FE1F, BCS notgs
|
||||
|
||||
BuildVBLFunction
|
||||
; in: ROM must be banked in for reading
|
||||
ldx romid
|
||||
cpx #ROMID_IIECOMPAT
|
||||
bne @build_none ; not a //e
|
||||
@ -22,7 +23,7 @@ BuildVBLFunction
|
||||
beq @build_iic ; //c family
|
||||
lda romid_mac
|
||||
cmp #ROMID_IIECARD
|
||||
beq @build_iiecard ; Mac Apple IIe card
|
||||
beq @build_iiecard ; Mac Apple IIe card
|
||||
sec
|
||||
jsr idroutine ; check for IIgs
|
||||
bcs @NotGS
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15906588
|
||||
!be24 15903445
|
||||
!le16 5130
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15851268
|
||||
!be24 15848103
|
||||
!le16 5732
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15783035
|
||||
!be24 15779870
|
||||
!le16 4194
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15797749
|
||||
!be24 15794584
|
||||
!le16 4652
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15816464
|
||||
!be24 15813299
|
||||
!le16 5621
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15837505
|
||||
!be24 15834340
|
||||
!le16 6199
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15911718
|
||||
!be24 15908575
|
||||
!le16 410
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912472
|
||||
!be24 15909329
|
||||
!le16 449
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912921
|
||||
!be24 15909778
|
||||
!le16 303
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 12679253
|
||||
!be24 12676088
|
||||
!le16 1652
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15859640
|
||||
!be24 15856475
|
||||
!le16 1640
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912204
|
||||
!be24 15909061
|
||||
!le16 67
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15906529
|
||||
!be24 15903386
|
||||
!le16 59
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15904949
|
||||
!be24 15901806
|
||||
!le16 1426
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15889715
|
||||
!be24 15886572
|
||||
!le16 557
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15857000
|
||||
!be24 15853835
|
||||
!le16 2640
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15861638
|
||||
!le16 451
|
||||
!be24 15858473
|
||||
!le16 473
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15862089
|
||||
!be24 15858946
|
||||
!le16 7564
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912128
|
||||
!be24 15908985
|
||||
!le16 76
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15906375
|
||||
!be24 15903232
|
||||
!le16 154
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912271
|
||||
!be24 15909128
|
||||
!le16 201
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15890272
|
||||
!be24 15887129
|
||||
!le16 4334
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15894606
|
||||
!be24 15891463
|
||||
!le16 1733
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15896339
|
||||
!be24 15893196
|
||||
!le16 1181
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15897520
|
||||
!be24 15894377
|
||||
!le16 3394
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15900914
|
||||
!be24 15897771
|
||||
!le16 3429
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15904343
|
||||
!be24 15901200
|
||||
!le16 479
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15904822
|
||||
!be24 15901679
|
||||
!le16 127
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15913224
|
||||
!be24 15910081
|
||||
!le16 2370
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15875058
|
||||
!be24 15871915
|
||||
!le16 5083
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15880141
|
||||
!be24 15876998
|
||||
!le16 2485
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15843704
|
||||
!be24 15840539
|
||||
!le16 7564
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15773452
|
||||
!be24 15770287
|
||||
!le16 9583
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15787229
|
||||
!be24 15784064
|
||||
!le16 10520
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15802401
|
||||
!be24 15799236
|
||||
!le16 14063
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15822085
|
||||
!be24 15818920
|
||||
!le16 15420
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15861280
|
||||
!be24 15858115
|
||||
!le16 358
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15869653
|
||||
!be24 15866510
|
||||
!le16 5405
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15882626
|
||||
!be24 15879483
|
||||
!le16 7089
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15769104
|
||||
!be24 15765939
|
||||
!le16 4348
|
||||
|
Loading…
Reference in New Issue
Block a user