mirror of
https://github.com/brouhaha/Apple-II_MiSTer.git
synced 2024-12-01 22:51:27 +00:00
265 lines
8.5 KiB
Systemverilog
265 lines
8.5 KiB
Systemverilog
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module hdmi_config
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(
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// Host Side
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input iCLK,
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input iRST_N,
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// 0 - 480i
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// 1 - 480p
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// 2 - 576i
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// 3 - 576p
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// 4 - 720p
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// 5-7 - reserved
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input [2:0] iRES,
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// 0 - 4:3
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// 1 - 16:9
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input iAR,
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input audio_48k,
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// I2C Side
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output I2C_SCL,
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inout I2C_SDA
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);
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// Internal Registers/Wires
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reg mI2C_GO = 0;
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wire mI2C_END;
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wire mI2C_ACK;
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reg [15:0] LUT_DATA;
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reg [7:0] LUT_INDEX = 0;
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I2C_Controller #(50_000_000, 400_000) i2c_av
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(
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.CLK(iCLK),
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.I2C_SCL(I2C_SCL), // I2C CLOCK
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.I2C_SDA(I2C_SDA), // I2C DATA
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.I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
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.START(mI2C_GO), // START transfer
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.END(mI2C_END), // END transfer
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.ACK(mI2C_ACK) // ACK
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);
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////////////////////// Config Control ////////////////////////////
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always@(posedge iCLK or negedge iRST_N) begin
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reg [1:0] mSetup_ST = 0;
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if(!iRST_N) begin
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LUT_INDEX <= 0;
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mSetup_ST <= 0;
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mI2C_GO <= 0;
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end else begin
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if(init_data[LUT_INDEX] != 16'hFFFF) begin
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case(mSetup_ST)
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0: begin
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mI2C_GO <= 1;
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mSetup_ST <= 1;
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end
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1: if(~mI2C_END) mSetup_ST <= 2;
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2: begin
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mI2C_GO <= 0;
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if(mI2C_END) begin
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mSetup_ST <= 0;
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if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
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end
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end
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endcase
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end
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end
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end
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wire [15:0] res480i[6] = '{'h35_1D, 'h36_92, 'h37_05, 'h38_A0, 'h39_0F, 'h3A_00};
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wire [15:0] res480p[6] = '{'h35_1F, 'h36_E8, 'h37_05, 'h38_A0, 'h39_1E, 'h3A_00};
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wire [15:0] res576i[6] = '{'h35_20, 'h36_D6, 'h37_05, 'h38_A0, 'h39_12, 'h3A_00};
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wire [15:0] res576p[6] = '{'h35_20, 'h36_EC, 'h37_05, 'h38_A0, 'h39_24, 'h3A_00};
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wire [15:0] res720p[6] = '{'h35_40, 'h36_D9, 'h37_0A, 'h38_00, 'h39_2D, 'h3A_00};
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reg [15:0] resVar[6];
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always_comb begin
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case(iRES)
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0: resVar <= res480i;
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1: resVar <= res480p;
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2: resVar <= res576i;
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3: resVar <= res576p;
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4: resVar <= res720p;
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default: resVar <= res720p;
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endcase
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end
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////////////////////////////////////////////////////////////////////
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///////////////////// Config Data LUT //////////////////////////
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wire [15:0] init_data[58] =
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'{
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16'h4110, // Power Down control
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16'h9803, // ADI required Write.
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16'h9A70, // ADI required Write.
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16'h9C30, // ADI required Write.
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{8'h9D, 8'b0110_0001}, // [7:4] must be b0110!.
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// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
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// [1:0] must be b01!
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16'hA2A4, // ADI required Write.
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16'hA3A4, // ADI required Write.
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16'hE0D0, // ADI required Write.
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resVar[0],
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resVar[1],
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resVar[2],
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resVar[3],
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resVar[4],
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resVar[5],
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{8'h16, 8'b0011_1000}, // Output Format 444 [7]=0.
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// [6] must be 0!
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// Colour Depth for Input Video data [5:4] b11 = 8-bit.
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// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
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// DDR Input Edge falling [1]=0 (not using DDR atm).
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// Output Colour Space RGB [0]=0.
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// {8'h16, 8'b1011_0101}, // Output Format 422 [7]=1.
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// [6] must be 0!
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// Colour Depth for Input Video data [5:4] b11 = 8-bit.
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// Input Style [3:2] b01 = Style 2.
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// DDR Input Edge falling [1]=0 (not using DDR atm).
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// Output Colour Space YPrPb [0]=1.
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// {8'h17, 8'b0110_0000}, // Aspect ratio 4:3 [1]=0. DE Generation DISabled [0]=0.
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// Vsync polarity HIGH [6]=0, LOW [6]=1.
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// Hsync polarity HIGH [5]=0, LOW [5]=1.
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// {8'h17, 8'b0110_0001}, // Aspect ratio 4:3 [1]=0. DE Generation ENabled [0]=1.
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// {8'h17, 8'b0110_0011}, // Aspect ratio 16:9 [1]=1. DE Generation ENabled [0]=1.
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{8'h17, 6'b011000, iAR, 1'b0}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
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{8'h18, 8'b0100_0110}, // CSC disabled [7]=0.
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// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
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// CSC Equation 3 [4:0] b00110.
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// {8'h3B, 8'b0000_1010}, // Pixel repetition [6:5] b00 AUTO. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
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{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
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// {8'h3B, 8'b0110_1010}, // Pixel repetition [6:5] b11 MANUAL. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
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// {8'h3C, 8'b0000_0110}, // VIC#6 480i-60, 2x clk, 4:3.
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// {8'h3C, 8'b0000_0001}, // VIC#1 VGA (640x480), 2x clk, 4:3.
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// {8'h3C, 8'b0000_0010}, // VIC#2 480p (720x480), 2x clk, 4:3.
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16'h4000, // General Control Packet Enable
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{8'h48, 8'b0000_1000}, // [6]=0 Normal bus order!
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// [5] DDR Alignment.
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// [4:3] b01 Data right justified (for YCbCr 422 input modes).
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16'h49A8, // ADI required Write.
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16'h4C00, // ADI required Write.
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{8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
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// {8'h55, 8'b0101_0000}, // [7] must be 0!. Set YCbCr 444 in AVinfo Frame [6:5], Set active format [4].
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// {8'h55, 8'b0011_0001}, // [7] must be 0!. Set YCbCr 422 in AVinfo Frame [6:5].
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// AVI InfoFrame Valid [4].
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// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
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// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
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// {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
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16'h7301,
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16'h9400, // HPD Interrupt disabled.
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16'h9902, // ADI required Write.
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16'h9B18, // ADI required Write.
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16'h9F00, // ADI required Write.
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{8'hA1, 8'b0100_0000}, // [6]=1 Monitor Sense Power Down DISabled.
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16'hA408, // ADI required Write.
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16'hA504, // ADI required Write.
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16'hA600, // ADI required Write.
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16'hA700, // ADI required Write.
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16'hA800, // ADI required Write.
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16'hA900, // ADI required Write.
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16'hAA00, // ADI required Write.
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16'hAB40, // ADI required Write.
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{8'hAF, 8'b0001_0110}, // [7]=0 HDCP Disabled.
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// [6:5] must be b00!
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// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
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// [3:2] must be b01!
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// [1]=1 HDMI Mode.
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// [0] must be b0!
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16'hB900, // ADI required Write.
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{8'hBA, 8'b0110_0000}, // [7:5] Input Clock delay...
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// b000 = -1.2ns.
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// b001 = -0.8ns.
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// b010 = -0.4ns.
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// b011 = No delay.
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// b100 = 0.4ns.
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// b101 = 0.8ns.
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// b110 = 1.2ns.
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// b111 = 1.6ns.
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16'hBB00, // ADI required Write.
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{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
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// 00 = HPD is from both HPD pin or CDC HPD
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// 01 = HPD is from CDC HPD
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// 10 = HPD is from HPD pin
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// 11 = HPD is always high
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16'hDE9C, // ADI required Write.
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16'hE460, // ADI required Write.
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16'hFA7D, // Nbr of times to search for good phase
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// (Audio stuff on Programming Guide, Page 66)...
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{8'h0A, 8'b0000_0000}, // [6:4] Audio Select. b000 = I2S.
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// [3:2] Audio Mode. (HBR stuff, leave at 00!).
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{8'h0B, 8'b0000_1110}, //
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{8'h0C, 8'b0000_0100}, // [7] 0 = Use sampling rate from I2S stream. 1 = Use samp rate from I2C Register.
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// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
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// [2] 1 = I2S0 Enable.
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// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
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{8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified.
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{8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits.
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{8'h15, ~audio_48k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
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// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
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// {8'h15, 8'b0010_0001}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
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// Input ID [3:0] b0001 (1) = 16, 20, 24 bit YCbCr 4:2:2 with Separate Syncs.
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// {8'h15, 8'b0010_0011}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
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// Input ID [3:0] b0011 (3) = 16, 20, 24 bit YCbCr 4:2:2 (2x Pixel Clock, with Separate Syncs).
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// Audio Clock Config
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16'h0100, //
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audio_48k ? 16'h0218 : 16'h0230, // Set N Value 12288/6144
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16'h0300, //
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16'h0701, //
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16'h0822, // Set CTS Value 74250
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16'h090A, //
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16'hFFFF // END
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};
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////////////////////////////////////////////////////////////////////
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endmodule |