Apple-2-Tools/Apple-II_MiSTer
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Initial port.

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sorgelig 2017-11-04 21:21:27 +08:00
commit 1ee0b6e2dc
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.gitignore vendored Normal file
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db
greybox_tmp
incremental_db
output_files
simulation
hc_output
scaler
hps_isw_handoff
vip
*_sim
.qsys_edit
PLLJ_PLLSPE_INFO.txt
*.bak
*.orig
*.rej
*.qdf
*.rpt
*.smsg
*.summary
*.done
*.jdi
*.pin
*.sof
*.qws
*.ppf
*.ddb
build_id.v
c5_pin_model_dump.txt
*.sopcinfo
*.csv
*.f
*.cmp
*.sip
*.spd
*.bsf
*~
*.xml

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
# Date created = 01:53:32 April 20, 2017
#
# -------------------------------------------------------------------------- #
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag_lite.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QIP_FILE sys/sysmem.qip
set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd
set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd
set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd
set_global_assignment -name VHDL_FILE mockingboard/m6522.vhd
set_global_assignment -name VERILOG_FILE ramcard.v
set_global_assignment -name VHDL_FILE spram.vhd
set_global_assignment -name VHDL_FILE keyboard.vhd
set_global_assignment -name VHDL_FILE timing_generator.vhd
set_global_assignment -name VHDL_FILE character_rom.vhd
set_global_assignment -name VHDL_FILE video_generator.vhd
set_global_assignment -name VHDL_FILE cpu6502.vhd
set_global_assignment -name VHDL_FILE apple2.vhd
set_global_assignment -name VHDL_FILE disk_ii.vhd
set_global_assignment -name VHDL_FILE disk_ii_rom.vhd
set_global_assignment -name VHDL_FILE vga_controller.vhd
set_global_assignment -name VHDL_FILE PS2_Ctrl.vhd
set_global_assignment -name VHDL_FILE roms.vhd
set_global_assignment -name VHDL_FILE apple2_top.vhd
set_global_assignment -name SYSTEMVERILOG_FILE Apple-II.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@ -0,0 +1,17 @@
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Synthesized away node \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[2\]\"" { } { } 0 14320 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(129): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(134): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "sysmem_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

32
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@ -0,0 +1,32 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "Apple-II"
PROJECT_REVISION = "Apple-II-lite"

376
Apple-II.qsf Normal file
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@ -0,0 +1,376 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
# Date created = 01:53:32 April 20, 2017
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QIP_FILE sys/vip.qip
set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd
set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd
set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd
set_global_assignment -name VHDL_FILE mockingboard/m6522.vhd
set_global_assignment -name VERILOG_FILE ramcard.v
set_global_assignment -name VHDL_FILE spram.vhd
set_global_assignment -name VHDL_FILE keyboard.vhd
set_global_assignment -name VHDL_FILE timing_generator.vhd
set_global_assignment -name VHDL_FILE character_rom.vhd
set_global_assignment -name VHDL_FILE video_generator.vhd
set_global_assignment -name VHDL_FILE cpu6502.vhd
set_global_assignment -name VHDL_FILE apple2.vhd
set_global_assignment -name VHDL_FILE disk_ii.vhd
set_global_assignment -name VHDL_FILE disk_ii_rom.vhd
set_global_assignment -name VHDL_FILE vga_controller.vhd
set_global_assignment -name VHDL_FILE PS2_Ctrl.vhd
set_global_assignment -name VHDL_FILE roms.vhd
set_global_assignment -name VHDL_FILE apple2_top.vhd
set_global_assignment -name SYSTEMVERILOG_FILE "Apple-II.sv"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

51
Apple-II.srf Normal file
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@ -0,0 +1,51 @@
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

307
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//============================================================================
// Apple II+
//
// Port to MiSTer
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [43:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [7:0] VIDEO_ARX,
output [7:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status ORed with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
input TAPE_IN,
// SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE
);
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign LED_USER = led;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
`include "build_id.v"
parameter CONF_STR = {
"Apple-II;;",
"-;",
"S,NIB;",
"-;",
"O1,Aspect ratio,4:3,16:9;",
"O23,Display,Color,B&W,Green,Amber;",
"-;",
"O4,Mocking board,Yes,No;",
"-;",
"T6,Reset;",
"J,Fire 1,Fire 2;",
"V,v1.01.",`BUILD_DATE
};
///////////////// CLOCKS ////////////////////////
wire clk_ram, clk_sys, clk_fdd, clk_vid;
wire pll_locked;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_vid),
.outclk_1(clk_sys),
.locked(pll_locked)
);
///////////////// HPS ///////////////////////////
wire [31:0] status;
wire [1:0] buttons;
wire [15:0] joystick_0, joystick_1;
wire [15:0] joystick_a0, joystick_a1;
wire [5:0] joy = (joystick_0[5:0] | joystick_1[5:0]) & {2'b11, {4{~joya_en}}};
wire [15:0] joya = joystick_a0 ? joystick_a0 : joystick_a1;
wire joya_en = |joya;
wire ps2_kbd_clk_out;
wire ps2_kbd_data_out;
reg [31:0] sd_lba;
reg sd_rd;
wire sd_ack;
wire [8:0] sd_buff_addr;
wire [7:0] sd_buff_dout;
wire sd_buff_wr;
wire img_mounted;
wire [63:0] img_size;
hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str(CONF_STR),
.buttons(buttons),
.status(status),
.sd_lba(sd_lba),
.sd_rd(sd_rd),
.sd_wr(0),
.sd_ack(sd_ack),
.sd_buff_addr(sd_buff_addr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din(0),
.sd_buff_wr(sd_buff_wr),
.img_mounted(img_mounted),
.img_size(img_size),
.ioctl_wait(0),
.ps2_kbd_clk_out(ps2_kbd_clk_out),
.ps2_kbd_data_out(ps2_kbd_data_out),
.joystick_0(joystick_0),
.joystick_1(joystick_1),
.joystick_analog_0(joystick_a0),
.joystick_analog_1(joystick_a1)
);
///////////////// RESET /////////////////////////
wire reset = RESET | status[0] | buttons[1] | status[6];
///////////////////////////////////////////////////
wire [7:0] audio_l, audio_r;
wire speaker;
assign AUDIO_L = {1'b0, audio_l, 7'd0} + {2'b0, speaker, 13'd0};
assign AUDIO_R = {1'b0, audio_r, 7'd0} + {2'b0, speaker, 13'd0};
assign AUDIO_S = 0;
assign CLK_VIDEO = clk_vid;
assign CE_PIXEL = 1;
wire led;
apple2_top apple2_top
(
.CLK_28M(clk_vid),
.CLK_14M(clk_sys),
.CPU_WAIT(cpu_wait),
.reset_in(reset),
.VGA_DE(VGA_DE),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.SCREEN_MODE(status[3:2]),
.AUDIO_L(audio_l),
.AUDIO_R(audio_r),
.SPEAKER(speaker),
.ps2Clk(ps2_kbd_clk_out),
.ps2Data(ps2_kbd_data_out),
.joy(joy),
.joy_an(joya),
.mb_enabled(~status[4]),
.TRACK(track),
.TRACK_RAM_ADDR({track_sec, sd_buff_addr}),
.TRACK_RAM_DI(sd_buff_dout),
.TRACK_RAM_WE(sd_buff_wr),
.ram_addr(ram_addr),
.ram_dout(ram_dout),
.ram_din(ram_din),
.ram_we(ram_we),
.LED(led)
);
wire [17:0] ram_addr;
reg [7:0] ram_dout;
wire [7:0] ram_din;
wire ram_we;
reg [7:0] ram[262144]; //om-nom-nom :)
always @(posedge clk_sys) begin
if(ram_we) begin
ram[ram_addr] <= ram_din;
ram_dout <= ram_din;
end else begin
ram_dout <= ram[ram_addr];
end
end
wire [5:0] track;
reg [3:0] track_sec;
reg cpu_wait = 0;
always @(posedge clk_sys) begin
reg [2:0] state = 0;
reg [5:0] cur_track;
reg mounted = 0;
reg old_ack = 0;
old_ack <= sd_ack;
mounted <= mounted | img_mounted;
case(state)
0: if((cur_track != track) || (mounted && ~img_mounted)) begin
cur_track <= track;
mounted <= 0;
if(img_size) begin
track_sec <= 0;
sd_lba <= 13 * track;
state <= 1;
sd_rd <= 1;
cpu_wait <= 1;
end
end
1: if(~old_ack & sd_ack) begin
if(track_sec >= 12) sd_rd <= 0;
sd_lba <= sd_lba + 1'd1;
end else if(old_ack & ~sd_ack) begin
track_sec <= track_sec + 1'd1;
if(~sd_rd) state <= 0;
cpu_wait <= 0;
end
endcase
end
endmodule

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-- PS2_Ctrl.vhd
-- ------------------------------------------------
-- Simplified PS/2 Controller (kbd, mouse...)
-- ------------------------------------------------
-- Only the Receive function is implemented !
-- (c) ALSE. http://www.alse-fr.com
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
-- --------------------------------------
Entity PS2_Ctrl is
-- --------------------------------------
generic (FilterSize : positive := 8);
port( Clk : in std_logic; -- System Clock
Reset : in std_logic; -- System Reset
PS2_Clk : in std_logic; -- Keyboard Clock Line
PS2_Data : in std_logic; -- Keyboard Data Line
DoRead : in std_logic; -- From outside when reading the scan code
Scan_Err : out std_logic; -- To outside : Parity or Overflow error
Scan_DAV : out std_logic; -- To outside when a scan code has arrived
Scan_Code : out unsigned(7 downto 0) -- Eight bits Data Out
);
end PS2_Ctrl;
-- --------------------------------------
Architecture ALSE_RTL of PS2_Ctrl is
-- --------------------------------------
-- (c) ALSE. http://www.alse-fr.com
-- Author : Bert Cuzeau.
-- Fully synchronous solution, same Filter on PS2_Clk.
-- Still as compact as "Plain_wrong"...
-- Possible improvement : add TIMEOUT on PS2_Clk while shifting
-- Note: PS2_Data is resynchronized though this should not be
-- necessary (qualified by Fall_Clk and does not change at that time).
-- Note the tricks to correctly interpret 'H' as '1' in RTL simulation.
signal PS2_Datr : std_logic;
subtype Filter_t is std_logic_vector(FilterSize-1 downto 0);
signal Filter : Filter_t;
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned(3 downto 0);
signal Parity : std_logic;
signal Scan_DAVi : std_logic;
signal S_Reg : unsigned(8 downto 0);
signal PS2_Clk_f : std_logic;
Type State_t is (Idle, Shifting);
signal State : State_t;
begin
Scan_DAV <= Scan_DAVi;
-- This filters digitally the raw clock signal coming from the keyboard :
-- * Eight consecutive PS2_Clk=1 makes the filtered_clock go high
-- * Eight consecutive PS2_Clk=0 makes the filtered_clock go low
-- Implies a (FilterSize+1) x Tsys_clock delay on Fall_Clk wrt Data
-- Also in charge of the re-synchronization of PS2_Data
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t'(others=>'1') then
PS2_Clk_f <= '1';
elsif Filter = Filter_t'(others=>'0') then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
-- This simple State Machine reads in the Serial Data
-- coming from the PS/2 peripheral.
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Parity <= '0';
Scan_Davi <= '0';
Scan_Err <= '0';
elsif rising_edge (Clk) then
if DoRead='1' then
Scan_Davi <= '0'; -- note: this assgnmnt can be overriden
end if;
case State is
when Idle =>
Parity <= '0';
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
Scan_Err <= '0';
State <= Shifting;
end if;
when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
-- Error is (wrong Parity) or (Stop='0') or Overflow
Scan_Err <= (not Parity) or (not PS2_Datr) or Scan_DAVi;
Scan_Davi <= '1';
Scan_Code <= S_Reg(7 downto 0);
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
Parity <= Parity xor PS2_Datr;
end if;
when others => -- never reached
State <= Idle;
end case;
--Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !
end if;
end process;
end ALSE_RTL;

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This is MiSTer port of Apple II+ from MiST.
Bellow is readme from MiST. Functionality is identical.
---------------------------------------------------------------------------
This the MiST port of a reconstruction of an 1980s-era Apple ][+ implemented in VHDL for FPGAs.
Original for the DE2: http://www1.cs.columbia.edu/~sedwards/apple2fpga/
Port for the MiST: http://ws0.org/tag/apple2/
Features:
- disk loading via osd (no write support yet)
- joystick support
- scanlines
- color, amber, green and black&white monitor
- language card in slot 0
- Saturn 128k RAM expansion in slot 5 (get the utility disks from here: http://apple2online.com/index.php?p=1_28)
- Mockingboard model A (two AY-3-8913 chips for six audio channels) in slot 4
On the "Apple ][" boot screen open the OSD with F12 and choose a nibblelized disk. It will boot
the disk automatically. Use dsk2nib to convert AppleII disk images to .nib images.
The disk emulation is read only.
If you press reset (the right button on the MiST) you'll enter Applesoft with the ] prompt.
From here you have some limited commands. See: http://www.landsnail.com/a2ref.htm
If you want to boot another disk choose a .nib image via the osd and type the following:
]PR#6
or
]CALL -151
*C600G
The call command will enter the Monitor. Type the call a second time if the * prompt won't
show the first time.
At the Monitor you can also type 6 and then Ctrl-P followed by return.
See http://vectronicsappleworld.com/appleii/dos.html#bootdos
---------------------------------------------------------------------------
Pre-MiST ReadMe for historical purpose.
---------------------------------------------------------------------------
This is a reconstruction of an 1980s-era Apple ][+ implemented in VHDL for
FPGAs.
Stephen A. Edwards, sedwards@cs.columbia.edu
http://www1.cs.columbia.edu/~sedwards
------------------------------
The current implementation uses the Altera DE2 board and takes advantage
of its off-chip SRAM, VGA DAC, SD card, audio CODEC, and PS/2 keyboard
interface.
It was designed to be fairly easy to port: the apple2.vhd file should
be implementation-agnostic: it only assumes the external availability
of 48K of RAM and a keyboard.
It contains a simple read-only Disk II emulator that expects
"nibblized" disk images written raw onto an SD or MMC card (i.e., it
does not use a FAT or any other type of filesystem).
The VGA controller (not part of an original Apple) doubles each line
and interprets the Apple's NTSC-compatible color signals to produce a color
640 X 480 VGA display with non-standard dot timing.
------------------------------
To compile under Altera's Quartus software, open the apple2fpga.qpf
project file and compile.
------------------------------
VHDL files, in order of elaboration:
timing_generator.vhd Timing signal generation, video counters
character_rom.vhd The beautiful 5 X 8 uppercase-only text font
video_generator.vhd Text, lores, and hires mode shift registers
main_roms.vhd D000-FFFF ROMs: Applesoft and the Monitor
cpu6502.vhd The 6502 CPU core
apple2.vhd Top-level of the Apple: mostly address decode
disk_ii_rom.vhd C600-C6FF ROM: Disk II bootstrap ROM
disk_ii.vhd Read-only Disk II emulator
vga_controller.vhd NTSC-to-VGA color interpolation, line doubler
PS2_Ctrl.vhd Low-level PS/2 keyboard interface
keyboard.vhd PS/2 keyboard-to-Apple interface
spi_controller.vhd SD/MMC card controller: reads raw tracks
i2c_controller.vhd Simple I2C bus driver; initializes the codec
wm8731_audio.vhd Controller for the Wolfson WM8731 audio codec
DE2_TOP.vhd Top-level entity for the Altera DE2 board
CLK28MPLL.vhd Altera-specific configuration for 28 MHz PLL
Other files:
dsk2nib.c Converts a 140K .dsk image file to the raw 228K
.nib format used by the Disk II emulator
makenibs A shell (e.g., bash) script that assembles
collections of .dsk files into a file suitable
for directly writing onto an SD card
rom2vhdl Script to convert raw ROM files into
synthesizable VHDL code. Used to produce main_roms.vhd
apple2fpga.qpf Project file for Altera's Quartus
DE2_TOP.qsf Mostly pin assignments for Altera's Quartus
DE2_TOP.sof A compiled bitstream for the DE2 board: the
result of compiling all the VHDL files in
Quartus; suitable for programming if you have a
DE2 board.
dos33master.nib Bootable disk image: Apple DOS 3.3 system master
bios.a65 6502 assembly source for a "fake" BIOS
bios.rom Binary data for the "fake" BIOS
Makefile Rules for creating the .zip, .vhd files, etc.
------------------------------
Disk images
The system expects a sequence of "nibblized" (227K) disk images on the
SD card starting at block 0. Switches on the DE2 board selects which
image appears to be in the drive; the image number is displayed in hex
on two of the seven-segment displays.
Most Apple II disk images are in 140K .dsk files, which stores only
the disk's logical data, i.e., is not encoded. dsk2nib.c is a small C
program that expands .dsk files to .nib files.
I used the "makenibs" script to find all the .dsk files in a tree of
directories, assemble them into an image suitable for downloading to
the SD card, and print an image number/file name cross-listing.
To write .nib images to an SD/MMC card under Linux, I use
dd if=dos33master.nib of=/dev/sdd
Of course, your card may appear as something other than /dev/sdd.
------------------------------
ROMs
This archive does NOT include a copy of the Apple ][+'s ROMs, which
are copyright Apple Computer. Instead, it includes a very trivial
BIOS that beeps, displays a text screen, then cycles through some
lores and hires graphics patterns when keys are pressed. This should
be enough to verify the graphics, sound, and keyboard are working (but
not the disk emulator). Source for this BIOS is in the bios.a65 file,
which I assembled using the xa65 cross-assembler.
The system requires two ROM images: a 12K image of the system roms
(memory from 0xD000 - 0xFFFF) and a 256-byte image of the Disk II
controller bootstrap ROM (memory from 0xc600 - 0xc6ff if the card is
in the usual slot 6).
Once you obtain them, run the "rom2vhdl" script to convert the binary
files into .vhd files that hold the data. The Makefile contains rules
for doing this.
------------------------------
Credits:
Peter Wendrich supplied the 6502 core:
-- cpu65xx_fast.vhdl, part of FPGA-64, is made available strictly for personal
-- educational purposes. Distributed with apple2fgpa with permission.
--
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com).
-- All rights reserved.
-- http://www.syntiac.com/fpga64.html
The low-level PS/2 keyboard controller is from ALSE:
-- PS2_Ctrl.vhd
-- ------------------------------------------------
-- Simplified PS/2 Controller (kbd, mouse...)
-- ------------------------------------------------
-- Only the Receive function is implemented !
-- (c) ALSE. http://www.alse-fr.com
I adapted the Apple ][ keyboard emulation from Alex Freed's FPGApple:
http://mirrow.com/FPGApple/

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-------------------------------------------------------------------------------
--
-- Top level of an Apple ][+
--
-- Stephen A. Edwards, sedwards@cs.columbia.edu
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity apple2 is
port (
CLK_14M : in std_logic; -- 14.31818 MHz master clock
CLK_2M : out std_logic;
CPU_WAIT : in std_logic;
PRE_PHASE_ZERO : out std_logic;
FLASH_CLK : in std_logic; -- approx. 2 Hz flashing char clock
reset : in std_logic;
ADDR : out unsigned(15 downto 0); -- CPU address
ram_addr : out unsigned(17 downto 0); -- RAM address
D : out unsigned(7 downto 0); -- Data to RAM
ram_do : in unsigned(7 downto 0); -- Data from RAM
PD : in unsigned(7 downto 0); -- Data to CPU from peripherals
ram_we : out std_logic; -- RAM write enable
VIDEO : out std_logic;
COLOR_LINE : out std_logic;
HBL : out std_logic;
VBL : out std_logic;
LD194 : out std_logic;
K : in unsigned(7 downto 0); -- Keyboard data
READ_KEY : out std_logic; -- Processor has read key
AN : out std_logic_vector(3 downto 0); -- Annunciator outputs
-- GAMEPORT input bits:
-- 7 6 5 4 3 2 1 0
-- pdl3 pdl2 pdl1 pdl0 pb3 pb2 pb1 casette
GAMEPORT : in std_logic_vector(7 downto 0);
PDL_STROBE : out std_logic; -- Pulses high when C07x read
STB : out std_logic; -- Pulses high when C04x read
IO_SELECT : out std_logic_vector(7 downto 0);
DEVICE_SELECT : out std_logic_vector(7 downto 0);
pcDebugOut : out unsigned(15 downto 0);
opcodeDebugOut : out unsigned(7 downto 0);
laudio : out std_logic_vector(7 downto 0);
raudio : out std_logic_vector(7 downto 0);
mb_enabled : in std_logic;
speaker : out std_logic -- One-bit speaker output
);
end apple2;
architecture rtl of apple2 is
component ramcard is
port ( mclk28: in std_logic;
reset_in: in std_logic;
addr: in std_logic_vector(15 downto 0);
ram_addr: out std_logic_vector(17 downto 0);
we: in std_logic;
card_ram_we: out std_logic;
card_ram_rd: out std_logic;
bank1: out std_logic
);
end component;
-- Clocks
signal CLK_7M : std_logic;
signal Q3, RAS_N, CAS_N, AX : std_logic;
signal PHASE_ZERO, PRE_PHASE_ZERO_sig : std_logic;
signal COLOR_REF : std_logic;
-- From the timing generator
signal VIDEO_ADDRESS : unsigned(15 downto 0);
signal LDPS_N : std_logic;
signal H0, VA, VB, VC, V2, V4 : std_logic;
signal BLANK, LD194_I : std_logic;
signal HIRES : std_logic; -- from video generator B11 p6
-- Soft switches
signal soft_switches : std_logic_vector(7 downto 0) := "00000000";
signal TEXT_MODE : std_logic;
signal MIXED_MODE : std_logic;
signal PAGE2 : std_logic;
signal HIRES_MODE : std_logic;
-- CPU signals
signal D_IN : unsigned(7 downto 0);
signal D_OUT: unsigned(7 downto 0);
signal A : unsigned(15 downto 0);
signal we : std_logic;
-- Main ROM signals
signal rom_out : unsigned(7 downto 0);
signal rom_addr : unsigned(13 downto 0);
-- Address decoder signals
signal RAM_SELECT : std_logic := '1';
signal KEYBOARD_SELECT : std_logic := '0';
signal SPEAKER_SELECT : std_logic;
signal SOFTSWITCH_SELECT : std_logic;
signal ROM_SELECT : std_logic;
signal GAMEPORT_SELECT : std_logic;
signal IO_STROBE : std_logic;
-- Speaker signal
signal speaker_sig : std_logic := '0';
signal DL : unsigned(7 downto 0); -- Latched RAM data
-- ramcard
signal card_addr : unsigned(17 downto 0);
signal card_ram_rd : std_logic;
signal card_ram_we : std_logic;
signal ram_card_read : std_logic;
signal ram_card_write : std_logic;
signal psg_irq_n : std_logic;
signal psg_do : unsigned(7 downto 0);
signal ioselect : std_logic_vector(7 downto 0);
signal devselect : std_logic_vector(7 downto 0);
signal R_W_n : std_logic;
begin
CLK_2M <= Q3;
PRE_PHASE_ZERO <= PRE_PHASE_ZERO_sig;
ram_addr <= card_addr when PHASE_ZERO = '1' else "00" & VIDEO_ADDRESS;
ram_we <= ((we and RAM_SELECT) or (we and ram_card_write)) when PHASE_ZERO = '1' else '0';
-- Latch RAM data on the rising edge of RAS
RAM_data_latch : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if AX = '1' and CAS_N = '0' and RAS_N = '0' then
DL <= ram_do;
end if;
end if;
end process;
ADDR <= A;
D <= D_OUT;
IO_SELECT <= ioselect;
DEVICE_SELECT <= devselect;
-- Address decoding
rom_addr <= (A(13) and A(12)) & (not A(12)) & A(11 downto 0);
address_decoder: process (A)
begin
ROM_SELECT <= '0';
RAM_SELECT <= '0';
KEYBOARD_SELECT <= '0';
READ_KEY <= '0';
SPEAKER_SELECT <= '0';
SOFTSWITCH_SELECT <= '0';
GAMEPORT_SELECT <= '0';
PDL_STROBE <= '0';
STB <= '0';
ioselect <= (others => '0');
devselect <= (others => '0');
IO_STROBE <= '0';
case A(15 downto 14) is
when "00" | "01" | "10" => -- 0000 - BFFF
RAM_SELECT <= '1';
when "11" => -- C000 - FFFF
case A(13 downto 12) is
when "00" => -- C000 - CFFF
case A(11 downto 8) is
when x"0" => -- C000 - C0FF
case A(7 downto 4) is
when x"0" => -- C000 - C00F
KEYBOARD_SELECT <= '1';
when x"1" => -- C010 - C01F
READ_KEY <= '1';
when x"3" => -- C030 - C03F
SPEAKER_SELECT <= '1';
when x"4" =>
STB <= '1';
when x"5" => -- C050 - C05F
SOFTSWITCH_SELECT <= '1';
when x"6" => -- C060 - C06F
GAMEPORT_SELECT <= '1';
when x"7" => -- C070 - C07F
PDL_STROBE <= '1';
when x"8" | x"9" | x"A" | -- C080 - C0FF
x"B" | x"C" | x"D" | x"E" | x"F" =>
devselect(TO_INTEGER(A(6 downto 4))) <= '1';
when others => null;
end case;
when x"1" | x"2" | x"3" | -- C100 - C7FF
x"4" | x"5" | x"6" | x"7" =>
ioselect(TO_INTEGER(A(10 downto 8))) <= '1';
when x"8" | x"9" | x"A" | -- C800 - CFFF
x"B" | x"C" | x"D" | x"E" | x"F" =>
IO_STROBE <= '1';
when others => null;
end case;
when "01" | "10" | "11" => -- D000 - FFFF
ROM_SELECT <= '1';
when others =>
null;
end case;
when others => null;
end case;
end process address_decoder;
speaker_ctrl: process (Q3)
begin
if rising_edge(Q3) then
if PRE_PHASE_ZERO_sig = '1' and SPEAKER_SELECT = '1' then
speaker_sig <= not speaker_sig;
end if;
end if;
end process speaker_ctrl;
softswitches: process (Q3)
begin
if rising_edge(Q3) then
if PRE_PHASE_ZERO_sig = '1' and SOFTSWITCH_SELECT = '1' then
soft_switches(TO_INTEGER(A(3 downto 1))) <= A(0);
end if;
end if;
end process softswitches;
TEXT_MODE <= soft_switches(0);
MIXED_MODE <= soft_switches(1);
PAGE2 <= soft_switches(2);
HIRES_MODE <= soft_switches(3);
AN <= soft_switches(7 downto 4);
speaker <= speaker_sig;
D_IN <= DL when RAM_SELECT = '1' or ram_card_read = '1' else -- RAM
K when KEYBOARD_SELECT = '1' else -- Keyboard
GAMEPORT(TO_INTEGER(A(2 downto 0))) & "0000000" -- Gameport
when GAMEPORT_SELECT = '1' else
rom_out when ROM_SELECT = '1' else -- ROMs
psg_do when (devselect(4) = '1' or ioselect(4) = '1') and mb_enabled = '1' else
PD; -- Peripherals
LD194 <= LD194_I;
timing : entity work.timing_generator port map (
CLK_14M => CLK_14M,
CLK_7M => CLK_7M,
CAS_N => CAS_N,
RAS_N => RAS_N,
Q3 => Q3,
AX => AX,
PHI0 => PHASE_ZERO,
PRE_PHI0 => PRE_PHASE_ZERO_sig,
COLOR_REF => COLOR_REF,
TEXT_MODE => TEXT_MODE,
PAGE2 => PAGE2,
HIRES => HIRES,
VIDEO_ADDRESS => VIDEO_ADDRESS,
H0 => H0,
VA => VA,
VB => VB,
VC => VC,
V2 => V2,
V4 => V4,
VBL => VBL,
HBL => HBL,
BLANK => BLANK,
LDPS_N => LDPS_N,
LD194 => LD194_I);
video_display : entity work.video_generator port map (
CLK_14M => CLK_14M,
CLK_7M => CLK_7M,
AX => AX,
CAS_N => CAS_N,
TEXT_MODE => TEXT_MODE,
PAGE2 => PAGE2,
HIRES_MODE => HIRES_MODE,
MIXED_MODE => MIXED_MODE,
H0 => H0,
VA => VA,
VB => VB,
VC => VC,
V2 => V2,
V4 => V4,
BLANK => BLANK,
DL => DL,
LDPS_N => LDPS_N,
LD194 => LD194_I,
FLASH_CLK => FLASH_CLK,
HIRES => HIRES,
VIDEO => VIDEO,
COLOR_LINE => COLOR_LINE);
cpu : entity work.cpu65xx
generic map (
pipelineOpcode => false,
pipelineAluMux => false,
pipelineAluOut => false)
port map (
clk => Q3,
enable => (not PRE_PHASE_ZERO_sig) and (not CPU_WAIT),
reset => reset,
nmi_n => '1',
irq_n => psg_irq_n,
di => D_IN,
do => D_OUT,
addr => A,
we => we,
debugPc => pcDebugOut,
debugOpcode => opcodeDebugOut
);
-- Original Apple had asynchronous ROMs. We use a synchronous ROM
-- that needs its address earlier, hence the odd clock.
roms : entity work.roms port map (
address => std_logic_vector(rom_addr),
clock => CLK_14M,
unsigned(q) => rom_out);
-- ramcard
ram_card_D: component ramcard
port map
(
mclk28 => CLK_14M,
reset_in => reset,
addr => std_logic_vector(A),
unsigned(ram_addr) => card_addr,
we => we,
card_ram_we => card_ram_we,
card_ram_rd => card_ram_rd,
bank1 => open
);
ram_card_read <= ROM_SELECT and card_ram_rd;
ram_card_write <= ROM_SELECT and card_ram_we;
mb : work.mockingboard
port map (
CLK_VIA => not Q3,
CLK_PSG => not PHASE_ZERO,
I_P2_H => not PHASE_ZERO,
I_RESET_L => not reset,
I_ENA_H => mb_enabled,
I_ADDR => std_logic_vector(A)(7 downto 0),
I_DATA => std_logic_vector(D_OUT),
unsigned(O_DATA) => psg_do,
I_RW_L => not we,
I_IOSEL_L => not ioselect(4),
O_IRQ_L => psg_irq_n,
O_AUDIO_L => laudio,
O_AUDIO_R => raudio
);
end rtl;

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--
--
-- Apple II+ toplevel for the MiST board
-- https://github.com/wsoltys/mist_apple2
--
-- Copyright (c) 2014 W. Soltys <wsoltys@gmail.com>
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity apple2_top is port
(
-- Clocks
CLK_28M : in std_logic;
CLK_14M : in std_logic;
CPU_WAIT : in std_logic;
reset_in : in std_logic;
-- VGA output
VGA_DE : out std_logic;
VGA_CLK : out std_logic;
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_G : out std_logic_vector(7 downto 0);
VGA_B : out std_logic_vector(7 downto 0);
SCREEN_MODE : in std_logic_vector(1 downto 0); -- 00: Color, 01: B&W, 10:Green, 11: Amber
-- Audio
AUDIO_L : out std_logic_vector(7 downto 0);
AUDIO_R : out std_logic_vector(7 downto 0);
SPEAKER : out std_logic;
ps2Clk : in std_logic;
ps2Data : in std_logic;
joy : in std_logic_vector(5 downto 0);
joy_an : in std_logic_vector(15 downto 0);
-- mocking board
mb_enabled : in std_logic;
-- disk control
TRACK : out unsigned(5 downto 0);
TRACK_RAM_ADDR : in unsigned(12 downto 0);
TRACK_RAM_DI : in unsigned(7 downto 0);
TRACK_RAM_WE : in std_logic;
-- main RAM
ram_addr : out std_logic_vector(17 downto 0);
ram_dout : in std_logic_vector(7 downto 0);
ram_din : out std_logic_vector(7 downto 0);
ram_we : out std_logic;
-- LEDG
LED : out std_logic
);
end apple2_top;
architecture datapath of apple2_top is
signal CLK_2M, PRE_PHASE_ZERO: std_logic;
signal IO_SELECT, DEVICE_SELECT : std_logic_vector(7 downto 0);
signal ADDR : unsigned(15 downto 0);
signal D, PD: unsigned(7 downto 0);
signal we_ram : std_logic;
signal VIDEO, HBL, VBL, LD194 : std_logic;
signal COLOR_LINE : std_logic;
signal COLOR_LINE_CONTROL : std_logic;
signal GAMEPORT : std_logic_vector(7 downto 0);
signal cpu_pc : unsigned(15 downto 0);
signal K : unsigned(7 downto 0);
signal read_key : std_logic;
signal flash_clk : unsigned(22 downto 0) := (others => '0');
signal power_on_reset : std_logic := '1';
signal reset : std_logic;
signal a_ram: unsigned(17 downto 0);
signal joyx : std_logic;
signal joyy : std_logic;
signal pdl_strobe : std_logic;
begin
reset <= power_on_reset;
power_on : process(CLK_14M, reset_in)
begin
if reset_in = '1' then
power_on_reset <= '1';
elsif rising_edge(CLK_14M) then
if flash_clk(22) = '1' then
power_on_reset <= '0';
end if;
end if;
end process;
-- In the Apple ][, this was a 555 timer
flash_clkgen : process (CLK_14M, reset_in)
begin
if reset_in = '1' then
flash_clk <= (others=>'0');
elsif rising_edge(CLK_14M) then
flash_clk <= flash_clk + 1;
end if;
end process;
-- Paddle buttons
-- GAMEPORT input bits:
-- 7 6 5 4 3 2 1 0
-- pdl3 pdl2 pdl1 pdl0 pb3 pb2 pb1 casette
GAMEPORT <= "00" & joyy & joyx & "0" & joy(5) & joy(4) & "0";
process(CLK_2M, pdl_strobe)
variable cx, cy : integer range -100 to 5800 := 0;
begin
if rising_edge(CLK_2M) then
if cx > 0 then
cx := cx -1;
joyx <= '1';
else
joyx <= '0';
end if;
if cy > 0 then
cy := cy -1;
joyy <= '1';
else
joyy <= '0';
end if;
if pdl_strobe = '1' then
cx := 2800+(22*to_integer(signed(joy_an(7 downto 0))));
cy := 2800+(22*to_integer(signed(joy_an(15 downto 8)))); -- max 5650
if cx < 0 then
cx := 0;
elsif cx >= 5590 then
cx := 5650;
end if;
if cy < 0 then
cy := 0;
elsif cy >= 5590 then
cy := 5650;
end if;
end if;
end if;
end process;
COLOR_LINE_CONTROL <= COLOR_LINE and not (SCREEN_MODE(0) or SCREEN_MODE(1)); -- Color or B&W mode
-- Simulate power up on cold reset to go to the disk boot routine
ram_we <= we_ram; -- when reset_in = '0' else '1';
ram_addr <= std_logic_vector(a_ram); -- when reset_in = '0' else std_logic_vector(to_unsigned(1012,ram_addr'length)); -- $3F4
ram_din <= std_logic_vector(D); -- when reset_in = '0' else "00000000";
core : entity work.apple2 port map (
CLK_14M => CLK_14M,
CLK_2M => CLK_2M,
CPU_WAIT => CPU_WAIT,
PRE_PHASE_ZERO => PRE_PHASE_ZERO,
FLASH_CLK => flash_clk(22),
reset => reset,
ADDR => ADDR,
ram_addr => a_ram,
D => D,
ram_do => unsigned(ram_dout),
PD => PD,
ram_we => we_ram,
VIDEO => VIDEO,
COLOR_LINE => COLOR_LINE,
HBL => HBL,
VBL => VBL,
LD194 => LD194,
K => K,
read_key => read_key,
AN => open,
GAMEPORT => GAMEPORT,
PDL_strobe => pdl_strobe,
IO_SELECT => IO_SELECT,
DEVICE_SELECT => DEVICE_SELECT,
pcDebugOut => cpu_pc,
speaker => SPEAKER,
laudio => AUDIO_L,
raudio => AUDIO_R,
mb_enabled => mb_enabled
);
vga : entity work.vga_controller port map (
CLK_28M => CLK_28M,
VIDEO => VIDEO,
COLOR_LINE => COLOR_LINE_CONTROL,
SCREEN_MODE => SCREEN_MODE,
HBL => HBL,
VBL => VBL,
LD194 => LD194,
VGA_CLK => VGA_CLK,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_DE => VGA_DE,
std_logic_vector(VGA_R) => VGA_R,
std_logic_vector(VGA_G) => VGA_G,
std_logic_vector(VGA_B) => VGA_B
);
keyboard : entity work.keyboard port map (
PS2_Clk => ps2Clk,
PS2_Data => ps2Data,
CLK_14M => CLK_14M,
reset => reset,
reads => read_key,
K => K
);
disk : entity work.disk_ii port map (
CLK_14M => CLK_14M,
CLK_2M => CLK_2M,
PRE_PHASE_ZERO => PRE_PHASE_ZERO,
IO_SELECT => IO_SELECT(6),
DEVICE_SELECT => DEVICE_SELECT(6),
RESET => reset,
A => ADDR,
D_IN => D,
D_OUT => PD,
TRACK => TRACK,
TRACK_ADDR => open,
D1_ACTIVE => LED,
D2_ACTIVE => open,
ram_write_addr => TRACK_RAM_ADDR,
ram_di => TRACK_RAM_DI,
ram_we => TRACK_RAM_WE
);
end datapath;

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character_rom.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity character_rom is
port (
addr : in unsigned(8 downto 0);
clk : in std_logic;
dout : out unsigned(4 downto 0));
end character_rom;
architecture rtl of character_rom is
type rom_array is array (0 to 511) of unsigned(4 downto 0);
constant ROM : rom_array := (
"01110",
"10001",
"10101",
"11101",
"01101",
"00001",
"11110",
"00000",
"00100",
"01010",
"10001",
"10001",
"11111",
"10001",
"10001",
"00000",
"01111",
"10001",
"10001",
"01111",
"10001",
"10001",
"01111",
"00000",
"01110",
"10001",
"00001",
"00001",
"00001",
"10001",
"01110",
"00000",
"01111",
"10001",
"10001",
"10001",
"10001",
"10001",
"01111",
"00000",
"11111",
"00001",
"00001",
"01111",
"00001",
"00001",
"11111",
"00000",
"11111",
"00001",
"00001",
"01111",
"00001",
"00001",
"00001",
"00000",
"11110",
"00001",
"00001",
"00001",
"11001",
"10001",
"11110",
"00000",
"10001",
"10001",
"10001",
"11111",
"10001",
"10001",
"10001",
"00000",
"01110",
"00100",
"00100",
"00100",
"00100",
"00100",
"01110",
"00000",
"10000",
"10000",
"10000",
"10000",
"10000",
"10001",
"01110",
"00000",
"10001",
"01001",
"00101",
"00011",
"00101",
"01001",
"10001",
"00000",
"00001",
"00001",
"00001",
"00001",
"00001",
"00001",
"11111",
"00000",
"10001",
"11011",
"10101",
"10101",
"10001",
"10001",
"10001",
"00000",
"10001",
"10001",
"10011",
"10101",
"11001",
"10001",
"10001",
"00000",
"01110",
"10001",
"10001",
"10001",
"10001",
"10001",
"01110",
"00000",
"01111",
"10001",
"10001",
"01111",
"00001",
"00001",
"00001",
"00000",
"01110",
"10001",
"10001",
"10001",
"10101",
"01001",
"10110",
"00000",
"01111",
"10001",
"10001",
"01111",
"00101",
"01001",
"10001",
"00000",
"01110",
"10001",
"00001",
"01110",
"10000",
"10001",
"01110",
"00000",
"11111",
"00100",
"00100",
"00100",
"00100",
"00100",
"00100",
"00000",
"10001",
"10001",
"10001",
"10001",
"10001",
"10001",
"01110",
"00000",
"10001",
"10001",
"10001",
"10001",
"10001",
"01010",
"00100",
"00000",
"10001",
"10001",
"10001",
"10101",
"10101",
"11011",
"10001",
"00000",
"10001",
"10001",
"01010",
"00100",
"01010",
"10001",
"10001",
"00000",
"10001",
"10001",
"01010",
"00100",
"00100",
"00100",
"00100",
"00000",
"11111",
"10000",
"01000",
"00100",
"00010",
"00001",
"11111",
"00000",
"11111",
"00011",
"00011",
"00011",
"00011",
"00011",
"11111",
"00000",
"00000",
"00001",
"00010",
"00100",
"01000",
"10000",
"00000",
"00000",
"11111",
"11000",
"11000",
"11000",
"11000",
"11000",
"11111",
"00000",
"00000",
"00000",
"00100",
"01010",
"10001",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"11111",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00100",
"00100",
"00100",
"00100",
"00100",
"00000",
"00100",
"00000",
"01010",
"01010",
"01010",
"00000",
"00000",
"00000",
"00000",
"00000",
"01010",
"01010",
"11111",
"01010",
"11111",
"01010",
"01010",
"00000",
"00100",
"11110",
"00101",
"01110",
"10100",
"01111",
"00100",
"00000",
"00011",
"10011",
"01000",
"00100",
"00010",
"11001",
"11000",
"00000",
"00010",
"00101",
"00101",
"00010",
"10101",
"01001",
"10110",
"00000",
"00100",
"00100",
"00100",
"00000",
"00000",
"00000",
"00000",
"00000",
"00100",
"00010",
"00001",
"00001",
"00001",
"00010",
"00100",
"00000",
"00100",
"01000",
"10000",
"10000",
"10000",
"01000",
"00100",
"00000",
"00100",
"10101",
"01110",
"00100",
"01110",
"10101",
"00100",
"00000",
"00000",
"00100",
"00100",
"11111",
"00100",
"00100",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00100",
"00100",
"00010",
"00000",
"00000",
"00000",
"00000",
"11111",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00100",
"00000",
"00000",
"10000",
"01000",
"00100",
"00010",
"00001",
"00000",
"00000",
"01110",
"10001",
"11001",
"10101",
"10011",
"10001",
"01110",
"00000",
"00100",
"00110",
"00100",
"00100",
"00100",
"00100",
"01110",
"00000",
"01110",
"10001",
"10000",
"01100",
"00010",
"00001",
"11111",
"00000",
"11111",
"10000",
"01000",
"01100",
"10000",
"10001",
"01110",
"00000",
"01000",
"01100",
"01010",
"01001",
"11111",
"01000",
"01000",
"00000",
"11111",
"00001",
"01111",
"10000",
"10000",
"10001",
"01110",
"00000",
"11100",
"00010",
"00001",
"01111",
"10001",
"10001",
"01110",
"00000",
"11111",
"10000",
"01000",
"00100",
"00010",
"00010",
"00010",
"00000",
"01110",
"10001",
"10001",
"01110",
"10001",
"10001",
"01110",
"00000",
"01110",
"10001",
"10001",
"11110",
"10000",
"01000",
"00111",
"00000",
"00000",
"00000",
"00100",
"00000",
"00100",
"00000",
"00000",
"00000",
"00000",
"00000",
"00100",
"00000",
"00100",
"00100",
"00010",
"00000",
"01000",
"00100",
"00010",
"00001",
"00010",
"00100",
"01000",
"00000",
"00000",
"00000",
"11111",
"00000",
"11111",
"00000",
"00000",
"00000",
"00010",
"00100",
"01000",
"10000",
"01000",
"00100",
"00010",
"00000",
"01110",
"10001",
"01000",
"00100",
"00100",
"00000",
"00100",
"00000");
begin
process (clk)
begin
if rising_edge(clk) then
dout <= ROM(TO_INTEGER(addr));
end if;
end process;
end rtl;

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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
rmdir /s /q diskemu\.qsys_edit
rmdir /s /q diskemu\diskemu
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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-------------------------------------------------------------------------------
--
-- Disk II emulator
--
-- This is read-only and only feeds "pre-nibblized" data to the processor
-- It has a single-track buffer and only supports one drive (1).
--
-- Stephen A. Edwards, sedwards@cs.columbia.edu
--
-------------------------------------------------------------------------------
--
-- Each track is represented as 0x1A00 bytes
-- Each disk image consists of 35 * 0x1A00 bytes = 0x38A00 (227.5 K)
--
-- X = $60 for slot 6
--
-- Off On
-- C080,X C081,X Phase 0 Head Stepper Motor Control
-- C082,X C083,X Phase 1
-- C084,X C085,X Phase 2
-- C086,X C087,X Phase 3
-- C088,X C089,X Motor On
-- C08A,X C08B,X Select Drive 2 (select drive 1 when off)
-- C08C,X C08D,X Q6 (Shift/load?)
-- C08E,X C08F,X Q7 (Write request to drive)
--
--
-- Q7 Q6
-- 0 0 Read
-- 0 1 Sense write protect
-- 1 0 Write
-- 1 1 Load Write Latch
--
-- Reading a byte:
-- LDA $C08E,X set read mode
-- ...
-- READ LDA $C08C,X
-- BPL READ
--
-- Sense write protect:
-- LDA $C08D,X
-- LDA $C08E,X
-- BMI PROTECTED
--
-- Writing
-- STA $C08F,X set write mode
-- ..
-- LDA DATA
-- STA $C08D,X load byte to write
-- STA $C08C,X write byte to disk
--
-- Data bytes must be written in 32 cycle loops.
--
-- There are 70 phases for the head stepper and and 35 tracks,
-- i.e., two phase changes per track.
--
-- The disk spins at 300 rpm; one new bit arrives every 4 us
-- The processor's clock is 1 MHz = 1 us, so it takes 8 * 4 = 32 cycles
-- for a new byte to arrive
--
-- This corresponds to dividing the 2 MHz signal by 64 to get the byte clock
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disk_ii is
port (
CLK_14M : in std_logic;
CLK_2M : in std_logic;
PRE_PHASE_ZERO : in std_logic;
IO_SELECT : in std_logic; -- e.g., C600 - C6FF ROM
DEVICE_SELECT : in std_logic; -- e.g., C0E0 - C0EF I/O locations
RESET : in std_logic;
A : in unsigned(15 downto 0);
D_IN : in unsigned(7 downto 0); -- From 6502
D_OUT : out unsigned(7 downto 0); -- To 6502
TRACK : out unsigned(5 downto 0); -- Current track (0-34)
track_addr : out unsigned(13 downto 0);
D1_ACTIVE : out std_logic; -- Disk 1 motor on
D2_ACTIVE : out std_logic; -- Disk 2 motor on
ram_write_addr : in unsigned(12 downto 0); -- Address for track RAM
ram_di : in unsigned(7 downto 0); -- Data to track RAM
ram_we : in std_logic -- RAM write enable
);
end disk_ii;
architecture rtl of disk_ii is
signal motor_phase : std_logic_vector(3 downto 0);
signal drive_on : std_logic;
signal drive2_select : std_logic;
signal q6, q7 : std_logic;
signal rom_dout : unsigned(7 downto 0);
-- Current phase of the head. This is in half-steps to assign
-- a unique position to the case, say, when both phase 0 and phase 1 are
-- on simultaneously. phase(7 downto 2) is the track number
signal phase : unsigned(7 downto 0); -- 0 - 139
-- Storage for one track worth of data in "nibblized" form
type track_ram is array(0 to 6655) of unsigned(7 downto 0);
-- Double-ported RAM for holding a track
signal track_memory : track_ram;
signal ram_do : unsigned(7 downto 0);
-- Lower bit indicates whether disk data is "valid" or not
-- RAM address is track_byte_addr(14 downto 1)
-- This makes it look to the software like new data is constantly
-- being read into the shift register, which indicates the data is
-- not yet ready.
signal track_byte_addr : unsigned(14 downto 0);
signal read_disk : std_logic; -- When C08C accessed
begin
interpret_io : process (CLK_2M)
begin
if rising_edge(CLK_2M) then
if reset = '1' then
motor_phase <= (others => '0');
drive_on <= '0';
drive2_select <= '0';
q6 <= '0';
q7 <= '0';
else
if PRE_PHASE_ZERO = '1' and DEVICE_SELECT = '1' then
if A(3) = '0' then -- C080 - C087
motor_phase(TO_INTEGER(A(2 downto 1))) <= A(0);
else
case A(2 downto 1) is
when "00" => drive_on <= A(0); -- C088 - C089
when "01" => drive2_select <= A(0); -- C08A - C08B
when "10" => q6 <= A(0); -- C08C - C08D
when "11" => q7 <= A(0); -- C08E - C08F
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
D1_ACTIVE <= drive_on and not drive2_select;
D2_ACTIVE <= drive_on and drive2_select;
-- There are two cases:
--
-- Current phase is odd (between two poles)
-- |
-- V
-- -3-2-1 0 1 2 3
-- X X X X
-- 0 1 2 3
--
--
-- Current phase is even (under a pole)
-- |
-- V
-- -4-3-2-1 0 1 2 3 4
-- X X X X X
-- 0 1 2 3 0
--
update_phase : process (CLK_14M)
variable phase_change : integer;
variable new_phase : integer;
variable rel_phase : std_logic_vector(3 downto 0);
begin
if rising_edge(CLK_14M) then
if reset = '1' then
phase <= TO_UNSIGNED(70, 8); -- Deliberately odd to test reset
else
phase_change := 0;
new_phase := TO_INTEGER(phase);
rel_phase := motor_phase;
case phase(2 downto 1) is
when "00" =>
rel_phase := rel_phase(1 downto 0) & rel_phase(3 downto 2);
when "01" =>
rel_phase := rel_phase(2 downto 0) & rel_phase(3);
when "10" => null;
when "11" =>
rel_phase := rel_phase(0) & rel_phase(3 downto 1);
when others => null;
end case;
if phase(0) = '1' then -- Phase is odd
case rel_phase is
when "0000" => phase_change := 0;
when "0001" => phase_change := -3;
when "0010" => phase_change := -1;
when "0011" => phase_change := -2;
when "0100" => phase_change := 1;
when "0101" => phase_change := -1;
when "0110" => phase_change := 0;
when "0111" => phase_change := -1;
when "1000" => phase_change := 3;
when "1001" => phase_change := 0;
when "1010" => phase_change := 1;
when "1011" => phase_change := -3;
when "1111" => phase_change := 0;
when others => null;
end case;
else -- Phase is even
case rel_phase is
when "0000" => phase_change := 0;
when "0001" => phase_change := -2;
when "0010" => phase_change := 0;
when "0011" => phase_change := -1;
when "0100" => phase_change := 2;
when "0101" => phase_change := 0;
when "0110" => phase_change := 1;
when "0111" => phase_change := 0;
when "1000" => phase_change := 0;
when "1001" => phase_change := 1;
when "1010" => phase_change := 2;
when "1011" => phase_change := -2;
when "1111" => phase_change := 0;
when others => null;
end case;
end if;
if new_phase + phase_change <= 0 then
new_phase := 0;
elsif new_phase + phase_change > 139 then
new_phase := 139;
else
new_phase := new_phase + phase_change;
end if;
phase <= TO_UNSIGNED(new_phase, 8);
end if;
end if;
end process;
TRACK <= phase(7 downto 2);
-- Dual-ported RAM holding the contents of the track
track_storage : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if ram_we = '1' then
track_memory(to_integer(ram_write_addr)) <= ram_di;
end if;
ram_do <= track_memory(to_integer(track_byte_addr(14 downto 1)));
end if;
end process;
-- Go to the next byte when the disk is accessed or if the counter times out
read_head : process (CLK_2M)
variable byte_delay : unsigned(5 downto 0); -- Accounts for disk spin rate
begin
if rising_edge(CLK_2M) then
if reset = '1' then
track_byte_addr <= (others => '0');
byte_delay := (others => '0');
else
byte_delay := byte_delay - 1;
if (read_disk = '1' and PRE_PHASE_ZERO = '1') or byte_delay = 0 then
byte_delay := (others => '0');
if track_byte_addr = X"33FE" then
track_byte_addr <= (others => '0');
else
track_byte_addr <= track_byte_addr + 1;
end if;
end if;
end if;
end if;
end process;
rom : entity work.disk_ii_rom port map (
addr => A(7 downto 0),
clk => CLK_14M,
dout => rom_dout);
read_disk <= '1' when DEVICE_SELECT = '1' and A(3 downto 0) = x"C" else
'0'; -- C08C
D_OUT <= rom_dout when IO_SELECT = '1' else
ram_do when read_disk = '1' and track_byte_addr(0) = '0' else
(others => '0');
track_addr <= track_byte_addr(14 downto 1);
end rtl;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disk_ii_rom is
port (
addr : in unsigned(7 downto 0);
clk : in std_logic;
dout : out unsigned(7 downto 0));
end disk_ii_rom;
architecture rtl of disk_ii_rom is
type rom_array is array(0 to 255) of unsigned(7 downto 0);
constant ROM : rom_array := (
X"a2", X"20", X"a0", X"00", X"a2", X"03", X"86", X"3c",
X"8a", X"0a", X"24", X"3c", X"f0", X"10", X"05", X"3c",
X"49", X"ff", X"29", X"7e", X"b0", X"08", X"4a", X"d0",
X"fb", X"98", X"9d", X"56", X"03", X"c8", X"e8", X"10",
X"e5", X"20", X"58", X"ff", X"ba", X"bd", X"00", X"01",
X"0a", X"0a", X"0a", X"0a", X"85", X"2b", X"aa", X"bd",
X"8e", X"c0", X"bd", X"8c", X"c0", X"bd", X"8a", X"c0",
X"bd", X"89", X"c0", X"a0", X"50", X"bd", X"80", X"c0",
X"98", X"29", X"03", X"0a", X"05", X"2b", X"aa", X"bd",
X"81", X"c0", X"a9", X"56", X"20", X"a8", X"fc", X"88",
X"10", X"eb", X"85", X"26", X"85", X"3d", X"85", X"41",
X"a9", X"08", X"85", X"27", X"18", X"08", X"bd", X"8c",
X"c0", X"10", X"fb", X"49", X"d5", X"d0", X"f7", X"bd",
X"8c", X"c0", X"10", X"fb", X"c9", X"aa", X"d0", X"f3",
X"ea", X"bd", X"8c", X"c0", X"10", X"fb", X"c9", X"96",
X"f0", X"09", X"28", X"90", X"df", X"49", X"ad", X"f0",
X"25", X"d0", X"d9", X"a0", X"03", X"85", X"40", X"bd",
X"8c", X"c0", X"10", X"fb", X"2a", X"85", X"3c", X"bd",
X"8c", X"c0", X"10", X"fb", X"25", X"3c", X"88", X"d0",
X"ec", X"28", X"c5", X"3d", X"d0", X"be", X"a5", X"40",
X"c5", X"41", X"d0", X"b8", X"b0", X"b7", X"a0", X"56",
X"84", X"3c", X"bc", X"8c", X"c0", X"10", X"fb", X"59",
X"d6", X"02", X"a4", X"3c", X"88", X"99", X"00", X"03",
X"d0", X"ee", X"84", X"3c", X"bc", X"8c", X"c0", X"10",
X"fb", X"59", X"d6", X"02", X"a4", X"3c", X"91", X"26",
X"c8", X"d0", X"ef", X"bc", X"8c", X"c0", X"10", X"fb",
X"59", X"d6", X"02", X"d0", X"87", X"a0", X"00", X"a2",
X"56", X"ca", X"30", X"fb", X"b1", X"26", X"5e", X"00",
X"03", X"2a", X"5e", X"00", X"03", X"2a", X"91", X"26",
X"c8", X"d0", X"ee", X"e6", X"27", X"e6", X"3d", X"a5",
X"3d", X"cd", X"00", X"08", X"a6", X"2b", X"90", X"db",
X"4c", X"01", X"08", X"00", X"00", X"00", X"00", X"00");
begin
process (clk)
begin
if rising_edge(clk) then
dout <= ROM(TO_INTEGER(addr));
end if;
end process;
end rtl;

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/***********************************************************************
*
* Apple ][ .dsk file to .nib file format converter
*
* Stephen A. Edwards, sedwards@cs.columbia.edu
*
* Adapted from the "dsk2pdb" program supplied with the PalmApple/Appalm ][
*
***********************************************************************
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
typedef unsigned char BYTE;
#define VOLUME_NUMBER 254
#define TRACKS 35
#define SECTORS 16
#define SECTOR_SIZE 256
#define DOS_TRACK_BYTES (SECTORS * SECTOR_SIZE)
#define RAW_TRACK_BYTES 0x1A00
FILE *disk_file;
BYTE dos_track[SECTORS * SECTOR_SIZE];
BYTE raw_track[RAW_TRACK_BYTES];
BYTE *target; /* Where to write in the raw_track buffer */
#define write_byte(x) (*target++ = (x))
BYTE GCR_encoding_table[64] = {
0x96, 0x97, 0x9A, 0x9B, 0x9D, 0x9E, 0x9F, 0xA6,
0xA7, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB2, 0xB3,
0xB4, 0xB5, 0xB6, 0xB7, 0xB9, 0xBA, 0xBB, 0xBC,
0xBD, 0xBE, 0xBF, 0xCB, 0xCD, 0xCE, 0xCF, 0xD3,
0xD6, 0xD7, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE,
0xDF, 0xE5, 0xE6, 0xE7, 0xE9, 0xEA, 0xEB, 0xEC,
0xED, 0xEE, 0xEF, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6,
0xF7, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF };
int Swap_Bit[4] = { 0, 2, 1, 3 }; /* swap lower 2 bits */
BYTE GCR_buffer[256];
BYTE GCR_buffer2[86];
/* physical sector no. to DOS 3.3 logical sector no. table */
int Logical_Sector[16] = {
0x0, 0x7, 0xE, 0x6, 0xD, 0x5, 0xC, 0x4,
0xB, 0x3, 0xA, 0x2, 0x9, 0x1, 0x8, 0xF };
/*
* write an FM encoded value, used in writing address fields
*/
void FM_encode( BYTE data )
{
write_byte( (data >> 1) | 0xAA );
write_byte( data | 0xAA );
}
/*
* Write 0xFF sync bytes
*/
void write_sync( int length )
{
while( length-- ) write_byte( 0xFF );
}
void write_address_field( int volume, int track, int sector )
{
/*
* write address mark
*/
write_byte( 0xD5 );
write_byte( 0xAA );
write_byte( 0x96 );
/*
* write Volume, Track, Sector & Check-sum
*/
FM_encode( volume );
FM_encode( track );
FM_encode( sector );
FM_encode( volume ^ track ^ sector );
/*
* write epilogue
*/
write_byte( 0xDE );
write_byte( 0xAA );
write_byte( 0xEB );
}
/*
* 6-and-2 group encoding: the heart of the "nibblization" procedure
*/
void encode62( BYTE *page )
{
int i, j;
/* 86 * 3 = 258, so the first two byte are encoded twice */
GCR_buffer2[0] = Swap_Bit[page[1] & 0x03];
GCR_buffer2[1] = Swap_Bit[page[0] & 0x03];
/* save higher 6 bits in GCR_buffer and lower 2 bits in GCR_buffer2 */
for( i = 255, j = 2; i >= 0; i--, j = j == 85? 0: j + 1 ) {
GCR_buffer2[j] = (GCR_buffer2[j] << 2) | Swap_Bit[page[i] & 0x03];
GCR_buffer[i] = page[i] >> 2;
}
/* clear off higher 2 bits of GCR_buffer2 set in the last call */
for( i = 0; i < 86; i++ )
GCR_buffer2[i] &= 0x3f;
}
void write_data_field(BYTE *page)
{
int i;
BYTE last, checksum;
encode62(page);
/* write prologue */
write_byte( 0xD5 );
write_byte( 0xAA );
write_byte( 0xAD );
/* write GCR encoded data */
for ( i = 0x55, last = 0 ; i >= 0 ; --i ) {
checksum = last ^ GCR_buffer2[i];
write_byte( GCR_encoding_table[checksum] );
last = GCR_buffer2[i];
}
for ( i = 0 ; i < 256 ; ++i ) {
checksum = last ^ GCR_buffer[i];
write_byte( GCR_encoding_table[checksum] );
last = GCR_buffer[i];
}
/* write checksum and epilogue */
write_byte( GCR_encoding_table[last] );
write_byte( 0xDE );
write_byte( 0xAA );
write_byte( 0xEB );
}
int main(int argc, char **argv)
{
char nibname[256], *p;
FILE *nib_file;
int track;
if (argc < 2) {
fprintf(stderr, "Usage: %s <DSK file> [NIB file]\n", argv[0]);
exit(1);
}
if (!(disk_file = fopen(argv[1], "rb"))) {
fprintf(stderr, "Unable to mount disk file \"%s\"\n", argv[1]);
exit(1);
}
if (argc > 2) {
strcpy(nibname, argv[2]);
} else {
/* Strip leading pathname from DSK name */
for (p = argv[1]; *p; p++) {
if (*p == '/' || *p == '\\')
argv[1] = p + 1;
}
strcpy(nibname, argv[1]);
/* Strip trailing .dsk, if any, from DSK name */
p = nibname + strlen(nibname);
if (p[-4] == '.' &&
(p[-3] == 'd' || p[-3] == 'D') &&
(p[-2] == 's' || p[-2] == 'S') &&
(p[-1] == 'k' || p[-1] == 'K')) p[-4] = 0;
strcat(nibname, ".nib");
}
if (!(nib_file = fopen(nibname, "wb"))) {
fprintf(stderr, "Unable to write \"%s\"\n", nibname);
exit(1);
}
/* Read, convert, and write each track */
for (track = 0 ; track < TRACKS ; ++track ) {
int sector;
fseek( disk_file, track * DOS_TRACK_BYTES, 0L );
if ( fread(dos_track, 1, DOS_TRACK_BYTES, disk_file) != DOS_TRACK_BYTES ) {
fprintf(stderr, "Unexpected end of disk data\n");
exit(1);
}
target = raw_track;
for ( sector = 0 ; sector < SECTORS ; sector ++ ) {
write_sync( 38 ); /* Inter-sector gap */
write_address_field( VOLUME_NUMBER, track, sector );
write_sync( 8 );
write_data_field( dos_track + Logical_Sector[sector] * SECTOR_SIZE );
}
/* Pad rest of buffer with sync bytes */
while (target != &raw_track[RAW_TRACK_BYTES])
write_byte( 0xff );
if ( fwrite(raw_track, 1, RAW_TRACK_BYTES, nib_file) != RAW_TRACK_BYTES) {
fprintf(stderr, "Error writing .nib file\n");
exit(1);
}
}
fclose(disk_file);
fclose(nib_file);
return 0;
}
/* Local Variables: */
/* compile-command: "cc -O -Wall -pedantic -ansi -o dsk2nib dsk2nib.c" */
/* End: */

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dsk2nib/dsk2nib.exe Normal file
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jtag.cdf Normal file
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/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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jtag_lite.cdf Normal file
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/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II-lite.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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-------------------------------------------------------------------------------
--
-- PS/2 Keyboard interface for the Apple ][
--
-- Stephen A. Edwards, sedwards@cs.columbia.edu
-- After an original by Alex Freed
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity keyboard is
port (
PS2_Clk : in std_logic; -- From PS/2 port
PS2_Data : in std_logic; -- From PS/2 port
CLK_14M : in std_logic;
reads : in std_logic; -- Read strobe
reset : in std_logic;
K : out unsigned(7 downto 0) -- Latched, decoded keyboard data
);
end keyboard;
architecture rtl of keyboard is
signal code, latched_code : unsigned(7 downto 0);
signal code_available : std_logic;
signal ascii : unsigned(7 downto 0); -- decoded
signal shifted_code : unsigned(11 downto 0);
signal key_pressed : std_logic; -- Key pressed & not read
signal ctrl, shift : std_logic;
-- Special PS/2 keyboard codes
constant KEY_UP_CODE : unsigned(7 downto 0) := X"F0";
constant EXTENDED_CODE : unsigned(7 downto 0) := X"E0";
constant LEFT_SHIFT : unsigned(7 downto 0) := X"12";
constant RIGHT_SHIFT : unsigned(7 downto 0) := X"59";
constant LEFT_CTRL : unsigned(7 downto 0) := X"14";
type states is (IDLE,
HAVE_CODE,
DECODE,
GOT_KEY_UP_CODE,
GOT_KEY_UP2,
GOT_KEY_UP3,
KEY_UP,
NORMAL_KEY
);
signal state, next_state : states;
begin
ps2_controller : entity work.PS2_Ctrl port map (
Clk => CLK_14M,
Reset => reset,
PS2_Clk => PS2_Clk,
PS2_Data => PS2_Data,
DoRead => code_available,
Scan_DAV => code_available,
Scan_Code => code);
K <= key_pressed & "00" & ascii(4 downto 0) when ctrl = '1' else
key_pressed & ascii(6 downto 0);
shift_ctrl : process (CLK_14M, reset)
begin
if reset = '1' then
shift <= '0';
ctrl <= '0';
elsif rising_edge(CLK_14M) then
if state = HAVE_CODE then
if code = LEFT_SHIFT or code = RIGHT_SHIFT then
shift <= '1';
elsif code = LEFT_CTRL then
ctrl <= '1';
end if;
elsif state = KEY_UP then
if code = LEFT_SHIFT or code = RIGHT_SHIFT then
shift <= '0';
elsif code = LEFT_CTRL then
ctrl <= '0';
end if;
end if;
end if;
end process shift_ctrl;
fsm : process (CLK_14M, reset)
begin
if reset = '1' then
state <= IDLE;
latched_code <= (others => '0');
key_pressed <= '0';
elsif rising_edge(CLK_14M) then
state <= next_state;
if reads = '1' then key_pressed <= '0'; end if;
if state = NORMAL_KEY then
latched_code <= code ;
key_pressed <= '1';
end if;
end if;
end process fsm;
fsm_next_state : process (code, code_available, state)
begin
next_state <= state;
case state is
when IDLE =>
if code_available = '1' then next_state <= HAVE_CODE; end if;
when HAVE_CODE =>
next_state <= DECODE;
when DECODE =>
if code = KEY_UP_CODE then
next_state <= GOT_KEY_UP_CODE;
elsif code = EXTENDED_CODE then -- Treat extended codes as normal
next_state <= IDLE;
elsif code = LEFT_SHIFT or code = RIGHT_SHIFT or code = LEFT_CTRL then
next_state <= IDLE;
else
next_state <= NORMAL_KEY;
end if;
when GOT_KEY_UP_CODE =>
next_state <= GOT_KEY_UP2;
when GOT_KEY_UP2 =>
next_state <= GOT_KEY_UP3;
when GOT_KEY_UP3 =>
if code_available = '1' then
next_state <= KEY_UP;
end if;
when KEY_UP | NORMAL_KEY =>
next_state <= IDLE;
end case;
end process fsm_next_state;
-- PS/2 scancode to ASCII translation
shifted_code <= "000" & shift & latched_code;
with shifted_code select
ascii <=
X"08" when X"066", -- Backspace ("backspace" key)
X"08" when X"166", -- Backspace ("backspace" key)
X"09" when X"00d", -- Horizontal Tab
X"09" when X"10d", -- Horizontal Tab
X"0d" when X"05a", -- Carriage return ("enter" key)
X"0d" when X"15a", -- Carriage return ("enter" key)
X"1b" when X"076", -- Escape ("esc" key)
X"1b" when X"176", -- Escape ("esc" key)
X"20" when X"029", -- Space
X"20" when X"129", -- Space
X"21" when X"116", -- !
X"22" when X"152", -- "
X"23" when X"126", -- #
X"24" when X"125", -- $
X"25" when X"12e", --
X"26" when X"13d", --
X"27" when X"052", --
X"28" when X"146", --
X"29" when X"145", --
X"2a" when X"13e", -- *
X"2b" when X"155", -- +
X"2c" when X"041", -- ,
X"2d" when X"04e", -- -
X"2e" when X"049", -- .
X"2f" when X"04a", -- /
X"30" when X"045", -- 0
X"31" when X"016", -- 1
X"32" when X"01e", -- 2
X"33" when X"026", -- 3
X"34" when X"025", -- 4
X"35" when X"02e", -- 5
X"36" when X"036", -- 6
X"37" when X"03d", -- 7
X"38" when X"03e", -- 8
X"39" when X"046", -- 9
X"3a" when X"14c", -- :
X"3b" when X"04c", -- ;
X"3c" when X"141", -- <
X"3d" when X"055", -- =
X"3e" when X"149", -- >
X"3f" when X"14a", -- ?
X"40" when X"11e", -- @
X"41" when X"11c", -- A
X"42" when X"132", -- B
X"43" when X"121", -- C
X"44" when X"123", -- D
X"45" when X"124", -- E
X"46" when X"12b", -- F
X"47" when X"134", -- G
X"48" when X"133", -- H
X"49" when X"143", -- I
X"4a" when X"13b", -- J
X"4b" when X"142", -- K
X"4c" when X"14b", -- L
X"4d" when X"13a", -- M
X"4e" when X"131", -- N
X"4f" when X"144", -- O
X"50" when X"14d", -- P
X"51" when X"115", -- Q
X"52" when X"12d", -- R
X"53" when X"11b", -- S
X"54" when X"12c", -- T
X"55" when X"13c", -- U
X"56" when X"12a", -- V
X"57" when X"11d", -- W
X"58" when X"122", -- X
X"59" when X"135", -- Y
X"5a" when X"11a", -- Z
X"5b" when X"054", -- [
X"5c" when X"05d", -- \
X"5d" when X"05b", -- ]
X"5e" when X"136", -- ^
X"5f" when X"14e", -- _
X"60" when X"00e", -- `
X"41" when X"01c", -- A
X"42" when X"032", -- B
X"43" when X"021", -- C
X"44" when X"023", -- D
X"45" when X"024", -- E
X"46" when X"02b", -- F
X"47" when X"034", -- G
X"48" when X"033", -- H
X"49" when X"043", -- I
X"4a" when X"03b", -- J
X"4b" when X"042", -- K
X"4c" when X"04b", -- L
X"4d" when X"03a", -- M
X"4e" when X"031", -- N
X"4f" when X"044", -- O
X"50" when X"04d", -- P
X"51" when X"015", -- Q
X"52" when X"02d", -- R
X"53" when X"01b", -- S
X"54" when X"02c", -- T
X"55" when X"03c", -- U
X"56" when X"02a", -- V
X"57" when X"01d", -- W
X"58" when X"022", -- X
X"59" when X"035", -- Y
X"5a" when X"01a", -- Z
X"7b" when X"154", -- {
X"7c" when X"15d", -- |
X"7d" when X"15b", -- }
X"7e" when X"10e", -- ~
X"7f" when X"071", -- (Delete OR DEL on numeric keypad)
X"15" when X"074", -- right arrow (cntrl U)
X"08" when X"06b", -- left arrow (BS)
X"0B" when X"075", -- (up arrow)
X"0A" when X"072", -- (down arrow, ^J, LF)
X"7f" when X"171", -- (Delete OR DEL on numeric keypad)
X"00" when others;
end rtl;

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mockingboard/YM2149_volmix.vhd Normal file
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--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses a volume table for accurate mixing of the three analogue channels,
-- where the outputs are wired together - like in the Atari ST
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149 is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
--
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of YM2149 is
component vol_table
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(9 downto 0)
);
end component;
-- signals
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal vol_table_in : std_logic_vector(11 downto 0);
signal vol_table_out : std_logic_vector(9 downto 0);
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
-- CLOCKED
--p_waddr : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--if (RESET_L = '0') then
--addr <= (others => '0');
--else
--if (busctrl_addr = '1') then
--addr <= I_DA;
--end if;
--end if;
--end process;
--p_wdata : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--env_reset <= '0';
--if (RESET_L = '0') then
--reg <= (others => (others => '0'));
--env_reset <= '1';
--else
--env_reset <= '0';
--if (busctrl_we = '1') then
--case addr(3 downto 0) is
--when x"0" => reg(0) <= I_DA;
--when x"1" => reg(1) <= I_DA;
--when x"2" => reg(2) <= I_DA;
--when x"3" => reg(3) <= I_DA;
--when x"4" => reg(4) <= I_DA;
--when x"5" => reg(5) <= I_DA;
--when x"6" => reg(6) <= I_DA;
--when x"7" => reg(7) <= I_DA;
--when x"8" => reg(8) <= I_DA;
--when x"9" => reg(9) <= I_DA;
--when x"A" => reg(10) <= I_DA;
--when x"B" => reg(11) <= I_DA;
--when x"C" => reg(12) <= I_DA;
--when x"D" => reg(13) <= I_DA; env_reset <= '1';
--when x"E" => reg(14) <= I_DA;
--when x"F" => reg(15) <= I_DA;
--when others => null;
--end case;
--end if;
--end if;
--end process;
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
p_waddr : process(reset_l, busctrl_addr)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif falling_edge(busctrl_addr) then -- yuk
addr <= I_DA;
end if;
end process;
p_wdata : process(reset_l, busctrl_we, addr)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
elsif falling_edge(busctrl_we) then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
when x"2" => reg(2) <= I_DA;
when x"3" => reg(3) <= I_DA;
when x"4" => reg(4) <= I_DA;
when x"5" => reg(5) <= I_DA;
when x"6" => reg(6) <= I_DA;
when x"7" => reg(7) <= I_DA;
when x"8" => reg(8) <= I_DA;
when x"9" => reg(9) <= I_DA;
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
when x"D" => reg(13) <= I_DA;
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
end if;
env_reset <= '0';
if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
env_reset <= '1';
end if;
end process;
p_rdata : process(busctrl_re, addr, reg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
elsif rising_edge(CLK) then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer_table : process
variable chan_mixed : std_logic_vector(2 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op);
chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op);
chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op);
vol_table_in <= x"000";
if (chan_mixed(0) = '1') then
if (reg(8)(4) = '0') then
vol_table_in(3 downto 0) <= reg(8)(3 downto 0);
else
vol_table_in(3 downto 0) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(1) = '1') then
if (reg(9)(4) = '0') then
vol_table_in(7 downto 4) <= reg(9)(3 downto 0);
else
vol_table_in(7 downto 4) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(2) = '1') then
if (reg(10)(4) = '0') then
vol_table_in(11 downto 8) <= reg(10)(3 downto 0);
else
vol_table_in(11 downto 8) <= env_vol(4 downto 1);
end if;
end if;
end if;
end process;
u_vol_table : vol_table
port map (
CLK => clk,
ADDR => vol_table_in,
DATA => vol_table_out
);
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (RESET_L = '0') then
O_AUDIO(7 downto 0) <= "00000000";
else
O_AUDIO(7 downto 0) <= vol_table_out(9 downto 2);
end if;
end process;
p_io_ports : process(reg)
begin
-- input low
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process
begin
wait until rising_edge(CLK);
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end process;
end architecture RTL;

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@ -0,0 +1,893 @@
--
-- A simulation model of VIC20 hardware
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email vic20@fpgaarcade.com
--
--
-- Revision list
--
-- version 003 Clearing PB7 when T1C-H is written by hoglet
-- version 002 fix from Mark McDougall, untested
-- version 001 initial release
-- not very sure about the shift register, documentation is a bit light.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library UNISIM;
-- use UNISIM.Vcomponents.all;
entity M6522 is
port (
I_RS : in std_logic_vector(3 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
I_RW_L : in std_logic;
I_CS1 : in std_logic;
I_CS2_L : in std_logic;
O_IRQ_L : out std_logic; -- note, not open drain
-- port a
I_CA1 : in std_logic;
I_CA2 : in std_logic;
O_CA2 : out std_logic;
O_CA2_OE_L : out std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
O_PA_OE_L : out std_logic_vector(7 downto 0);
-- port b
I_CB1 : in std_logic;
O_CB1 : out std_logic;
O_CB1_OE_L : out std_logic;
I_CB2 : in std_logic;
O_CB2 : out std_logic;
O_CB2_OE_L : out std_logic;
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
O_PB_OE_L : out std_logic_vector(7 downto 0);
I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
CLK : in std_logic
);
end;
architecture RTL of M6522 is
signal phase : std_logic_vector(1 downto 0);
signal p2_h_t1 : std_logic;
signal cs : std_logic;
-- registers
signal r_ddra : std_logic_vector(7 downto 0);
signal r_ora : std_logic_vector(7 downto 0);
signal r_ira : std_logic_vector(7 downto 0);
signal r_ddrb : std_logic_vector(7 downto 0);
signal r_orb : std_logic_vector(7 downto 0);
signal r_irb : std_logic_vector(7 downto 0);
signal r_t1l_l : std_logic_vector(7 downto 0);
signal r_t1l_h : std_logic_vector(7 downto 0);
signal r_t2l_l : std_logic_vector(7 downto 0);
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
signal r_sr : std_logic_vector(7 downto 0);
signal r_acr : std_logic_vector(7 downto 0);
signal r_pcr : std_logic_vector(7 downto 0);
signal r_ifr : std_logic_vector(7 downto 0);
signal r_ier : std_logic_vector(6 downto 0);
signal sr_write_ena : boolean;
signal sr_read_ena : boolean;
signal ifr_write_ena : boolean;
signal ier_write_ena : boolean;
signal clear_irq : std_logic_vector(7 downto 0);
signal load_data : std_logic_vector(7 downto 0);
-- timer 1
signal t1c : std_logic_vector(15 downto 0);
signal t1c_active : boolean;
signal t1c_done : boolean;
signal t1_w_reset_int : boolean;
signal t1_r_reset_int : boolean;
signal t1_load_counter : boolean;
signal t1_reload_counter : boolean;
signal t1_toggle : std_logic;
signal t1_irq : std_logic := '0';
-- timer 2
signal t2c : std_logic_vector(15 downto 0);
signal t2c_active : boolean;
signal t2c_done : boolean;
signal t2_pb6 : std_logic;
signal t2_pb6_t1 : std_logic;
signal t2_w_reset_int : boolean;
signal t2_r_reset_int : boolean;
signal t2_load_counter : boolean;
signal t2_reload_counter : boolean;
signal t2_irq : std_logic := '0';
signal t2_sr_ena : boolean;
-- shift reg
signal sr_cnt : std_logic_vector(3 downto 0);
signal sr_cb1_oe_l : std_logic;
signal sr_cb1_out : std_logic;
signal sr_drive_cb2 : std_logic;
signal sr_strobe : std_logic;
signal sr_strobe_t1 : std_logic;
signal sr_strobe_falling : boolean;
signal sr_strobe_rising : boolean;
signal sr_irq : std_logic;
signal sr_out : std_logic;
signal sr_off_delay : std_logic;
-- io
signal w_orb_hs : std_logic;
signal w_ora_hs : std_logic;
signal r_irb_hs : std_logic;
signal r_ira_hs : std_logic;
signal ca_hs_sr : std_logic;
signal ca_hs_pulse : std_logic;
signal cb_hs_sr : std_logic;
signal cb_hs_pulse : std_logic;
signal cb1_in_mux : std_logic;
signal ca1_ip_reg : std_logic;
signal cb1_ip_reg : std_logic;
signal ca1_int : boolean;
signal cb1_int : boolean;
signal ca1_irq : std_logic;
signal cb1_irq : std_logic;
signal ca2_ip_reg : std_logic;
signal cb2_ip_reg : std_logic;
signal ca2_int : boolean;
signal cb2_int : boolean;
signal ca2_irq : std_logic;
signal cb2_irq : std_logic;
signal final_irq : std_logic;
begin
p_phase : process
begin
-- internal clock phase
wait until rising_edge(CLK);
if (ENA_4 = '1') then
p2_h_t1 <= I_P2_H;
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
else
phase <= phase + "1";
end if;
end if;
end process;
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
begin
cs <= '0';
if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then
cs <= '1';
end if;
end process;
-- peripheral control reg (pcr)
-- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge)
-- 3..1 ca2 operation
-- 000 input -ve edge
-- 001 independend interrupt input -ve edge
-- 010 input +ve edge
-- 011 independend interrupt input +ve edge
-- 100 handshake output
-- 101 pulse output
-- 110 low output
-- 111 high output
-- 7..4 as 3..0 for cb1,cb2
-- auxiliary control reg (acr)
-- 0 input latch PA (0 disable, 1 enable)
-- 1 input latch PB (0 disable, 1 enable)
-- 4..2 shift reg control
-- 000 disable
-- 001 shift in using t2
-- 010 shift in using o2
-- 011 shift in using ext clk
-- 100 shift out free running t2 rate
-- 101 shift out using t2
-- 101 shift out using o2
-- 101 shift out using ext clk
-- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6)
-- 7..6 t1 timer control
-- 00 timed interrupt each time t1 is loaded pb7 disable
-- 01 continuous interrupts pb7 disable
-- 00 timed interrupt each time t1 is loaded pb7 one shot output
-- 01 continuous interrupts pb7 square wave output
--
p_write_reg_reset : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ora <= x"00"; r_orb <= x"00";
r_ddra <= x"00"; r_ddrb <= x"00";
r_acr <= x"00"; r_pcr <= x"00";
w_orb_hs <= '0';
w_ora_hs <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
w_orb_hs <= '0';
w_ora_hs <= '0';
if (cs = '1') and (I_RW_L = '0') then
case I_RS is
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
when x"2" => r_ddrb <= I_DATA;
when x"3" => r_ddra <= I_DATA;
when x"B" => r_acr <= I_DATA;
when x"C" => r_pcr <= I_DATA;
when x"F" => r_ora <= I_DATA;
when others => null;
end case;
end if;
if (r_acr(7) = '1') then
if t1_load_counter then
r_orb(7) <= '0'; -- writing T1C-H resets bit 7
elsif (t1_toggle = '1') then
r_orb(7) <= not r_orb(7); -- toggle
end if;
end if;
end if;
end if;
end process;
p_write_reg : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
t1_w_reset_int <= false;
t1_load_counter <= false;
t2_w_reset_int <= false;
t2_load_counter <= false;
load_data <= x"00";
sr_write_ena <= false;
ifr_write_ena <= false;
ier_write_ena <= false;
if (cs = '1') and (I_RW_L = '0') then
load_data <= I_DATA;
case I_RS is
when x"4" => r_t1l_l <= I_DATA;
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
t1_load_counter <= true;
when x"6" => r_t1l_l <= I_DATA;
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
when x"8" => r_t2l_l <= I_DATA;
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
t2_load_counter <= true;
when x"A" => sr_write_ena <= true;
when x"D" => ifr_write_ena <= true;
when x"E" => ier_write_ena <= true;
when others => null;
end case;
end if;
end if;
end process;
p_oe : process(cs, I_RW_L)
begin
O_DATA_OE_L <= '1';
if (cs = '1') and (I_RW_L = '1') then
O_DATA_OE_L <= '0';
end if;
end process;
p_read : process
begin
wait until rising_edge(CLK);
if ENA_4 = '1' then
t1_r_reset_int <= false;
t2_r_reset_int <= false;
sr_read_ena <= false;
r_irb_hs <= '0';
r_ira_hs <= '0';
if (cs = '1') and (I_RW_L = '1') then
case I_RS is
--when x"0" => O_DATA <= r_irb; r_irb_hs <= '1';
-- fix from Mark McDougall, untested
when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1';
when x"1" => O_DATA <= r_ira; r_ira_hs <= '1';
when x"2" => O_DATA <= r_ddrb;
when x"3" => O_DATA <= r_ddra;
when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true;
when x"5" => O_DATA <= t1c(15 downto 8);
when x"6" => O_DATA <= r_t1l_l;
when x"7" => O_DATA <= r_t1l_h;
when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true;
when x"9" => O_DATA <= t2c(15 downto 8);
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
when x"B" => O_DATA <= r_acr;
when x"C" => O_DATA <= r_pcr;
when x"D" => O_DATA <= r_ifr;
when x"E" => O_DATA <= ('0' & r_ier);
when x"F" => O_DATA <= r_ira;
when others => null;
end case;
end if;
end if;
end process;
--
-- IO
--
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
begin
-- if the shift register is enabled, cb1 may be an output
-- in this case, we should listen to the CB1_OUT for the interrupt
if (sr_cb1_oe_l = '1') then
cb1_in_mux <= I_CB1;
else
cb1_in_mux <= sr_cb1_out;
end if;
end process;
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux)
begin
if (r_pcr(0) = '0') then -- ca1 control
-- negative edge
ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0');
else
-- positive edge
ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1');
end if;
if (r_pcr(4) = '0') then -- cb1 control
-- negative edge
cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0');
else
-- positive edge
cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1');
end if;
end process;
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2)
begin
ca2_int <= false;
if (r_pcr(3) = '0') then -- ca2 input
if (r_pcr(2) = '0') then -- ca2 edge
-- negative edge
ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0');
else
-- positive edge
ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1');
end if;
end if;
cb2_int <= false;
if (r_pcr(7) = '0') then -- cb2 input
if (r_pcr(6) = '0') then -- cb2 edge
-- negative edge
cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0');
else
-- positive edge
cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1');
end if;
end if;
end process;
p_ca2_cb2 : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_CA2 <= '0';
O_CA2_OE_L <= '1';
O_CB2 <= '0';
O_CB2_OE_L <= '1';
ca_hs_sr <= '0';
ca_hs_pulse <= '0';
cb_hs_sr <= '0';
cb_hs_pulse <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- ca
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
ca_hs_sr <= '1';
elsif ca1_int then
ca_hs_sr <= '0';
end if;
if (phase = "00") then
ca_hs_pulse <= w_ora_hs or r_ira_hs;
end if;
O_CA2_OE_L <= not r_pcr(3); -- ca2 output
case r_pcr(3 downto 1) is
when "000" => O_CA2 <= '0'; -- input
when "001" => O_CA2 <= '0'; -- input
when "010" => O_CA2 <= '0'; -- input
when "011" => O_CA2 <= '0'; -- input
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
when "110" => O_CA2 <= '0'; -- low
when "111" => O_CA2 <= '1'; -- high
when others => null;
end case;
-- cb
if (phase = "00") and (w_orb_hs = '1') then
cb_hs_sr <= '1';
elsif cb1_int then
cb_hs_sr <= '0';
end if;
if (phase = "00") then
cb_hs_pulse <= w_orb_hs;
end if;
O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial
if (sr_drive_cb2 = '1') then -- serial output
O_CB2 <= sr_out;
else
case r_pcr(7 downto 5) is
when "000" => O_CB2 <= '0'; -- input
when "001" => O_CB2 <= '0'; -- input
when "010" => O_CB2 <= '0'; -- input
when "011" => O_CB2 <= '0'; -- input
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
when "110" => O_CB2 <= '0'; -- low
when "111" => O_CB2 <= '1'; -- high
when others => null;
end case;
end if;
end if;
end if;
end process;
O_CB1 <= sr_cb1_out;
O_CB1_OE_L <= sr_cb1_oe_l;
p_ca_cb_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_irq <= '0';
ca2_irq <= '0';
cb1_irq <= '0';
cb2_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- not pretty
if ca1_int then
ca1_irq <= '1';
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
ca1_irq <= '0';
end if;
if ca2_int then
ca2_irq <= '1';
else
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
(clear_irq(0) = '1') then
ca2_irq <= '0';
end if;
end if;
if cb1_int then
cb1_irq <= '1';
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
cb1_irq <= '0';
end if;
if cb2_int then
cb2_irq <= '1';
else
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
(clear_irq(3) = '1') then
cb2_irq <= '0';
end if;
end if;
end if;
end if;
end process;
p_input_reg : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_ip_reg <= '0';
cb1_ip_reg <= '0';
ca2_ip_reg <= '0';
cb2_ip_reg <= '0';
r_ira <= x"00";
r_irb <= x"00";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- we have a fast clock, so we can have input registers
ca1_ip_reg <= I_CA1;
cb1_ip_reg <= cb1_in_mux;
ca2_ip_reg <= I_CA2;
cb2_ip_reg <= I_CB2;
if (r_acr(0) = '0') then
r_ira <= I_PA;
else -- enable latching
if ca1_int then
r_ira <= I_PA;
end if;
end if;
if (r_acr(1) = '0') then
r_irb <= I_PB;
else -- enable latching
if cb1_int then
r_irb <= I_PB;
end if;
end if;
end if;
end if;
end process;
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb)
begin
-- data direction reg (ddr) 0 = input, 1 = output
O_PA <= r_ora;
O_PA_OE_L <= not r_ddra;
if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well
O_PB_OE_L(7) <= '0'; -- an output if under t1 control
else
O_PB_OE_L(7) <= not (r_ddrb(7));
end if;
O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0);
O_PB(7 downto 0) <= r_orb(7 downto 0);
end process;
--
-- Timer 1
--
p_timer1_done : process(t1c,phase,r_acr)
variable done : boolean;
begin
done := (t1c = x"0000");
t1c_done <= done and (phase = "11");
--if (phase = "11") then
t1_reload_counter <= done and (r_acr(6) = '1');
--end if;
end process;
p_timer1 : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if t1_load_counter or (t1_reload_counter and phase = "11") then
t1c( 7 downto 0) <= r_t1l_l;
t1c(15 downto 8) <= r_t1l_h;
elsif (phase="11") then
t1c <= t1c - "1";
end if;
if t1_load_counter or t1_reload_counter then
t1c_active <= true;
elsif t1c_done then
t1c_active <= false;
end if;
if RESET_L = '0' then
t1c_active <= false;
end if;
t1_toggle <= '0';
if t1c_active and t1c_done then
t1_toggle <= '1';
t1_irq <= '1';
elsif RESET_L = '0' or t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
t1_irq <= '0';
end if;
end if;
end process;
--
-- Timer2
--
p_timer2_pb6_input : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then -- leading edge p2_h
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;
end if;
end process;
p_timer2_done : process(t2c,phase)
variable done : boolean;
begin
done := (t2c = x"0000");
t2c_done <= done and (phase = "11");
--if (phase = "11") then
t2_reload_counter <= done;
--end if;
end process;
p_timer2 : process
variable ena : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (r_acr(5) = '0') then
ena := true;
else
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge
end if;
if t2_load_counter or (t2_reload_counter and phase = "11") then
-- not sure if t2c_reload should be here. Does timer2 just continue to
-- count down, or is it reloaded ? Reloaded makes more sense if using
-- it to generate a clock for the shift register.
t2c( 7 downto 0) <= r_t2l_l;
t2c(15 downto 8) <= r_t2l_h;
else
if (phase="11") and ena then -- or count mode
t2c <= t2c - "1";
end if;
end if;
t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11");
if t2_load_counter then
t2c_active <= true;
elsif t2c_done then
t2c_active <= false;
end if;
if RESET_L = '0' then
t2c_active <= false;
end if;
if t2c_active and t2c_done then
t2_irq <= '1';
elsif RESET_L = '0' or t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
t2_irq <= '0';
end if;
end if;
end process;
--
-- Shift Register
--
p_sr : process(RESET_L, CLK)
variable dir_out : std_logic;
variable ena : std_logic;
variable cb1_op : std_logic;
variable cb1_ip : std_logic;
variable use_t2 : std_logic;
variable free_run : std_logic;
variable sr_count_ena : boolean;
begin
if (RESET_L = '0') then
r_sr <= x"00";
sr_drive_cb2 <= '0';
sr_cb1_oe_l <= '1';
sr_cb1_out <= '0';
sr_strobe <= '1';
sr_cnt <= "0000";
sr_irq <= '0';
sr_out <= '1';
sr_off_delay <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- decode mode
dir_out := r_acr(4); -- output on cb2
cb1_op := '0';
cb1_ip := '0';
use_t2 := '0';
free_run := '0';
case r_acr(4 downto 2) is
when "000" => ena := '0'; cb1_ip := '1';
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "010" => ena := '1'; cb1_op := '1';
when "011" => ena := '1'; cb1_ip := '1';
when "100" => ena := '1'; use_t2 := '1'; free_run := '1';
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "110" => ena := '1';
when "111" => ena := '1'; cb1_ip := '1';
when others => null;
end case;
-- clock select
-- SR still runs even in disabled mode (on rising edge of CB1). It
-- just doesn't generate any interrupts.
-- Ref BBC micro advanced user guide p409
if (cb1_ip = '1') then
sr_strobe <= I_CB1;
else
if (sr_cnt(3) = '0') and (free_run = '0') then
sr_strobe <= '1';
else
if ((use_t2 = '1') and t2_sr_ena) or
((use_t2 = '0') and (phase = "00")) then
sr_strobe <= not sr_strobe;
end if;
end if;
end if;
-- latch on rising edge, shift on falling edge
if sr_write_ena then
r_sr <= load_data;
else
if (dir_out = '0') then
-- input
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
if sr_strobe_rising then
r_sr(0) <= I_CB2;
elsif sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
end if;
end if;
sr_out <= '1';
else
-- output
if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then
if sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
r_sr(0) <= r_sr(7);
sr_out <= r_sr(7);
end if;
else
sr_out <= '1';
end if;
end if;
end if;
sr_count_ena := sr_strobe_rising;
if ena = '1' and (sr_write_ena or sr_read_ena) then
-- some documentation says sr bit in IFR must be set as well ?
sr_cnt <= "1000";
elsif sr_count_ena and (sr_cnt(3) = '1') then
sr_cnt <= sr_cnt + "1";
end if;
if (phase = "00") then
sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out
end if;
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
sr_irq <= '1';
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
sr_irq <= '0';
end if;
-- assign ops
sr_drive_cb2 <= dir_out;
sr_cb1_oe_l <= not cb1_op;
sr_cb1_out <= sr_strobe;
end if;
end if;
end process;
p_sr_strobe_rise_fall : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
sr_strobe_t1 <= sr_strobe;
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
end if;
end process;
--
-- Interrupts
--
p_ier : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ier <= "0000000";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ier_write_ena then
if (load_data(7) = '1') then
-- set
r_ier <= r_ier or load_data(6 downto 0);
else
-- clear
r_ier <= r_ier and not load_data(6 downto 0);
end if;
end if;
end if;
end if;
end process;
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
cb1_irq, cb2_irq)
begin
r_ifr(7) <= final_irq;
r_ifr(6) <= t1_irq;
r_ifr(5) <= t2_irq;
r_ifr(4) <= cb1_irq;
r_ifr(3) <= cb2_irq;
r_ifr(2) <= sr_irq;
r_ifr(1) <= ca1_irq;
r_ifr(0) <= ca2_irq;
O_IRQ_L <= not final_irq;
end process;
p_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
final_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
final_irq <= '0'; -- no interrupts
else
final_irq <= '1';
end if;
end if;
end if;
end process;
p_clear_irq : process(ifr_write_ena, load_data)
begin
clear_irq <= x"00";
if ifr_write_ena then
clear_irq <= load_data;
end if;
end process;
end architecture RTL;

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--
-- Mockingboard clone for the Apple II
-- Model A: two AY-3-8913 chips for six audio channels
--
-- Top file by W. Soltys <wsoltys@gmail.com>
--
-- loosely based on:
-- http://www.downloads.reactivemicro.com/Public/Apple%20II%20Items/Hardware/Mockingboard_v1/Mockingboard-v1a-Docs.pdf
-- http://www.applelogic.org/CarteBlancheIIProj6.html
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOCKINGBOARD is
port (
I_ADDR : in std_logic_vector(7 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
I_RW_L : in std_logic;
O_IRQ_L : out std_logic;
I_IOSEL_L : in std_logic;
I_RESET_L : in std_logic;
I_ENA_H : in std_logic;
O_AUDIO_L : out std_logic_vector(7 downto 0);
O_AUDIO_R : out std_logic_vector(7 downto 0);
CLK_VIA : in std_logic;
CLK_PSG : in std_logic;
I_P2_H : in std_logic
);
end;
architecture RTL of MOCKINGBOARD is
signal o_pb_l : std_logic_vector(7 downto 0);
signal o_pb_r : std_logic_vector(7 downto 0);
signal i_psg_r : std_logic_vector(7 downto 0);
signal i_psg_l : std_logic_vector(7 downto 0);
signal o_data_l : std_logic_vector(7 downto 0);
signal o_data_r : std_logic_vector(7 downto 0);
signal lvia_read : std_logic;
signal rvia_read : std_logic;
signal lirq_l : std_logic;
signal rirq_l : std_logic;
begin
O_DATA <= o_data_l when lvia_read = '1' else o_data_r when rvia_read = '1' else (others=>'Z');
lvia_read <= I_RW_L and not I_ADDR(7);
rvia_read <= I_RW_L and I_ADDR(7);
O_IRQ_L <= lirq_l and rirq_l;
-- Left Channel Combo
m6522_left : work.M6522
port map (
I_RS => I_ADDR(3 downto 0),
I_DATA => I_DATA,
O_DATA => o_data_l,
O_DATA_OE_L => open,
I_RW_L => I_RW_L,
I_CS1 => not I_ADDR(7),
I_CS2_L => I_IOSEL_L,
O_IRQ_L => lirq_l,
-- port a
I_CA1 => '0',
I_CA2 => '0',
O_CA2 => open,
O_CA2_OE_L => open,
I_PA => (others => '0'),
O_PA => i_psg_l,
O_PA_OE_L => open,
-- port b
I_CB1 => '0',
O_CB1 => open,
O_CB1_OE_L => open,
I_CB2 => '0',
O_CB2 => open,
O_CB2_OE_L => open,
I_PB => (others => '0'),
O_PB => o_pb_l,
O_PB_OE_L => open,
I_P2_H => I_P2_H,
RESET_L => I_RESET_L,
ENA_4 => '1',
CLK => CLK_VIA and I_ENA_H
);
psg_left : work.YM2149
port map (
-- data bus
I_DA => i_psg_l,
O_DA => open,
O_DA_OE_L => open,
-- control
I_A9_L => '0', -- /A9 pulled down internally
I_A8 => '1',
I_BDIR => o_pb_l(1),
I_BC2 => '1',
I_BC1 => o_pb_l(0),
I_SEL_L => '1', -- /SEL is high for AY-3-8912 compatibility
O_AUDIO => O_AUDIO_L,
-- port a
I_IOA => (others => '0'), -- port A unused
O_IOA => open,
O_IOA_OE_L => open,
-- port b
I_IOB => (others => '0'), -- port B unused
O_IOB => open,
O_IOB_OE_L => open,
--
ENA => '1',
RESET_L => o_pb_l(2),
CLK => CLK_PSG and I_ENA_H
);
-- Right Channel Combo
m6522_right : work.M6522
port map (
I_RS => I_ADDR(3 downto 0),
I_DATA => I_DATA,
O_DATA => o_data_r,
O_DATA_OE_L => open,
I_RW_L => I_RW_L,
I_CS1 => I_ADDR(7),
I_CS2_L => I_IOSEL_L,
O_IRQ_L => rirq_l,
-- port a
I_CA1 => '0',
I_CA2 => '0',
O_CA2 => open,
O_CA2_OE_L => open,
I_PA => (others => '0'),
O_PA => i_psg_r,
O_PA_OE_L => open,
-- port b
I_CB1 => '0',
O_CB1 => open,
O_CB1_OE_L => open,
I_CB2 => '0',
O_CB2 => open,
O_CB2_OE_L => open,
I_PB => (others => '0'),
O_PB => o_pb_r,
O_PB_OE_L => open,
I_P2_H => I_P2_H,
RESET_L => I_RESET_L,
ENA_4 => '1',
CLK => CLK_VIA and I_ENA_H
);
psg_right : work.YM2149
port map (
-- data bus
I_DA => i_psg_r,
O_DA => open,
O_DA_OE_L => open,
-- control
I_A9_L => '0', -- /A9 pulled down internally
I_A8 => '1',
I_BDIR => o_pb_r(1),
I_BC2 => '1',
I_BC1 => o_pb_r(0),
I_SEL_L => '1', -- /SEL is high for AY-3-8912 compatibility
O_AUDIO => O_AUDIO_R,
-- port a
I_IOA => (others => '0'), -- port A unused
O_IOA => open,
O_IOA_OE_L => open,
-- port b
I_IOB => (others => '0'), -- port B unused
O_IOB => open,
O_IOB_OE_L => open,
--
ENA => '1',
RESET_L => o_pb_r(2),
CLK => CLK_PSG and I_ENA_H
);
end architecture RTL;

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-- generated with tablegen by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vol_table is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(9 downto 0)
);
end;
architecture RTL of vol_table is
type ROM_ARRAY is array(0 to 4095) of std_logic_vector(11 downto 0);
constant ROM : ROM_ARRAY := (
x"000",x"002",x"004",x"006",x"009",x"00D",x"014",x"01B", -- 0x0000
x"027",x"036",x"050",x"06D",x"0A5",x"0EB",x"17D",x"24D", -- 0x0008
x"002",x"005",x"007",x"009",x"00D",x"010",x"016",x"01D", -- 0x0010
x"02A",x"038",x"051",x"06F",x"0A7",x"0ED",x"17E",x"24D", -- 0x0018
x"004",x"007",x"009",x"00B",x"00E",x"012",x"018",x"020", -- 0x0020
x"02B",x"03A",x"054",x"071",x"0A9",x"0EF",x"17E",x"24D", -- 0x0028
x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0030
x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"17F",x"24D", -- 0x0038
x"009",x"00D",x"00E",x"011",x"014",x"018",x"01D",x"024", -- 0x0040
x"031",x"03F",x"058",x"076",x"0AD",x"0F3",x"180",x"24D", -- 0x0048
x"00D",x"010",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0050
x"035",x"042",x"05C",x"079",x"0B0",x"0F5",x"182",x"24D", -- 0x0058
x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02F", -- 0x0060
x"03A",x"049",x"062",x"07E",x"0B5",x"0FA",x"184",x"24D", -- 0x0068
x"01B",x"01D",x"020",x"021",x"024",x"028",x"02F",x"035", -- 0x0070
x"042",x"050",x"068",x"085",x"0BB",x"0FE",x"188",x"24D", -- 0x0078
x"027",x"02A",x"02B",x"02E",x"031",x"035",x"03A",x"042", -- 0x0080
x"04D",x"05C",x"073",x"091",x"0C5",x"108",x"18E",x"24D", -- 0x0088
x"036",x"038",x"03A",x"03C",x"03F",x"042",x"049",x"050", -- 0x0090
x"05C",x"06A",x"082",x"09D",x"0D2",x"114",x"19A",x"24D", -- 0x0098
x"050",x"051",x"054",x"055",x"058",x"05C",x"062",x"068", -- 0x00A0
x"073",x"082",x"098",x"0B4",x"0E7",x"128",x"1AB",x"254", -- 0x00A8
x"06D",x"06F",x"071",x"073",x"076",x"079",x"07E",x"085", -- 0x00B0
x"091",x"09D",x"0B4",x"0D0",x"102",x"142",x"1C1",x"264", -- 0x00B8
x"0A5",x"0A7",x"0A9",x"0AB",x"0AD",x"0B0",x"0B5",x"0BB", -- 0x00C0
x"0C5",x"0D2",x"0E7",x"102",x"133",x"172",x"1ED",x"27C", -- 0x00C8
x"0EB",x"0ED",x"0EF",x"0F0",x"0F3",x"0F5",x"0FA",x"0FE", -- 0x00D0
x"108",x"114",x"128",x"142",x"172",x"1AF",x"21D",x"2AB", -- 0x00D8
x"17D",x"17E",x"17E",x"17F",x"180",x"182",x"184",x"188", -- 0x00E0
x"18E",x"19A",x"1AB",x"1C1",x"1ED",x"21D",x"284",x"30A", -- 0x00E8
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x00F0
x"24D",x"24D",x"254",x"264",x"27C",x"2AB",x"30A",x"379", -- 0x00F8
x"002",x"005",x"006",x"009",x"00C",x"010",x"016",x"01D", -- 0x0100
x"02A",x"038",x"052",x"06F",x"0A7",x"0ED",x"17E",x"24E", -- 0x0108
x"005",x"007",x"009",x"00B",x"00F",x"012",x"018",x"01F", -- 0x0110
x"02C",x"03A",x"053",x"071",x"0A9",x"0EF",x"17F",x"24E", -- 0x0118
x"006",x"009",x"00B",x"00D",x"011",x"014",x"01B",x"022", -- 0x0120
x"02E",x"03D",x"056",x"073",x"0AB",x"0F0",x"180",x"24E", -- 0x0128
x"009",x"00B",x"00D",x"010",x"013",x"016",x"01C",x"023", -- 0x0130
x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"181",x"24E", -- 0x0138
x"00C",x"00F",x"011",x"013",x"016",x"01A",x"01F",x"027", -- 0x0140
x"033",x"041",x"05B",x"078",x"0AF",x"0F4",x"181",x"24E", -- 0x0148
x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0150
x"037",x"044",x"05E",x"07B",x"0B2",x"0F7",x"183",x"24E", -- 0x0158
x"016",x"018",x"01B",x"01C",x"01F",x"023",x"02A",x"031", -- 0x0160
x"03D",x"04B",x"064",x"080",x"0B7",x"0FB",x"185",x"24E", -- 0x0168
x"01D",x"01F",x"022",x"023",x"027",x"02A",x"031",x"037", -- 0x0170
x"044",x"052",x"06A",x"087",x"0BD",x"100",x"189",x"24E", -- 0x0178
x"02A",x"02C",x"02E",x"030",x"033",x"037",x"03D",x"044", -- 0x0180
x"04F",x"05E",x"075",x"092",x"0C7",x"10A",x"190",x"24E", -- 0x0188
x"038",x"03A",x"03D",x"03E",x"041",x"044",x"04B",x"052", -- 0x0190
x"05E",x"06C",x"083",x"09F",x"0D4",x"115",x"19B",x"24E", -- 0x0198
x"052",x"053",x"056",x"057",x"05B",x"05E",x"064",x"06A", -- 0x01A0
x"075",x"083",x"09A",x"0B6",x"0E9",x"12A",x"1AD",x"256", -- 0x01A8
x"06F",x"071",x"073",x"075",x"078",x"07B",x"080",x"087", -- 0x01B0
x"092",x"09F",x"0B6",x"0D1",x"104",x"143",x"1C2",x"265", -- 0x01B8
x"0A7",x"0A9",x"0AB",x"0AD",x"0AF",x"0B2",x"0B7",x"0BD", -- 0x01C0
x"0C7",x"0D4",x"0E9",x"104",x"135",x"174",x"1EE",x"27D", -- 0x01C8
x"0ED",x"0EF",x"0F0",x"0F2",x"0F4",x"0F7",x"0FB",x"100", -- 0x01D0
x"10A",x"115",x"12A",x"143",x"174",x"1B0",x"21E",x"2AC", -- 0x01D8
x"17E",x"17F",x"180",x"181",x"181",x"183",x"185",x"189", -- 0x01E0
x"190",x"19B",x"1AD",x"1C2",x"1EE",x"21E",x"285",x"30B", -- 0x01E8
x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x01F0
x"24E",x"24E",x"256",x"265",x"27D",x"2AC",x"30B",x"379", -- 0x01F8
x"004",x"006",x"008",x"00A",x"00D",x"011",x"018",x"01F", -- 0x0200
x"02B",x"039",x"053",x"070",x"0A8",x"0EE",x"17F",x"24F", -- 0x0208
x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0210
x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"180",x"24F", -- 0x0218
x"008",x"00B",x"00D",x"00F",x"012",x"016",x"01C",x"023", -- 0x0220
x"02F",x"03E",x"057",x"074",x"0AC",x"0F2",x"181",x"24F", -- 0x0228
x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01E",x"025", -- 0x0230
x"031",x"040",x"059",x"077",x"0AE",x"0F3",x"182",x"24F", -- 0x0238
x"00D",x"011",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0240
x"035",x"043",x"05C",x"079",x"0B0",x"0F5",x"183",x"24F", -- 0x0248
x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0250
x"039",x"046",x"05F",x"07C",x"0B3",x"0F8",x"184",x"24F", -- 0x0258
x"018",x"01A",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0260
x"03E",x"04C",x"065",x"082",x"0B8",x"0FD",x"186",x"24F", -- 0x0268
x"01F",x"021",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0270
x"045",x"053",x"06C",x"088",x"0BE",x"101",x"18A",x"24F", -- 0x0278
x"02B",x"02E",x"02F",x"031",x"035",x"039",x"03E",x"045", -- 0x0280
x"051",x"05F",x"077",x"094",x"0C8",x"10B",x"191",x"24F", -- 0x0288
x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0290
x"05F",x"06D",x"085",x"0A0",x"0D5",x"116",x"19C",x"24F", -- 0x0298
x"053",x"055",x"057",x"059",x"05C",x"05F",x"065",x"06C", -- 0x02A0
x"077",x"085",x"09B",x"0B7",x"0EA",x"12B",x"1AE",x"256", -- 0x02A8
x"070",x"073",x"074",x"077",x"079",x"07C",x"082",x"088", -- 0x02B0
x"094",x"0A0",x"0B7",x"0D3",x"105",x"144",x"1C3",x"266", -- 0x02B8
x"0A8",x"0AB",x"0AC",x"0AE",x"0B0",x"0B3",x"0B8",x"0BE", -- 0x02C0
x"0C8",x"0D5",x"0EA",x"105",x"136",x"175",x"1EF",x"27E", -- 0x02C8
x"0EE",x"0F0",x"0F2",x"0F3",x"0F5",x"0F8",x"0FC",x"101", -- 0x02D0
x"10B",x"116",x"12B",x"144",x"175",x"1B1",x"21F",x"2AD", -- 0x02D8
x"17F",x"180",x"181",x"182",x"183",x"184",x"186",x"18A", -- 0x02E0
x"191",x"19C",x"1AE",x"1C3",x"1EF",x"21F",x"285",x"30B", -- 0x02E8
x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x02F0
x"24E",x"24E",x"256",x"266",x"27E",x"2AD",x"30B",x"37A", -- 0x02F8
x"006",x"009",x"00A",x"00D",x"010",x"014",x"01A",x"021", -- 0x0300
x"02D",x"03B",x"055",x"072",x"0AA",x"0F0",x"181",x"250", -- 0x0308
x"009",x"00B",x"00D",x"00F",x"013",x"016",x"01C",x"023", -- 0x0310
x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"182",x"250", -- 0x0318
x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01F",x"026", -- 0x0320
x"031",x"040",x"059",x"076",x"0AE",x"0F3",x"183",x"250", -- 0x0328
x"00D",x"00F",x"011",x"014",x"017",x"01A",x"020",x"027", -- 0x0330
x"034",x"042",x"05B",x"079",x"0B0",x"0F5",x"183",x"250", -- 0x0338
x"010",x"013",x"014",x"017",x"01A",x"01E",x"023",x"02A", -- 0x0340
x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"184",x"250", -- 0x0348
x"014",x"016",x"018",x"01A",x"01E",x"021",x"027",x"02E", -- 0x0350
x"03B",x"048",x"061",x"07E",x"0B5",x"0FA",x"186",x"250", -- 0x0358
x"01A",x"01C",x"01F",x"020",x"023",x"027",x"02D",x"034", -- 0x0360
x"040",x"04E",x"067",x"084",x"0BA",x"0FE",x"188",x"250", -- 0x0368
x"021",x"023",x"026",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0370
x"047",x"055",x"06E",x"08A",x"0C0",x"103",x"18C",x"250", -- 0x0378
x"02D",x"030",x"031",x"034",x"037",x"03B",x"040",x"047", -- 0x0380
x"053",x"061",x"079",x"096",x"0CA",x"10C",x"192",x"250", -- 0x0388
x"03B",x"03E",x"040",x"042",x"045",x"048",x"04E",x"055", -- 0x0390
x"061",x"06F",x"087",x"0A2",x"0D7",x"118",x"19E",x"250", -- 0x0398
x"055",x"057",x"059",x"05B",x"05E",x"061",x"067",x"06E", -- 0x03A0
x"079",x"087",x"09D",x"0B9",x"0EC",x"12C",x"1AF",x"258", -- 0x03A8
x"072",x"075",x"076",x"079",x"07B",x"07E",x"084",x"08A", -- 0x03B0
x"096",x"0A2",x"0B9",x"0D4",x"106",x"145",x"1C4",x"267", -- 0x03B8
x"0AA",x"0AD",x"0AE",x"0B0",x"0B2",x"0B5",x"0BA",x"0C0", -- 0x03C0
x"0CA",x"0D7",x"0EC",x"106",x"137",x"176",x"1F0",x"27F", -- 0x03C8
x"0F0",x"0F2",x"0F3",x"0F5",x"0F7",x"0FA",x"0FE",x"103", -- 0x03D0
x"10C",x"118",x"12C",x"145",x"176",x"1B2",x"220",x"2AE", -- 0x03D8
x"181",x"182",x"183",x"183",x"184",x"186",x"188",x"18C", -- 0x03E0
x"192",x"19E",x"1AF",x"1C4",x"1F0",x"220",x"286",x"30C", -- 0x03E8
x"250",x"250",x"250",x"250",x"250",x"250",x"250",x"250", -- 0x03F0
x"250",x"250",x"257",x"267",x"27F",x"2AE",x"30C",x"37A", -- 0x03F8
x"009",x"00C",x"00D",x"010",x"013",x"017",x"01D",x"024", -- 0x0400
x"030",x"03E",x"058",x"075",x"0AD",x"0F3",x"183",x"251", -- 0x0408
x"00C",x"00E",x"010",x"012",x"016",x"019",x"01F",x"026", -- 0x0410
x"033",x"041",x"05A",x"077",x"0AF",x"0F4",x"184",x"251", -- 0x0418
x"00D",x"010",x"012",x"014",x"017",x"01B",x"022",x"029", -- 0x0420
x"034",x"043",x"05C",x"079",x"0B1",x"0F6",x"185",x"251", -- 0x0428
x"010",x"012",x"014",x"017",x"01A",x"01D",x"023",x"02A", -- 0x0430
x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"185",x"251", -- 0x0438
x"013",x"016",x"017",x"01A",x"01D",x"021",x"026",x"02D", -- 0x0440
x"03A",x"048",x"061",x"07E",x"0B4",x"0FA",x"186",x"251", -- 0x0448
x"017",x"019",x"01B",x"01D",x"021",x"024",x"02A",x"031", -- 0x0450
x"03E",x"04B",x"064",x"081",x"0B8",x"0FC",x"188",x"251", -- 0x0458
x"01D",x"01F",x"022",x"023",x"026",x"02A",x"030",x"037", -- 0x0460
x"043",x"051",x"06A",x"086",x"0BC",x"101",x"18A",x"251", -- 0x0468
x"024",x"026",x"029",x"02A",x"02D",x"031",x"037",x"03E", -- 0x0470
x"04A",x"058",x"070",x"08C",x"0C2",x"105",x"18E",x"251", -- 0x0478
x"030",x"033",x"034",x"037",x"03A",x"03E",x"043",x"04A", -- 0x0480
x"056",x"064",x"07B",x"098",x"0CD",x"10F",x"194",x"251", -- 0x0488
x"03E",x"041",x"043",x"045",x"048",x"04B",x"051",x"058", -- 0x0490
x"064",x"072",x"089",x"0A4",x"0D9",x"11A",x"1A0",x"251", -- 0x0498
x"058",x"05A",x"05C",x"05E",x"061",x"064",x"06A",x"070", -- 0x04A0
x"07B",x"089",x"0A0",x"0BB",x"0EE",x"12E",x"1B1",x"259", -- 0x04A8
x"075",x"077",x"079",x"07B",x"07E",x"081",x"086",x"08C", -- 0x04B0
x"098",x"0A4",x"0BB",x"0D6",x"109",x"147",x"1C6",x"269", -- 0x04B8
x"0AD",x"0AF",x"0B1",x"0B2",x"0B4",x"0B8",x"0BC",x"0C2", -- 0x04C0
x"0CD",x"0D9",x"0EE",x"109",x"139",x"178",x"1F2",x"280", -- 0x04C8
x"0F3",x"0F4",x"0F6",x"0F7",x"0FA",x"0FC",x"101",x"105", -- 0x04D0
x"10E",x"11A",x"12E",x"147",x"178",x"1B3",x"221",x"2AF", -- 0x04D8
x"183",x"184",x"185",x"185",x"186",x"188",x"18A",x"18E", -- 0x04E0
x"194",x"1A0",x"1B1",x"1C6",x"1F1",x"221",x"287",x"30D", -- 0x04E8
x"251",x"251",x"251",x"251",x"251",x"251",x"251",x"251", -- 0x04F0
x"251",x"251",x"259",x"269",x"280",x"2AF",x"30D",x"37B", -- 0x04F8
x"00D",x"010",x"011",x"014",x"017",x"01B",x"021",x"028", -- 0x0500
x"034",x"042",x"05C",x"078",x"0B0",x"0F6",x"186",x"254", -- 0x0508
x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0510
x"036",x"044",x"05D",x"07B",x"0B2",x"0F7",x"187",x"254", -- 0x0518
x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0520
x"038",x"047",x"05F",x"07C",x"0B4",x"0F9",x"187",x"254", -- 0x0528
x"014",x"016",x"018",x"01B",x"01E",x"021",x"027",x"02E", -- 0x0530
x"03A",x"048",x"061",x"07F",x"0B5",x"0FA",x"188",x"254", -- 0x0538
x"017",x"01A",x"01B",x"01E",x"021",x"025",x"02A",x"031", -- 0x0540
x"03D",x"04B",x"064",x"081",x"0B8",x"0FD",x"189",x"254", -- 0x0548
x"01B",x"01D",x"01F",x"021",x"025",x"028",x"02E",x"035", -- 0x0550
x"041",x"04E",x"067",x"084",x"0BB",x"0FF",x"18A",x"254", -- 0x0558
x"021",x"023",x"025",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0560
x"047",x"055",x"06D",x"089",x"0BF",x"104",x"18D",x"254", -- 0x0568
x"028",x"02A",x"02C",x"02E",x"031",x"035",x"03B",x"041", -- 0x0570
x"04E",x"05B",x"074",x"090",x"0C6",x"108",x"191",x"254", -- 0x0578
x"034",x"036",x"038",x"03A",x"03D",x"041",x"047",x"04E", -- 0x0580
x"059",x"067",x"07E",x"09B",x"0D0",x"112",x"197",x"254", -- 0x0588
x"042",x"044",x"047",x"048",x"04B",x"04E",x"055",x"05B", -- 0x0590
x"067",x"075",x"08C",x"0A8",x"0DC",x"11D",x"1A2",x"254", -- 0x0598
x"05C",x"05D",x"05F",x"061",x"064",x"067",x"06D",x"074", -- 0x05A0
x"07E",x"08C",x"0A3",x"0BE",x"0F1",x"131",x"1B3",x"25B", -- 0x05A8
x"078",x"07B",x"07C",x"07F",x"081",x"084",x"089",x"090", -- 0x05B0
x"09B",x"0A8",x"0BE",x"0D9",x"10B",x"14A",x"1C8",x"26B", -- 0x05B8
x"0B0",x"0B2",x"0B4",x"0B5",x"0B8",x"0BB",x"0BF",x"0C6", -- 0x05C0
x"0D0",x"0DC",x"0F1",x"10B",x"13C",x"17A",x"1F4",x"282", -- 0x05C8
x"0F6",x"0F7",x"0F9",x"0FA",x"0FD",x"0FF",x"103",x"108", -- 0x05D0
x"111",x"11D",x"131",x"14A",x"17A",x"1B6",x"223",x"2B0", -- 0x05D8
x"186",x"187",x"187",x"188",x"189",x"18A",x"18D",x"191", -- 0x05E0
x"197",x"1A2",x"1B3",x"1C8",x"1F4",x"223",x"289",x"30E", -- 0x05E8
x"253",x"253",x"253",x"253",x"253",x"253",x"253",x"253", -- 0x05F0
x"253",x"253",x"25B",x"26B",x"282",x"2B0",x"30E",x"37C", -- 0x05F8
x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02E", -- 0x0600
x"03A",x"048",x"061",x"07E",x"0B5",x"0FA",x"18A",x"256", -- 0x0608
x"016",x"018",x"01B",x"01C",x"020",x"023",x"029",x"030", -- 0x0610
x"03C",x"04A",x"063",x"080",x"0B7",x"0FC",x"18B",x"256", -- 0x0618
x"018",x"01B",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0620
x"03E",x"04C",x"065",x"081",x"0B9",x"0FD",x"18B",x"256", -- 0x0628
x"01A",x"01C",x"01E",x"021",x"024",x"027",x"02D",x"034", -- 0x0630
x"040",x"04E",x"066",x"084",x"0BA",x"0FF",x"18C",x"256", -- 0x0638
x"01D",x"020",x"021",x"024",x"027",x"02B",x"030",x"037", -- 0x0640
x"043",x"051",x"069",x"086",x"0BC",x"101",x"18D",x"256", -- 0x0648
x"021",x"023",x"025",x"027",x"02B",x"02E",x"034",x"03B", -- 0x0650
x"047",x"054",x"06D",x"089",x"0C0",x"104",x"18E",x"256", -- 0x0658
x"027",x"029",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0660
x"04C",x"05A",x"073",x"08E",x"0C4",x"108",x"191",x"256", -- 0x0668
x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0670
x"053",x"061",x"079",x"094",x"0CA",x"10D",x"194",x"256", -- 0x0678
x"03A",x"03C",x"03E",x"040",x"043",x"047",x"04C",x"053", -- 0x0680
x"05F",x"06C",x"083",x"0A0",x"0D4",x"116",x"19B",x"256", -- 0x0688
x"048",x"04A",x"04C",x"04E",x"051",x"054",x"05A",x"061", -- 0x0690
x"06C",x"07A",x"091",x"0AC",x"0E0",x"121",x"1A6",x"256", -- 0x0698
x"061",x"063",x"065",x"066",x"069",x"06D",x"073",x"079", -- 0x06A0
x"083",x"091",x"0A7",x"0C3",x"0F5",x"135",x"1B7",x"25E", -- 0x06A8
x"07E",x"080",x"081",x"084",x"086",x"089",x"08E",x"094", -- 0x06B0
x"0A0",x"0AC",x"0C3",x"0DE",x"10F",x"14E",x"1CB",x"26D", -- 0x06B8
x"0B5",x"0B7",x"0B9",x"0BA",x"0BC",x"0C0",x"0C4",x"0CA", -- 0x06C0
x"0D4",x"0E0",x"0F5",x"10F",x"13F",x"17E",x"1F6",x"284", -- 0x06C8
x"0FA",x"0FC",x"0FD",x"0FF",x"101",x"103",x"108",x"10C", -- 0x06D0
x"116",x"121",x"135",x"14E",x"17D",x"1B8",x"226",x"2B2", -- 0x06D8
x"18A",x"18B",x"18B",x"18C",x"18D",x"18E",x"191",x"194", -- 0x06E0
x"19B",x"1A6",x"1B7",x"1CB",x"1F6",x"226",x"28B",x"30F", -- 0x06E8
x"256",x"256",x"256",x"256",x"256",x"256",x"256",x"256", -- 0x06F0
x"256",x"256",x"25E",x"26D",x"284",x"2B2",x"30F",x"37D", -- 0x06F8
x"01B",x"01D",x"01F",x"021",x"024",x"028",x"02E",x"034", -- 0x0700
x"041",x"04E",x"067",x"084",x"0BB",x"100",x"18E",x"25A", -- 0x0708
x"01D",x"01F",x"022",x"023",x"027",x"02A",x"030",x"037", -- 0x0710
x"043",x"050",x"069",x"086",x"0BD",x"101",x"18F",x"25A", -- 0x0718
x"01F",x"022",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0720
x"044",x"053",x"06B",x"087",x"0BE",x"103",x"190",x"25A", -- 0x0728
x"021",x"023",x"025",x"028",x"02B",x"02E",x"034",x"03B", -- 0x0730
x"047",x"054",x"06D",x"08A",x"0C0",x"104",x"191",x"25A", -- 0x0738
x"024",x"027",x"028",x"02B",x"02E",x"031",x"037",x"03E", -- 0x0740
x"04A",x"057",x"070",x"08C",x"0C2",x"107",x"191",x"25A", -- 0x0748
x"028",x"02A",x"02C",x"02E",x"031",x"034",x"03B",x"041", -- 0x0750
x"04D",x"05A",x"073",x"08F",x"0C5",x"109",x"193",x"25A", -- 0x0758
x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0760
x"053",x"060",x"079",x"094",x"0CA",x"10D",x"195",x"25A", -- 0x0768
x"034",x"037",x"039",x"03B",x"03E",x"041",x"047",x"04D", -- 0x0770
x"059",x"067",x"07F",x"09A",x"0D0",x"112",x"199",x"25A", -- 0x0778
x"041",x"043",x"044",x"047",x"04A",x"04D",x"053",x"059", -- 0x0780
x"065",x"072",x"089",x"0A5",x"0D9",x"11B",x"19F",x"25A", -- 0x0788
x"04E",x"050",x"053",x"054",x"057",x"05A",x"060",x"067", -- 0x0790
x"072",x"080",x"097",x"0B2",x"0E6",x"126",x"1AA",x"25A", -- 0x0798
x"067",x"069",x"06B",x"06D",x"070",x"073",x"079",x"07F", -- 0x07A0
x"089",x"097",x"0AD",x"0C8",x"0FA",x"13A",x"1BB",x"262", -- 0x07A8
x"084",x"086",x"087",x"08A",x"08C",x"08F",x"094",x"09A", -- 0x07B0
x"0A5",x"0B2",x"0C8",x"0E3",x"114",x"152",x"1CF",x"271", -- 0x07B8
x"0BB",x"0BD",x"0BE",x"0C0",x"0C2",x"0C5",x"0CA",x"0D0", -- 0x07C0
x"0D9",x"0E6",x"0FA",x"114",x"144",x"182",x"1FA",x"287", -- 0x07C8
x"0FF",x"101",x"102",x"104",x"106",x"108",x"10D",x"112", -- 0x07D0
x"11B",x"126",x"13A",x"152",x"181",x"1BC",x"229",x"2B5", -- 0x07D8
x"18E",x"18F",x"190",x"191",x"191",x"193",x"195",x"199", -- 0x07E0
x"19F",x"1AA",x"1BB",x"1CF",x"1F9",x"229",x"28D",x"312", -- 0x07E8
x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A", -- 0x07F0
x"25A",x"25A",x"261",x"270",x"287",x"2B5",x"312",x"37F", -- 0x07F8
x"027",x"02A",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0800
x"04C",x"05A",x"072",x"08E",x"0C5",x"109",x"197",x"261", -- 0x0808
x"02A",x"02C",x"02E",x"030",x"033",x"036",x"03C",x"043", -- 0x0810
x"04F",x"05C",x"074",x"090",x"0C7",x"10B",x"198",x"261", -- 0x0818
x"02B",x"02E",x"030",x"032",x"035",x"038",x"03E",x"045", -- 0x0820
x"050",x"05E",x"076",x"092",x"0C8",x"10C",x"198",x"261", -- 0x0828
x"02D",x"030",x"032",x"034",x"037",x"03A",x"040",x"046", -- 0x0830
x"052",x"060",x"078",x"094",x"0CA",x"10E",x"199",x"261", -- 0x0838
x"030",x"033",x"035",x"037",x"03A",x"03E",x"043",x"049", -- 0x0840
x"055",x"062",x"07B",x"096",x"0CC",x"110",x"19A",x"261", -- 0x0848
x"034",x"036",x"038",x"03A",x"03E",x"041",x"046",x"04D", -- 0x0850
x"059",x"065",x"07E",x"099",x"0CF",x"112",x"19B",x"261", -- 0x0858
x"03A",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0860
x"05E",x"06B",x"083",x"09E",x"0D3",x"117",x"19E",x"261", -- 0x0868
x"041",x"043",x"045",x"046",x"049",x"04D",x"053",x"059", -- 0x0870
x"065",x"072",x"089",x"0A4",x"0D9",x"11B",x"1A1",x"261", -- 0x0878
x"04C",x"04F",x"050",x"052",x"055",x"059",x"05E",x"065", -- 0x0880
x"070",x"07D",x"094",x"0AF",x"0E3",x"124",x"1A7",x"261", -- 0x0888
x"05A",x"05C",x"05E",x"060",x"062",x"065",x"06B",x"072", -- 0x0890
x"07D",x"08A",x"0A1",x"0BB",x"0EF",x"12F",x"1B2",x"261", -- 0x0898
x"072",x"074",x"076",x"078",x"07B",x"07E",x"083",x"089", -- 0x08A0
x"094",x"0A1",x"0B6",x"0D1",x"103",x"142",x"1C2",x"268", -- 0x08A8
x"08E",x"090",x"092",x"094",x"096",x"099",x"09E",x"0A4", -- 0x08B0
x"0AF",x"0BB",x"0D1",x"0EB",x"11C",x"15A",x"1D6",x"277", -- 0x08B8
x"0C5",x"0C7",x"0C8",x"0CA",x"0CC",x"0CF",x"0D3",x"0D9", -- 0x08C0
x"0E3",x"0EF",x"103",x"11C",x"14B",x"189",x"200",x"28D", -- 0x08C8
x"109",x"10A",x"10C",x"10D",x"110",x"112",x"116",x"11B", -- 0x08D0
x"123",x"12F",x"142",x"15A",x"189",x"1C3",x"22F",x"2BA", -- 0x08D8
x"197",x"198",x"198",x"199",x"19A",x"19B",x"19E",x"1A1", -- 0x08E0
x"1A7",x"1B2",x"1C2",x"1D6",x"200",x"22F",x"292",x"315", -- 0x08E8
x"260",x"260",x"260",x"260",x"260",x"260",x"260",x"260", -- 0x08F0
x"260",x"260",x"268",x"276",x"28C",x"2BA",x"315",x"382", -- 0x08F8
x"036",x"038",x"039",x"03B",x"03E",x"042",x"048",x"04E", -- 0x0900
x"05A",x"067",x"07F",x"09A",x"0D0",x"114",x"1A1",x"268", -- 0x0908
x"038",x"03A",x"03C",x"03E",x"041",x"044",x"04A",x"050", -- 0x0910
x"05C",x"069",x"080",x"09C",x"0D2",x"116",x"1A1",x"268", -- 0x0918
x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"052", -- 0x0920
x"05D",x"06B",x"083",x"09E",x"0D4",x"117",x"1A2",x"268", -- 0x0928
x"03B",x"03E",x"040",x"042",x"045",x"048",x"04D",x"054", -- 0x0930
x"05F",x"06C",x"084",x"0A0",x"0D5",x"119",x"1A3",x"268", -- 0x0938
x"03E",x"041",x"043",x"045",x"048",x"04B",x"050",x"057", -- 0x0940
x"062",x"06F",x"087",x"0A2",x"0D7",x"11B",x"1A3",x"268", -- 0x0948
x"042",x"044",x"046",x"048",x"04B",x"04E",x"054",x"05A", -- 0x0950
x"066",x"072",x"08A",x"0A5",x"0DA",x"11D",x"1A5",x"268", -- 0x0958
x"048",x"04A",x"04C",x"04D",x"050",x"054",x"05A",x"060", -- 0x0960
x"06B",x"078",x"090",x"0AA",x"0DF",x"121",x"1A7",x"268", -- 0x0968
x"04E",x"050",x"052",x"054",x"057",x"05A",x"060",x"066", -- 0x0970
x"071",x"07E",x"095",x"0B0",x"0E4",x"126",x"1AB",x"268", -- 0x0978
x"05A",x"05C",x"05D",x"05F",x"062",x"066",x"06B",x"071", -- 0x0980
x"07C",x"089",x"09F",x"0BB",x"0EE",x"12E",x"1B0",x"268", -- 0x0988
x"067",x"069",x"06B",x"06C",x"06F",x"072",x"078",x"07E", -- 0x0990
x"089",x"096",x"0AC",x"0C6",x"0F9",x"139",x"1BB",x"268", -- 0x0998
x"07F",x"080",x"083",x"084",x"087",x"08A",x"090",x"095", -- 0x09A0
x"09F",x"0AC",x"0C1",x"0DC",x"10D",x"14C",x"1CB",x"26F", -- 0x09A8
x"09A",x"09C",x"09E",x"0A0",x"0A2",x"0A5",x"0AA",x"0B0", -- 0x09B0
x"0BB",x"0C6",x"0DC",x"0F6",x"126",x"163",x"1DE",x"27E", -- 0x09B8
x"0D0",x"0D2",x"0D4",x"0D5",x"0D7",x"0DA",x"0DF",x"0E4", -- 0x09C0
x"0EE",x"0F9",x"10D",x"126",x"154",x"192",x"207",x"293", -- 0x09C8
x"114",x"115",x"117",x"118",x"11A",x"11C",x"121",x"125", -- 0x09D0
x"12E",x"138",x"14C",x"163",x"191",x"1CA",x"235",x"2BF", -- 0x09D8
x"1A1",x"1A1",x"1A2",x"1A3",x"1A3",x"1A5",x"1A7",x"1AB", -- 0x09E0
x"1B0",x"1BB",x"1CB",x"1DE",x"207",x"235",x"298",x"31A", -- 0x09E8
x"268",x"268",x"268",x"268",x"268",x"268",x"268",x"268", -- 0x09F0
x"268",x"268",x"26F",x"27D",x"293",x"2BF",x"31A",x"386", -- 0x09F8
x"050",x"052",x"053",x"055",x"058",x"05B",x"061",x"067", -- 0x0A00
x"072",x"07E",x"096",x"0B0",x"0E5",x"128",x"1B1",x"275", -- 0x0A08
x"052",x"054",x"056",x"057",x"05B",x"05D",x"063",x"069", -- 0x0A10
x"074",x"080",x"097",x"0B2",x"0E7",x"129",x"1B2",x"275", -- 0x0A18
x"053",x"056",x"057",x"059",x"05C",x"05F",x"065",x"06B", -- 0x0A20
x"075",x"082",x"099",x"0B4",x"0E8",x"12B",x"1B3",x"275", -- 0x0A28
x"055",x"057",x"059",x"05B",x"05E",x"061",x"066",x"06C", -- 0x0A30
x"077",x"084",x"09B",x"0B6",x"0EA",x"12C",x"1B4",x"275", -- 0x0A38
x"058",x"05B",x"05C",x"05E",x"061",x"064",x"069",x"06F", -- 0x0A40
x"07A",x"086",x"09D",x"0B8",x"0EC",x"12E",x"1B4",x"275", -- 0x0A48
x"05B",x"05D",x"05F",x"061",x"064",x"067",x"06C",x"073", -- 0x0A50
x"07E",x"089",x"0A0",x"0BA",x"0EE",x"130",x"1B6",x"275", -- 0x0A58
x"061",x"063",x"065",x"066",x"069",x"06C",x"072",x"078", -- 0x0A60
x"082",x"08F",x"0A5",x"0BF",x"0F3",x"134",x"1B8",x"275", -- 0x0A68
x"067",x"069",x"06B",x"06C",x"06F",x"073",x"078",x"07E", -- 0x0A70
x"088",x"095",x"0AB",x"0C5",x"0F8",x"138",x"1BB",x"275", -- 0x0A78
x"072",x"074",x"075",x"077",x"07A",x"07E",x"082",x"088", -- 0x0A80
x"093",x"09F",x"0B5",x"0CF",x"101",x"141",x"1C0",x"275", -- 0x0A88
x"07E",x"080",x"082",x"084",x"086",x"089",x"08F",x"095", -- 0x0A90
x"09F",x"0AB",x"0C1",x"0DA",x"10C",x"14B",x"1CB",x"275", -- 0x0A98
x"096",x"097",x"099",x"09B",x"09D",x"0A0",x"0A5",x"0AB", -- 0x0AA0
x"0B5",x"0C1",x"0D5",x"0EF",x"11F",x"15D",x"1DA",x"27C", -- 0x0AA8
x"0B0",x"0B2",x"0B4",x"0B6",x"0B8",x"0BA",x"0BF",x"0C5", -- 0x0AB0
x"0CF",x"0DA",x"0EF",x"108",x"136",x"172",x"1EC",x"28A", -- 0x0AB8
x"0E5",x"0E7",x"0E8",x"0EA",x"0EC",x"0EE",x"0F3",x"0F8", -- 0x0AC0
x"101",x"10C",x"11E",x"136",x"164",x"1A0",x"213",x"29E", -- 0x0AC8
x"127",x"128",x"12A",x"12B",x"12D",x"12F",x"133",x"137", -- 0x0AD0
x"140",x"14A",x"15D",x"172",x"19F",x"1D7",x"240",x"2C8", -- 0x0AD8
x"1B1",x"1B2",x"1B3",x"1B4",x"1B4",x"1B6",x"1B8",x"1BB", -- 0x0AE0
x"1C0",x"1CB",x"1DA",x"1EC",x"212",x"240",x"2A1",x"320", -- 0x0AE8
x"274",x"274",x"274",x"274",x"274",x"274",x"274",x"274", -- 0x0AF0
x"274",x"274",x"27B",x"288",x"29D",x"2C8",x"320",x"38B", -- 0x0AF8
x"06D",x"06F",x"070",x"072",x"075",x"078",x"07D",x"082", -- 0x0B00
x"08C",x"097",x"0AE",x"0C6",x"0F9",x"13B",x"1C0",x"27D", -- 0x0B08
x"06F",x"071",x"073",x"074",x"077",x"079",x"07E",x"084", -- 0x0B10
x"08E",x"099",x"0AF",x"0C8",x"0FB",x"13C",x"1C1",x"27D", -- 0x0B18
x"070",x"073",x"074",x"076",x"078",x"07B",x"080",x"086", -- 0x0B20
x"08F",x"09B",x"0B1",x"0CA",x"0FD",x"13D",x"1C1",x"27D", -- 0x0B28
x"072",x"074",x"076",x"078",x"07A",x"07D",x"082",x"087", -- 0x0B30
x"091",x"09C",x"0B2",x"0CB",x"0FE",x"13F",x"1C2",x"27D", -- 0x0B38
x"075",x"077",x"078",x"07A",x"07D",x"080",x"084",x"08A", -- 0x0B40
x"094",x"09F",x"0B5",x"0CD",x"100",x"141",x"1C2",x"27D", -- 0x0B48
x"078",x"079",x"07B",x"07D",x"080",x"082",x"087",x"08D", -- 0x0B50
x"097",x"0A1",x"0B7",x"0D0",x"102",x"142",x"1C4",x"27D", -- 0x0B58
x"07D",x"07E",x"080",x"082",x"084",x"087",x"08C",x"092", -- 0x0B60
x"09B",x"0A6",x"0BC",x"0D4",x"106",x"146",x"1C6",x"27D", -- 0x0B68
x"082",x"084",x"086",x"087",x"08A",x"08D",x"092",x"097", -- 0x0B70
x"0A1",x"0AC",x"0C1",x"0D9",x"10B",x"14A",x"1C9",x"27D", -- 0x0B78
x"08C",x"08E",x"08F",x"091",x"094",x"097",x"09B",x"0A1", -- 0x0B80
x"0AA",x"0B5",x"0CA",x"0E3",x"113",x"151",x"1CE",x"27D", -- 0x0B88
x"097",x"099",x"09B",x"09C",x"09F",x"0A1",x"0A6",x"0AC", -- 0x0B90
x"0B5",x"0C1",x"0D5",x"0ED",x"11D",x"15B",x"1D7",x"27D", -- 0x0B98
x"0AE",x"0AF",x"0B1",x"0B2",x"0B5",x"0B7",x"0BC",x"0C1", -- 0x0BA0
x"0CA",x"0D5",x"0E7",x"100",x"12F",x"16B",x"1E5",x"283", -- 0x0BA8
x"0C6",x"0C8",x"0CA",x"0CB",x"0CD",x"0D0",x"0D4",x"0D9", -- 0x0BB0
x"0E3",x"0ED",x"100",x"118",x"145",x"17F",x"1F6",x"290", -- 0x0BB8
x"0F9",x"0FB",x"0FD",x"0FE",x"100",x"102",x"106",x"10B", -- 0x0BC0
x"113",x"11D",x"12E",x"145",x"170",x"1AB",x"21A",x"2A2", -- 0x0BC8
x"139",x"13A",x"13C",x"13D",x"13F",x"141",x"144",x"148", -- 0x0BD0
x"150",x"159",x"16B",x"17F",x"1A9",x"1DF",x"245",x"2CA", -- 0x0BD8
x"1C0",x"1C1",x"1C1",x"1C2",x"1C2",x"1C4",x"1C6",x"1C9", -- 0x0BE0
x"1CE",x"1D7",x"1E5",x"1F6",x"219",x"245",x"2A2",x"31E", -- 0x0BE8
x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B", -- 0x0BF0
x"27B",x"27B",x"282",x"28E",x"2A1",x"2CA",x"31E",x"386", -- 0x0BF8
x"0A5",x"0A7",x"0A8",x"0A9",x"0AB",x"0AE",x"0B2",x"0B7", -- 0x0C00
x"0C0",x"0C9",x"0DD",x"0F3",x"123",x"162",x"1E0",x"292", -- 0x0C08
x"0A7",x"0A8",x"0AA",x"0AB",x"0AE",x"0B0",x"0B4",x"0B9", -- 0x0C10
x"0C1",x"0CB",x"0DE",x"0F5",x"125",x"163",x"1E1",x"292", -- 0x0C18
x"0A8",x"0AA",x"0AB",x"0AD",x"0AF",x"0B1",x"0B6",x"0BA", -- 0x0C20
x"0C2",x"0CC",x"0E0",x"0F6",x"126",x"164",x"1E1",x"292", -- 0x0C28
x"0A9",x"0AB",x"0AD",x"0AE",x"0B0",x"0B2",x"0B7",x"0BB", -- 0x0C30
x"0C4",x"0CD",x"0E1",x"0F8",x"127",x"165",x"1E2",x"292", -- 0x0C38
x"0AB",x"0AE",x"0AF",x"0B0",x"0B2",x"0B5",x"0B9",x"0BD", -- 0x0C40
x"0C6",x"0CF",x"0E3",x"0F9",x"129",x"167",x"1E2",x"292", -- 0x0C48
x"0AE",x"0B0",x"0B1",x"0B2",x"0B5",x"0B7",x"0BB",x"0C0", -- 0x0C50
x"0C9",x"0D2",x"0E5",x"0FB",x"12B",x"168",x"1E3",x"292", -- 0x0C58
x"0B2",x"0B4",x"0B6",x"0B7",x"0B9",x"0BB",x"0C0",x"0C4", -- 0x0C60
x"0CC",x"0D6",x"0E9",x"0FF",x"12E",x"16C",x"1E5",x"292", -- 0x0C68
x"0B7",x"0B9",x"0BA",x"0BB",x"0BD",x"0C0",x"0C4",x"0C9", -- 0x0C70
x"0D1",x"0DB",x"0EE",x"103",x"132",x"16F",x"1E8",x"292", -- 0x0C78
x"0C0",x"0C1",x"0C2",x"0C4",x"0C6",x"0C9",x"0CC",x"0D1", -- 0x0C80
x"0D9",x"0E2",x"0F5",x"10B",x"139",x"175",x"1EC",x"292", -- 0x0C88
x"0C9",x"0CB",x"0CC",x"0CD",x"0CF",x"0D2",x"0D6",x"0DB", -- 0x0C90
x"0E2",x"0EC",x"0FF",x"114",x"142",x"17D",x"1F4",x"292", -- 0x0C98
x"0DD",x"0DE",x"0E0",x"0E1",x"0E3",x"0E5",x"0E9",x"0EE", -- 0x0CA0
x"0F5",x"0FF",x"10E",x"126",x"152",x"18B",x"1FF",x"298", -- 0x0CA8
x"0F3",x"0F5",x"0F6",x"0F8",x"0F9",x"0FB",x"0FF",x"103", -- 0x0CB0
x"10B",x"114",x"126",x"13B",x"164",x"19C",x"20E",x"2A2", -- 0x0CB8
x"123",x"125",x"126",x"127",x"129",x"12B",x"12E",x"132", -- 0x0CC0
x"139",x"142",x"150",x"164",x"18D",x"1C4",x"22E",x"2B2", -- 0x0CC8
x"160",x"161",x"162",x"163",x"164",x"166",x"169",x"16C", -- 0x0CD0
x"173",x"17A",x"18B",x"19C",x"1C2",x"1F4",x"256",x"2D5", -- 0x0CD8
x"1E0",x"1E1",x"1E1",x"1E2",x"1E2",x"1E3",x"1E5",x"1E8", -- 0x0CE0
x"1EC",x"1F4",x"1FF",x"20E",x"22B",x"256",x"2AD",x"324", -- 0x0CE8
x"290",x"290",x"290",x"290",x"290",x"290",x"290",x"290", -- 0x0CF0
x"290",x"290",x"295",x"2A0",x"2B0",x"2D5",x"324",x"388", -- 0x0CF8
x"0EB",x"0ED",x"0EE",x"0EF",x"0F1",x"0F3",x"0F7",x"0FB", -- 0x0D00
x"103",x"10B",x"11E",x"132",x"160",x"19D",x"217",x"2C2", -- 0x0D08
x"0ED",x"0EE",x"0F0",x"0F1",x"0F3",x"0F5",x"0F8",x"0FD", -- 0x0D10
x"104",x"10C",x"11F",x"134",x"162",x"19E",x"217",x"2C2", -- 0x0D18
x"0EE",x"0F0",x"0F1",x"0F2",x"0F4",x"0F6",x"0FA",x"0FE", -- 0x0D20
x"105",x"10E",x"120",x"135",x"163",x"19F",x"217",x"2C2", -- 0x0D28
x"0EF",x"0F1",x"0F2",x"0F3",x"0F5",x"0F7",x"0FB",x"0FF", -- 0x0D30
x"106",x"10F",x"121",x"136",x"164",x"1A0",x"218",x"2C2", -- 0x0D38
x"0F1",x"0F3",x"0F4",x"0F5",x"0F7",x"0F9",x"0FD",x"101", -- 0x0D40
x"108",x"111",x"123",x"137",x"165",x"1A1",x"218",x"2C2", -- 0x0D48
x"0F3",x"0F5",x"0F6",x"0F7",x"0F9",x"0FB",x"0FF",x"103", -- 0x0D50
x"10B",x"113",x"125",x"139",x"167",x"1A3",x"219",x"2C2", -- 0x0D58
x"0F7",x"0F8",x"0FA",x"0FB",x"0FD",x"0FF",x"103",x"107", -- 0x0D60
x"10E",x"116",x"128",x"13C",x"16A",x"1A6",x"21B",x"2C2", -- 0x0D68
x"0FB",x"0FD",x"0FE",x"0FF",x"101",x"103",x"107",x"10B", -- 0x0D70
x"112",x"11A",x"12C",x"140",x"16D",x"1A8",x"21D",x"2C2", -- 0x0D78
x"103",x"104",x"105",x"106",x"108",x"10B",x"10E",x"112", -- 0x0D80
x"119",x"121",x"133",x"147",x"173",x"1AE",x"221",x"2C2", -- 0x0D88
x"10B",x"10C",x"10E",x"10F",x"111",x"113",x"116",x"11A", -- 0x0D90
x"121",x"12A",x"13B",x"14F",x"17B",x"1B5",x"228",x"2C2", -- 0x0D98
x"11E",x"11F",x"120",x"121",x"123",x"125",x"128",x"12C", -- 0x0DA0
x"133",x"13B",x"149",x"15F",x"18B",x"1C1",x"232",x"2C6", -- 0x0DA8
x"132",x"134",x"135",x"136",x"137",x"139",x"13C",x"140", -- 0x0DB0
x"147",x"14F",x"15F",x"173",x"19A",x"1D0",x"23F",x"2D0", -- 0x0DB8
x"160",x"162",x"163",x"164",x"165",x"167",x"16A",x"16D", -- 0x0DC0
x"173",x"17B",x"187",x"19A",x"1C1",x"1F7",x"25C",x"2DE", -- 0x0DC8
x"19A",x"19B",x"19C",x"19D",x"19E",x"1A0",x"1A2",x"1A5", -- 0x0DD0
x"1AB",x"1B2",x"1C1",x"1D0",x"1F3",x"224",x"282",x"2FD", -- 0x0DD8
x"217",x"217",x"217",x"218",x"218",x"219",x"21B",x"21D", -- 0x0DE0
x"221",x"228",x"232",x"23F",x"259",x"282",x"2D5",x"348", -- 0x0DE8
x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE", -- 0x0DF0
x"2BE",x"2BE",x"2C3",x"2CC",x"2DA",x"2FD",x"348",x"3AA", -- 0x0DF8
x"17D",x"17E",x"17E",x"17F",x"181",x"183",x"185",x"188", -- 0x0E00
x"18E",x"194",x"1A4",x"1B5",x"1DF",x"218",x"288",x"325", -- 0x0E08
x"17E",x"17F",x"180",x"180",x"182",x"184",x"186",x"189", -- 0x0E10
x"18F",x"195",x"1A4",x"1B6",x"1E0",x"219",x"288",x"325", -- 0x0E18
x"17E",x"180",x"180",x"182",x"183",x"185",x"187",x"18A", -- 0x0E20
x"18F",x"196",x"1A5",x"1B6",x"1E0",x"219",x"289",x"325", -- 0x0E28
x"17F",x"180",x"182",x"183",x"184",x"185",x"188",x"18B", -- 0x0E30
x"190",x"197",x"1A6",x"1B7",x"1E1",x"21A",x"289",x"325", -- 0x0E38
x"181",x"182",x"183",x"184",x"185",x"187",x"189",x"18C", -- 0x0E40
x"192",x"198",x"1A7",x"1B8",x"1E2",x"21B",x"289",x"325", -- 0x0E48
x"183",x"184",x"185",x"185",x"187",x"188",x"18B",x"18E", -- 0x0E50
x"194",x"199",x"1A9",x"1BA",x"1E4",x"21C",x"28A",x"325", -- 0x0E58
x"185",x"186",x"187",x"188",x"189",x"18B",x"18E",x"191", -- 0x0E60
x"196",x"19C",x"1AB",x"1BC",x"1E6",x"21E",x"28B",x"325", -- 0x0E68
x"188",x"189",x"18A",x"18B",x"18C",x"18E",x"191",x"194", -- 0x0E70
x"199",x"19F",x"1AE",x"1BF",x"1E8",x"220",x"28D",x"325", -- 0x0E78
x"18E",x"18F",x"18F",x"190",x"192",x"194",x"196",x"199", -- 0x0E80
x"19E",x"1A4",x"1B3",x"1C4",x"1ED",x"224",x"290",x"325", -- 0x0E88
x"194",x"195",x"196",x"197",x"198",x"199",x"19C",x"19F", -- 0x0E90
x"1A4",x"1AA",x"1B9",x"1C9",x"1F2",x"229",x"295",x"325", -- 0x0E98
x"1A4",x"1A4",x"1A5",x"1A6",x"1A7",x"1A9",x"1AB",x"1AE", -- 0x0EA0
x"1B3",x"1B9",x"1C3",x"1D8",x"200",x"232",x"29C",x"328", -- 0x0EA8
x"1B5",x"1B6",x"1B6",x"1B7",x"1B8",x"1BA",x"1BC",x"1BF", -- 0x0EB0
x"1C4",x"1C9",x"1D8",x"1E8",x"20B",x"23D",x"2A5",x"32F", -- 0x0EB8
x"1DF",x"1E0",x"1E0",x"1E1",x"1E2",x"1E4",x"1E6",x"1E8", -- 0x0EC0
x"1ED",x"1F2",x"1FB",x"20B",x"22E",x"260",x"2BD",x"339", -- 0x0EC8
x"214",x"214",x"215",x"216",x"217",x"218",x"21A",x"21C", -- 0x0ED0
x"220",x"225",x"232",x"23D",x"25B",x"287",x"2DF",x"352", -- 0x0ED8
x"288",x"288",x"289",x"289",x"289",x"28A",x"28B",x"28D", -- 0x0EE0
x"290",x"295",x"29C",x"2A5",x"2B8",x"2DF",x"32B",x"396", -- 0x0EE8
x"320",x"320",x"320",x"320",x"320",x"320",x"320",x"320", -- 0x0EF0
x"320",x"320",x"324",x"32B",x"335",x"352",x"396",x"3F3", -- 0x0EF8
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F00
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F08
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F10
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F18
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F20
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F28
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F30
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F38
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F40
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F48
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F50
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F58
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F60
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F68
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F70
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F78
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F80
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F88
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F90
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F98
x"254",x"254",x"254",x"254",x"254",x"254",x"254",x"254", -- 0x0FA0
x"254",x"254",x"254",x"264",x"284",x"2AB",x"302",x"379", -- 0x0FA8
x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C", -- 0x0FB0
x"25C",x"25C",x"264",x"26C",x"284",x"2AB",x"302",x"379", -- 0x0FB8
x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C", -- 0x0FC0
x"27C",x"27C",x"27C",x"284",x"29C",x"2C3",x"30A",x"379", -- 0x0FC8
x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3", -- 0x0FD0
x"2A3",x"2A3",x"2AB",x"2AB",x"2BB",x"2DB",x"322",x"381", -- 0x0FD8
x"302",x"302",x"302",x"302",x"302",x"302",x"302",x"302", -- 0x0FE0
x"302",x"302",x"302",x"302",x"302",x"322",x"359",x"3B0", -- 0x0FE8
x"371",x"371",x"371",x"371",x"371",x"371",x"371",x"371", -- 0x0FF0
x"371",x"371",x"371",x"371",x"371",x"381",x"3B0",x"3FF" -- 0x0FF8
);
begin
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= ROM(to_integer(unsigned(ADDR)))(9 downto 0);
end process;
end RTL;

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// taken from the Apple II project by Alex Freed
// and modified for own use
module ramcard(mclk28,reset_in,addr,ram_addr, we, card_ram_we,card_ram_rd, bank1);
input mclk28;
input reset_in;
input [15:0] addr;
output [17:0] ram_addr;
input we;
output card_ram_we;
output card_ram_rd;
output bank1;
reg bank1, read_en, write_en, pre_wr_en, bankB, sat_read_en, sat_write_en, sat_pre_wr_en, sat_en;
reg [2:0] bank16k;
reg [15:0] addr2;
wire Dxxx,DEF;
always @(posedge mclk28) begin
addr2 <= addr;
if(reset_in) begin
bank1 <= 0;
read_en <= 0;
write_en <= 1;
pre_wr_en <= 0;
bankB <= 0;
sat_read_en <= 0;
sat_write_en <= 0;
sat_pre_wr_en <= 0;
end
else
begin
if((addr[15:4] == 'hC08) & (addr2 != addr)) begin
// Looks like a Language Card in slot 0
bank1 <= addr[3];
pre_wr_en <= addr[0] & ~we;
write_en <= addr[0] & pre_wr_en & ~we;
read_en <= ~(addr[0] ^ addr[1]);
end
if((addr[15:4] == 'hC0D) & (addr2 != addr)) begin
// Looks like Saturn128 Card in slot 5
if(addr[2] == 0) begin
// State selection
bankB <= addr[3];
sat_pre_wr_en <= addr[0];
sat_write_en <= addr[0] & sat_pre_wr_en;
sat_read_en <= ~(addr[0] ^ addr[1]);
end
else
begin
// 16K bank selection
bank16k <= {addr[3], addr[1], addr[0]};
end
end
end
end
assign Dxxx = (addr[15:12] == 4'b1101);
assign DEF = ((addr[15:14] == 2'b11) & (addr[13:12] != 2'b00));
assign ram_addr = ((sat_write_en || sat_read_en) && DEF)?{1'b1, bank16k, addr[13], addr[12] & ~(bankB & Dxxx), addr[11:0]}:{2'b0,addr[15:13], addr[12] & ~(bank1 & Dxxx), addr[11:0]};
assign card_ram_we = (write_en | sat_write_en);
assign card_ram_rd = (read_en | sat_read_en);
endmodule

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-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 12288;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 6F D8 65 D7 F8 DC 94 D9 B1 DB 30 F3 D8 DF E1 DB 8F F3 98 F3 E4 F1 DD F1;
0018: D4 F1 24 F2 31 F2 40 F2 D7 F3 E1 F3 E8 F6 FD F6 68 F7 6E F7 E6 F7 57 FC;
0030: 20 F7 26 F7 74 F7 6C F2 6E F2 72 F2 76 F2 7F F2 4E F2 6A D9 55 F2 85 F2;
0048: A5 F2 CA F2 17 F3 BB F3 9E F3 61 F2 45 DA 3D D9 11 D9 C8 D9 48 D8 F4 03;
0060: 20 D9 6A D9 DB D9 6D D8 EB D9 83 E7 C8 D8 AF D8 12 E3 7A E7 D4 DA 95 D8;
0078: A4 D6 69 D6 9F DB 48 D6 90 EB 23 EC AF EB 0A 00 DE E2 12 D4 CD DF FF E2;
0090: 8D EE AE EF 41 E9 09 EF EA EF F1 EF 3A F0 9E F0 64 E7 D6 E6 C5 E3 07 E7;
00A8: E5 E6 46 E6 5A E6 86 E6 91 E6 79 C0 E7 79 A9 E7 7B 81 E9 7B 68 EA 7D 96;
00C0: EE 50 54 DF 46 4E DF 7F CF EE 7F 97 DE 64 64 DF 45 4E C4 46 4F D2 4E 45;
00D8: 58 D4 44 41 54 C1 49 4E 50 55 D4 44 45 CC 44 49 CD 52 45 41 C4 47 D2 54;
00F0: 45 58 D4 50 52 A3 49 4E A3 43 41 4C CC 50 4C 4F D4 48 4C 49 CE 56 4C 49;
0108: CE 48 47 52 B2 48 47 D2 48 43 4F 4C 4F 52 BD 48 50 4C 4F D4 44 52 41 D7;
0120: 58 44 52 41 D7 48 54 41 C2 48 4F 4D C5 52 4F 54 BD 53 43 41 4C 45 BD 53;
0138: 48 4C 4F 41 C4 54 52 41 43 C5 4E 4F 54 52 41 43 C5 4E 4F 52 4D 41 CC 49;
0150: 4E 56 45 52 53 C5 46 4C 41 53 C8 43 4F 4C 4F 52 BD 50 4F D0 56 54 41 C2;
0168: 48 49 4D 45 4D BA 4C 4F 4D 45 4D BA 4F 4E 45 52 D2 52 45 53 55 4D C5 52;
0180: 45 43 41 4C CC 53 54 4F 52 C5 53 50 45 45 44 BD 4C 45 D4 47 4F 54 CF 52;
0198: 55 CE 49 C6 52 45 53 54 4F 52 C5 A6 47 4F 53 55 C2 52 45 54 55 52 CE 52;
01B0: 45 CD 53 54 4F D0 4F CE 57 41 49 D4 4C 4F 41 C4 53 41 56 C5 44 45 C6 50;
01C8: 4F 4B C5 50 52 49 4E D4 43 4F 4E D4 4C 49 53 D4 43 4C 45 41 D2 47 45 D4;
01E0: 4E 45 D7 54 41 42 A8 54 CF 46 CE 53 50 43 A8 54 48 45 CE 41 D4 4E 4F D4;
01F8: 53 54 45 D0 AB AD AA AF DE 41 4E C4 4F D2 BE BD BC 53 47 CE 49 4E D4 41;
0210: 42 D3 55 53 D2 46 52 C5 53 43 52 4E A8 50 44 CC 50 4F D3 53 51 D2 52 4E;
0228: C4 4C 4F C7 45 58 D0 43 4F D3 53 49 CE 54 41 CE 41 54 CE 50 45 45 CB 4C;
0240: 45 CE 53 54 52 A4 56 41 CC 41 53 C3 43 48 52 A4 4C 45 46 54 A4 52 49 47;
0258: 48 54 A4 4D 49 44 A4 00 4E 45 58 54 20 57 49 54 48 4F 55 54 20 46 4F D2;
0270: 53 59 4E 54 41 D8 52 45 54 55 52 4E 20 57 49 54 48 4F 55 54 20 47 4F 53;
0288: 55 C2 4F 55 54 20 4F 46 20 44 41 54 C1 49 4C 4C 45 47 41 4C 20 51 55 41;
02A0: 4E 54 49 54 D9 4F 56 45 52 46 4C 4F D7 4F 55 54 20 4F 46 20 4D 45 4D 4F;
02B8: 52 D9 55 4E 44 45 46 27 44 20 53 54 41 54 45 4D 45 4E D4 42 41 44 20 53;
02D0: 55 42 53 43 52 49 50 D4 52 45 44 49 4D 27 44 20 41 52 52 41 D9 44 49 56;
02E8: 49 53 49 4F 4E 20 42 59 20 5A 45 52 CF 49 4C 4C 45 47 41 4C 20 44 49 52;
0300: 45 43 D4 54 59 50 45 20 4D 49 53 4D 41 54 43 C8 53 54 52 49 4E 47 20 54;
0318: 4F 4F 20 4C 4F 4E C7 46 4F 52 4D 55 4C 41 20 54 4F 4F 20 43 4F 4D 50 4C;
0330: 45 D8 43 41 4E 27 54 20 43 4F 4E 54 49 4E 55 C5 55 4E 44 45 46 27 44 20;
0348: 46 55 4E 43 54 49 4F CE 20 45 52 52 4F 52 07 00 20 49 4E 20 00 0D 42 52;
0360: 45 41 4B 07 00 BA E8 E8 E8 E8 BD 01 01 C9 81 D0 21 A5 86 D0 0A BD 02 01;
0378: 85 85 BD 03 01 85 86 DD 03 01 D0 07 A5 85 DD 02 01 F0 07 8A 18 69 12 AA;
0390: D0 D8 60 20 E3 D3 85 6D 84 6E 38 A5 96 E5 9B 85 5E A8 A5 97 E5 9C AA E8;
03A8: 98 F0 23 A5 96 38 E5 5E 85 96 B0 03 C6 97 38 A5 94 E5 5E 85 94 B0 08 C6;
03C0: 95 90 04 B1 96 91 94 88 D0 F9 B1 96 91 94 C6 97 C6 95 CA D0 F2 60 0A 69;
03D8: 36 B0 35 85 5E BA E4 5E 90 2E 60 C4 70 90 28 D0 04 C5 6F 90 22 48 A2 09;
03F0: 98 48 B5 93 CA 10 FA 20 84 E4 A2 F7 68 95 9D E8 30 FA 68 A8 68 C4 70 90;
0408: 06 D0 05 C5 6F B0 01 60 A2 4D 24 D8 10 03 4C E9 F2 20 FB DA 20 5A DB BD;
0420: 60 D2 48 20 5C DB E8 68 10 F5 20 83 D6 A9 50 A0 D3 20 3A DB A4 76 C8 F0;
0438: 03 20 19 ED 20 FB DA A2 DD 20 2E D5 86 B8 84 B9 46 D8 20 B1 00 AA F0 EC;
0450: A2 FF 86 76 90 06 20 59 D5 4C 05 D8 A6 AF 86 69 A6 B0 86 6A 20 0C DA 20;
0468: 59 D5 84 0F 20 1A D6 90 44 A0 01 B1 9B 85 5F A5 69 85 5E A5 9C 85 61 A5;
0480: 9B 88 F1 9B 18 65 69 85 69 85 60 A5 6A 69 FF 85 6A E5 9C AA 38 A5 9B E5;
0498: 69 A8 B0 03 E8 C6 61 18 65 5E 90 03 C6 5F 18 B1 5E 91 60 C8 D0 F9 E6 5F;
04B0: E6 61 CA D0 F2 AD 00 02 F0 38 A5 73 A4 74 85 6F 84 70 A5 69 85 96 65 0F;
04C8: 85 94 A4 6A 84 97 90 01 C8 84 95 20 93 D3 A5 50 A4 51 8D FE 01 8C FF 01;
04E0: A5 6D A4 6E 85 69 84 6A A4 0F B9 FB 01 88 91 9B D0 F8 20 65 D6 A5 67 A4;
04F8: 68 85 5E 84 5F 18 A0 01 B1 5E D0 0B A5 69 85 AF A5 6A 85 B0 4C 3C D4 A0;
0510: 04 C8 B1 5E D0 FB C8 98 65 5E AA A0 00 91 5E A5 5F 69 00 C8 91 5E 86 5E;
0528: 85 5F 90 D2 A2 80 86 33 20 6A FD E0 EF 90 02 A2 EF A9 00 9D 00 02 8A F0;
0540: 0B BD FF 01 29 7F 9D FF 01 CA D0 F5 A9 00 A2 FF A0 01 60 20 0C FD 29 7F;
0558: 60 A6 B8 CA A0 04 84 13 24 D6 10 08 68 68 20 65 D6 4C D2 D7 E8 BD 00 02;
0570: 24 13 70 04 C9 20 F0 F4 85 0E C9 22 F0 74 70 4D C9 3F D0 04 A9 BA D0 45;
0588: C9 30 90 04 C9 3C 90 3D 84 AD A9 D0 85 9D A9 CF 85 9E A0 00 84 0F 88 86;
05A0: B8 CA C8 D0 02 E6 9E E8 BD 00 02 C9 20 F0 F8 38 F1 9D F0 EE C9 80 D0 41;
05B8: 05 0F C9 C5 D0 0D BD 01 02 C9 4E F0 34 C9 4F F0 30 A9 C5 A4 AD E8 C8 99;
05D0: FB 01 B9 FB 01 F0 39 38 E9 3A F0 04 C9 49 D0 02 85 13 38 E9 78 D0 86 85;
05E8: 0E BD 00 02 F0 DF C5 0E F0 DB C8 99 FB 01 E8 D0 F0 A6 B8 E6 0F B1 9D C8;
0600: D0 02 E6 9E 0A 90 F6 B1 9D D0 9D BD 00 02 10 BB 99 FD 01 C6 B9 A9 FF 85;
0618: B8 60 A5 67 A6 68 A0 01 85 9B 86 9C B1 9B F0 1F C8 C8 A5 51 D1 9B 90 18;
0630: F0 03 88 D0 09 A5 50 88 D1 9B 90 0C F0 0A 88 B1 9B AA 88 B1 9B B0 D7 18;
0648: 60 D0 FD A9 00 85 D6 A8 91 67 C8 91 67 A5 67 69 02 85 69 85 AF A5 68 69;
0660: 00 85 6A 85 B0 20 97 D6 A9 00 D0 2A A5 73 A4 74 85 6F 84 70 A5 69 A4 6A;
0678: 85 6B 84 6C 85 6D 84 6E 20 49 D8 A2 55 86 52 68 A8 68 A2 F8 9A 48 98 48;
0690: A9 00 85 7A 85 14 60 18 A5 67 69 FF 85 B8 A5 68 69 FF 85 B9 60 90 0A F0;
06A8: 08 C9 C9 F0 04 C9 2C D0 E5 20 0C DA 20 1A D6 20 B7 00 F0 10 C9 C9 F0 04;
06C0: C9 2C D0 84 20 B1 00 20 0C DA D0 CA 68 68 A5 50 05 51 D0 06 A9 FF 85 50;
06D8: 85 51 A0 01 B1 9B F0 44 20 58 D8 20 FB DA C8 B1 9B AA C8 B1 9B C5 51 D0;
06F0: 04 E4 50 F0 02 B0 2D 84 85 20 24 ED A9 20 A4 85;
0700: 29 7F 20 5C DB A5 24 C9 21 90 07 20 FB DA A9 05 85 24 C8 B1 9B D0 1D A8;
0718: B1 9B AA C8 B1 9B 86 9B 85 9C D0 B6 A9 0D 20 5C DB 4C D2 D7 C8 D0 02 E6;
0730: 9E B1 9D 60 10 CC 38 E9 7F AA 84 85 A0 D0 84 9D A0 CF 84 9E A0 FF CA F0;
0748: 07 20 2C D7 10 FB 30 F6 A9 20 20 5C DB 20 2C D7 30 05 20 5C DB D0 F6 20;
0760: 5C DB A9 20 D0 98 A9 80 85 14 20 46 DA 20 65 D3 D0 05 8A 69 0F AA 9A 68;
0778: 68 A9 09 20 D6 D3 20 A3 D9 18 98 65 B8 48 A5 B9 69 00 48 A5 76 48 A5 75;
0790: 48 A9 C1 20 C0 DE 20 6A DD 20 67 DD A5 A2 09 7F 25 9E 85 9E A9 AF A0 D7;
07A8: 85 5E 84 5F 4C 20 DE A9 13 A0 E9 20 F9 EA 20 B7 00 C9 C7 D0 06 20 B1 00;
07C0: 20 67 DD 20 82 EB 20 15 DE A5 86 48 A5 85 48 A9 81 48 BA 86 F8 20 58 D8;
07D8: A5 B8 A4 B9 A6 76 E8 F0 04 85 79 84 7A A0 00 B1 B8 D0 57 A0 02 B1 B8 18;
07F0: F0 34 C8 B1 B8 85 75 C8 B1 B8 85 76 98 65 B8 85 B8 90 02 E6 B9 24 F2 10;
0808: 14 A6 76 E8 F0 0F A9 23 20 5C DB A6 75 A5 76 20 24 ED 20 57 DB 20 B1 00;
0820: 20 28 D8 4C D2 D7 F0 62 F0 2D E9 80 90 11 C9 40 B0 14 0A A8 B9 01 D0 48;
0838: B9 00 D0 48 4C B1 00 4C 46 DA C9 3A F0 BF 4C C9 DE 38 A5 67 E9 01 A4 68;
0850: B0 01 88 85 7D 84 7E 60 AD 00 C0 C9 83 F0 01 60 20 53 D5 A2 FF 24 D8 10;
0868: 03 4C E9 F2 C9 03 B0 01 18 D0 3C A5 B8 A4 B9 A6 76 E8 F0 0C 85 79 84 7A;
0880: A5 75 A4 76 85 77 84 78 68 68 A9 5D A0 D3 90 03 4C 31 D4 4C 3C D4 D0 17;
0898: A2 D2 A4 7A D0 03 4C 12 D4 A5 79 85 B8 84 B9 A5 77 A4 78 85 75 84 76 60;
08B0: 38 A5 AF E5 67 85 50 A5 B0 E5 68 85 51 20 F0 D8 20 CD FE 20 01 D9 4C CD;
08C8: FE 20 F0 D8 20 FD FE 18 A5 67 65 50 85 69 A5 68 65 51 85 6A A5 52 85 D6;
08E0: 20 01 D9 20 FD FE 24 D6 10 03 4C 65 D6 4C F2 D4 A9 50 A0 00 85 3C 84 3D;
08F8: A9 52 85 3E 84 3F 84 D6 60 A5 67 A4 68 85 3C 84 3D A5 69 A4 6A 85 3E 84;
0910: 3F 60 08 C6 76 28 D0 03 4C 65 D6 20 6C D6 4C 35 D9 A9 03 20 D6 D3 A5 B9;
0928: 48 A5 B8 48 A5 76 48 A5 75 48 A9 B0 48 20 B7 00 20 3E D9 4C D2 D7 20 0C;
0940: DA 20 A6 D9 A5 76 C5 51 B0 0B 98 38 65 B8 A6 B9 90 07 E8 B0 04 A5 67 A6;
0958: 68 20 1E D6 90 1E A5 9B E9 01 85 B8 A5 9C E9 00 85 B9 60 D0 FD A9 FF 85;
0970: 85 20 65 D3 9A C9 B0 F0 0B A2 16 2C A2 5A 4C 12 D4 4C C9 DE 68 68 C0 42;
0988: F0 3B 85 75 68 85 76 68 85 B8 68 85 B9 20 A3 D9 98 18 65 B8 85 B8 90 02;
09A0: E6 B9 60 A2 3A 2C A2 00 86 0D A0 00 84 0E A5 0E A6 0D 85 0D 86 0E B1 B8;
09B8: F0 E8 C5 0E F0 E4 C8 C9 22 D0 F3 F0 E9 68 68 68 60 20 7B DD 20 B7 00 C9;
09D0: AB F0 05 A9 C4 20 C0 DE A5 9D D0 05 20 A6 D9 F0 B7 20 B7 00 B0 03 4C 3E;
09E8: D9 4C 28 D8 20 F8 E6 48 C9 B0 F0 04 C9 AB D0 89 C6 A1 D0 04 68 4C 2A D8;
0A00: 20 B1 00 20 0C DA C9 2C F0 EE 68 60 A2 00 86 50 86 51 B0 F7 E9 2F 85 0D;
0A18: A5 51 85 5E C9 19 B0 D4 A5 50 0A 26 5E 0A 26 5E 65 50 85 50 A5 5E 65 51;
0A30: 85 51 06 50 26 51 A5 50 65 0D 85 50 90 02 E6 51 20 B1 00 4C 12 DA 20 E3;
0A48: DF 85 85 84 86 A9 D0 20 C0 DE A5 12 48 A5 11 48 20 7B DD 68 2A 20 6D DD;
0A60: D0 18 68 10 12 20 72 EB 20 0C E1 A0 00 A5 A0 91 85 C8 A5 A1 91 85 60 4C;
0A78: 27 EB 68 A0 02 B1 A0 C5 70 90 17 D0 07 88 B1 A0 C5 6F 90 0E A4 A1 C4 6A;
0A90: 90 08 D0 0D A5 A0 C5 69 B0 07 A5 A0 A4 A1 4C B7 DA A0 00 B1 A0 20 D5 E3;
0AA8: A5 8C A4 8D 85 AB 84 AC 20 D4 E5 A9 9D A0 00 85 8C 84 8D 20 35 E6 A0 00;
0AC0: B1 8C 91 85 C8 B1 8C 91 85 C8 B1 8C 91 85 60 20 3D DB 20 B7 00 F0 24 F0;
0AD8: 29 C9 C0 F0 39 C9 C3 18 F0 34 C9 2C 18 F0 1C C9 3B F0 44 20 7B DD 24 11;
0AF0: 30 DD 20 34 ED 20 E7 E3 4C CF DA A9 0D 20 5C DB 49 FF 60 A5 24 C9 18 90;
0B08: 05 20 FB DA D0 21 69 10 29 F0 85 24 90 19 08 20 F5 E6 C9 29 F0 03 4C C9;
0B20: DE 28 90 07 CA 8A E5 24 90 05 AA E8 CA D0 06 20 B1 00 4C D7 DA 20 57 DB;
0B38: D0 F2 20 E7 E3 20 00 E6 AA A0 00 E8 CA F0 BB B1 5E 20 5C DB C8 C9 0D D0;
0B50: F3 20 00 DB 4C 44 DB A9 20 2C A9 3F 09 80 C9 A0 90 02 05 F3 20 ED FD 29;
0B68: 7F 48 A5 F1 20 A8 FC 68 60 A5 15 F0 12 30 04 A0 FF D0 04 A5 7B A4 7C 85;
0B80: 75 84 76 4C C9 DE 68 24 D8 10 05 A2 FE 4C E9 F2 A9 EF A0 DC 20 3A DB A5;
0B98: 79 A4 7A 85 B8 84 B9 60 20 06 E3 A2 01 A0 02 A9 00 8D 01 02 A9 40 20 EB;
0BB0: DB 60 C9 22 D0 0E 20 81 DE A9 3B 20 C0 DE 20 3D DB 4C C7 DB 20 5A DB 20;
0BC8: 06 E3 A9 2C 8D FF 01 20 2C D5 AD 00 02 C9 03 D0 10 4C 63 D8 20 5A DB 4C;
0BE0: 2C D5 A6 7D A4 7E A9 98 2C A9 00 85 15 86 7F 84 80 20 E3 DF 85 85 84 86;
0BF8: A5 B8 A4 B9 85 87 84 88 A6 7F A4 80 86 B8 84 B9 20 B7 00 D0 1E 24 15 50;
0C10: 0E 20 0C FD 29 7F 8D 00 02 A2 FF A0 01 D0 08 30 7F 20 5A DB 20 DC DB 86;
0C28: B8 84 B9 20 B1 00 24 11 10 31 24 15 50 09 E8 86 B8 A9 00 85 0D F0 0C 85;
0C40: 0D C9 22 F0 07 A9 3A 85 0D A9 2C 18 85 0E A5 B8 A4 B9 69 00 90 01 C8 20;
0C58: ED E3 20 3D E7 20 7B DA 4C 72 DC 48 AD 00 02 F0 30 68 20 4A EC A5 12 20;
0C70: 63 DA 20 B7 00 F0 07 C9 2C F0 03 4C 71 DB A5 B8 A4 B9 85 7F 84 80 A5 87;
0C88: A4 88 85 B8 84 B9 20 B7 00 F0 33 20 BE DE 4C F1 DB A5 15 D0 CC 4C 86 DB;
0CA0: 20 A3 D9 C8 AA D0 12 A2 2A C8 B1 B8 F0 5F C8 B1 B8 85 7B C8 B1 B8 C8 85;
0CB8: 7C B1 B8 AA 20 98 D9 E0 83 D0 DD 4C 2B DC A5 7F A4 80 A6 15 10 03 4C 53;
0CD0: D8 A0 00 B1 7F F0 07 A9 DF A0 DC 4C 3A DB 60 3F 45 58 54 52 41 20 49 47;
0CE8: 4E 4F 52 45 44 0D 00 3F 52 45 45 4E 54 45 52 0D 00 D0 04 A0 00 F0 03 20;
0D00: E3 DF 85 85 84 86 20 65 D3 F0 04 A2 00 F0 69 9A E8 E8 E8 E8 8A E8 E8 E8;
0D18: E8 E8 E8 86 60 A0 01 20 F9 EA BA BD 09 01 85 A2 A5 85 A4 86 20 BE E7 20;
0D30: 27 EB A0 01 20 B4 EB BA 38 FD 09 01 F0 17 BD 0F 01 85 75 BD 10 01 85 76;
0D48: BD 12 01 85 B8 BD 11 01 85 B9 4C D2 D7 8A 69 11 AA 9A 20 B7 00 C9 2C D0;
0D60: F1 20 B1 00 20 FF DC 20 7B DD 18 24 38 24 11 30 03 B0 03 60 B0 FD A2 A3;
0D78: 4C 12 D4 A6 B8 D0 02 C6 B9 C6 B8 A2 00 24 48 8A 48 A9 01 20 D6 D3 20 60;
0D90: DE A9 00 85 89 20 B7 00 38 E9 CF 90 17 C9 03 B0 13 C9 01 2A 49 01 45 89;
0DA8: C5 89 90 61 85 89 20 B1 00 4C 98 DD A6 89 D0 2C B0 7B 69 07 90 77 65 11;
0DC0: D0 03 4C 97 E5 69 FF 85 5E 0A 65 5E A8 68 D9 B2 D0 B0 67 20 6A DD 48 20;
0DD8: FD DD 68 A4 87 10 17 AA F0 56 D0 5F 46 11 8A 2A A6 B8 D0 02 C6 B9 C6 B8;
0DF0: A0 1B 85 89 D0 D7 D9 B2 D0 B0 48 90 D9 B9 B4 D0;
0E00: 48 B9 B3 D0 48 20 10 DE A5 89 4C 86 DD 4C C9 DE A5 A2 BE B2 D0 A8 68 85;
0E18: 5E E6 5E 68 85 5F 98 48 20 72 EB A5 A1 48 A5 A0 48 A5 9F 48 A5 9E 48 A5;
0E30: 9D 48 6C 5E 00 A0 FF 68 F0 23 C9 64 F0 03 20 6A DD 84 87 68 4A 85 16 68;
0E48: 85 A5 68 85 A6 68 85 A7 68 85 A8 68 85 A9 68 85 AA 45 A2 85 AB A5 9D 60;
0E60: A9 00 85 11 20 B1 00 B0 03 4C 4A EC 20 7D E0 B0 64 C9 2E F0 F4 C9 C9 F0;
0E78: 55 C9 C8 F0 E7 C9 22 D0 0F A5 B8 A4 B9 69 00 90 01 C8 20 E7 E3 4C 3D E7;
0E90: C9 C6 D0 10 A0 18 D0 38 A5 9D D0 03 A0 01 2C A0 00 4C 01 E3 C9 C2 D0 03;
0EA8: 4C 54 E3 C9 D2 90 03 4C 0C DF 20 BB DE 20 7B DD A9 29 2C A9 28 2C A9 2C;
0EC0: A0 00 D1 B8 D0 03 4C B1 00 A2 10 4C 12 D4 A0 15 68 68 4C D7 DD 20 E3 DF;
0ED8: 85 A0 84 A1 A6 11 F0 05 A2 00 86 AC 60 A6 12 10 0D A0 00 B1 A0 AA C8 B1;
0EF0: A0 A8 8A 4C F2 E2 4C F9 EA 20 B1 00 20 EC F1 8A A4 F0 20 71 F8 A8 20 01;
0F08: E3 4C B8 DE C9 D7 F0 E9 0A 48 AA 20 B1 00 E0 CF 90 20 20 BB DE 20 7B DD;
0F20: 20 BE DE 20 6C DD 68 AA A5 A1 48 A5 A0 48 8A 48 20 F8 E6 68 A8 8A 48 4C;
0F38: 3F DF 20 B2 DE 68 A8 B9 DC CF 85 91 B9 DD CF 85 92 20 90 00 4C 6A DD A5;
0F50: A5 05 9D D0 0B A5 A5 F0 04 A5 9D D0 03 A0 00 2C A0 01 4C 01 E3 20 6D DD;
0F68: B0 13 A5 AA 09 7F 25 A6 85 A6 A9 A5 A0 00 20 B2 EB AA 4C B0 DF A9 00 85;
0F80: 11 C6 89 20 00 E6 85 9D 86 9E 84 9F A5 A8 A4 A9 20 04 E6 86 A8 84 A9 AA;
0F98: 38 E5 9D F0 08 A9 01 90 04 A6 9D A9 FF 85 A2 A0 FF E8 C8 CA D0 07 A6 A2;
0FB0: 30 0F 18 90 0C B1 A8 D1 9E F0 EF A2 FF B0 02 A2 01 E8 8A 2A 25 16 F0 02;
0FC8: A9 01 4C 93 EB 20 FB E6 20 1E FB 4C 01 E3 20 BE DE AA 20 E8 DF 20 B7 00;
0FE0: D0 F4 60 A2 00 20 B7 00 86 10 85 81 20 B7 00 20 7D E0 B0 03 4C C9 DE A2;
0FF8: 00 86 11 86 12 4C 07 E0 4C 28 F1 4C 3C D4 00 20 B1 00 90 05 20 7D E0 90;
1010: 0B AA 20 B1 00 90 FB 20 7D E0 B0 F6 C9 24 D0 06 A9 FF 85 11 D0 10 C9 25;
1028: D0 13 A5 14 30 C6 A9 80 85 12 05 81 85 81 8A 09 80 AA 20 B1 00 86 82 38;
1040: 05 14 E9 28 D0 03 4C 1E E1 24 14 30 02 70 F7 A9 00 85 14 A5 69 A6 6A A0;
1058: 00 86 9C 85 9B E4 6C D0 04 C5 6B F0 22 A5 81 D1 9B D0 08 A5 82 C8 D1 9B;
1070: F0 6C 88 18 A5 9B 69 07 90 E1 E8 D0 DC C9 41 90 05 E9 5B 38 E9 A5 60 68;
1088: 48 C9 D7 D0 0F BA BD 02 01 C9 DE D0 07 A9 9A A0 E0 60 00 00 A5 6B A4 6C;
10A0: 85 9B 84 9C A5 6D A4 6E 85 96 84 97 18 69 07 90 01 C8 85 94 84 95 20 93;
10B8: D3 A5 94 A4 95 C8 85 6B 84 6C A0 00 A5 81 91 9B C8 A5 82 91 9B A9 00 C8;
10D0: 91 9B C8 91 9B C8 91 9B C8 91 9B C8 91 9B A5 9B 18 69 02 A4 9C 90 01 C8;
10E8: 85 83 84 84 60 A5 0F 0A 69 05 65 9B A4 9C 90 01 C8 85 94 84 95 60 90 80;
1100: 00 00 20 B1 00 20 67 DD A5 A2 30 0D A5 9D C9 90 90 09 A9 FE A0 E0 20 B2;
1118: EB D0 7E 4C F2 EB A5 14 D0 47 A5 10 05 12 48 A5 11 48 A0 00 98 48 A5 82;
1130: 48 A5 81 48 20 02 E1 68 85 81 68 85 82 68 A8 BA BD 02 01 48 BD 01 01 48;
1148: A5 A0 9D 02 01 A5 A1 9D 01 01 C8 20 B7 00 C9 2C F0 D2 84 0F 20 B8 DE 68;
1160: 85 11 68 85 12 29 7F 85 10 A6 6B A5 6C 86 9B 85 9C C5 6E D0 04 E4 6D F0;
1178: 3F A0 00 B1 9B C8 C5 81 D0 06 A5 82 D1 9B F0 16 C8 B1 9B 18 65 9B AA C8;
1190: B1 9B 65 9C 90 D7 A2 6B 2C A2 35 4C 12 D4 A2 78 A5 10 D0 F7 A5 14 F0 02;
11A8: 38 60 20 ED E0 A5 0F A0 04 D1 9B D0 E1 4C 4B E2 A5 14 F0 05 A2 2A 4C 12;
11C0: D4 20 ED E0 20 E3 D3 A9 00 A8 85 AE A2 05 A5 81 91 9B 10 01 CA C8 A5 82;
11D8: 91 9B 10 02 CA CA 86 AD A5 0F C8 C8 C8 91 9B A2 0B A9 00 24 10 50 08 68;
11F0: 18 69 01 AA 68 69 00 C8 91 9B C8 8A 91 9B 20 AD E2 86 AD 85 AE A4 5E C6;
1208: 0F D0 DC 65 95 B0 5D 85 95 A8 8A 65 94 90 03 C8 F0 52 20 E3 D3 85 6D 84;
1220: 6E A9 00 E6 AE A4 AD F0 05 88 91 94 D0 FB C6 95 C6 AE D0 F5 E6 95 38 A5;
1238: 6D E5 9B A0 02 91 9B A5 6E C8 E5 9C 91 9B A5 10 D0 62 C8 B1 9B 85 0F A9;
1250: 00 85 AD 85 AE C8 68 AA 85 A0 68 85 A1 D1 9B 90 0E D0 06 C8 8A D1 9B 90;
1268: 07 4C 96 E1 4C 10 D4 C8 A5 AE 05 AD 18 F0 0A 20 AD E2 8A 65 A0 AA 98 A4;
1280: 5E 65 A1 86 AD C6 0F D0 CA 85 AE A2 05 A5 81 10 01 CA A5 82 10 02 CA CA;
1298: 86 64 A9 00 20 B6 E2 8A 65 94 85 83 98 65 95 85 84 A8 A5 83 60 84 5E B1;
12B0: 9B 85 64 88 B1 9B 85 65 A9 10 85 99 A2 00 A0 00 8A 0A AA 98 2A A8 B0 A4;
12C8: 06 AD 26 AE 90 0B 18 8A 65 64 AA 98 65 65 A8 B0 93 C6 99 D0 E3 60 A5 11;
12E0: F0 03 20 00 E6 20 84 E4 38 A5 6F E5 6D A8 A5 70 E5 6E A2 00 86 11 85 9E;
12F8: 84 9F A2 90 4C 9B EB A4 24 A9 00 38 F0 EC A6 76 E8 D0 A1 A2 95 2C A2 E0;
1310: 4C 12 D4 20 41 E3 20 06 E3 20 BB DE A9 80 85 14 20 E3 DF 20 6A DD 20 B8;
1328: DE A9 D0 20 C0 DE 48 A5 84 48 A5 83 48 A5 B9 48 A5 B8 48 20 95 D9 4C AF;
1340: E3 A9 C2 20 C0 DE 09 80 85 14 20 EA DF 85 8A 84 8B 4C 6A DD 20 41 E3 A5;
1358: 8B 48 A5 8A 48 20 B2 DE 20 6A DD 68 85 8A 68 85 8B A0 02 B1 8A 85 83 AA;
1370: C8 B1 8A F0 99 85 84 C8 B1 83 48 88 10 FA A4 84 20 2B EB A5 B9 48 A5 B8;
1388: 48 B1 8A 85 B8 C8 B1 8A 85 B9 A5 84 48 A5 83 48 20 67 DD 68 85 8A 68 85;
13A0: 8B 20 B7 00 F0 03 4C C9 DE 68 85 B8 68 85 B9 A0 00 68 91 8A 68 C8 91 8A;
13B8: 68 C8 91 8A 68 C8 91 8A 68 C8 91 8A 60 20 6A DD A0 00 20 36 ED 68 68 A9;
13D0: FF A0 00 F0 12 A6 A0 A4 A1 86 8C 84 8D 20 52 E4 86 9E 84 9F 85 9D 60 A2;
13E8: 22 86 0D 86 0E 85 AB 84 AC 85 9E 84 9F A0 FF C8 B1 AB F0 0C C5 0D F0 04;
1400: C5 0E D0 F3 C9 22 F0 01 18 84 9D 98 65 AB 85 AD A6 AC 90 01 E8 86 AE A5;
1418: AC F0 04 C9 02 D0 0B 98 20 D5 E3 A6 AB A4 AC 20 E2 E5 A6 52 E0 5E D0 05;
1430: A2 BF 4C 12 D4 A5 9D 95 00 A5 9E 95 01 A5 9F 95 02 A0 00 86 A0 84 A1 88;
1448: 84 11 86 53 E8 E8 E8 86 52 60 46 13 48 49 FF 38 65 6F A4 70 B0 01 88 C4;
1460: 6E 90 11 D0 04 C5 6D 90 0B 85 6F 84 70 85 71 84 72 AA 68 60 A2 4D A5 13;
1478: 30 B8 20 84 E4 A9 80 85 13 68 D0 D0 A6 73 A5 74 86 6F 85 70 A0 00 84 8B;
1490: A5 6D A6 6E 85 9B 86 9C A9 55 A2 00 85 5E 86 5F C5 52 F0 05 20 23 E5 F0;
14A8: F7 A9 07 85 8F A5 69 A6 6A 85 5E 86 5F E4 6C D0 04 C5 6B F0 05 20 19 E5;
14C0: F0 F3 85 94 86 95 A9 03 85 8F A5 94 A6 95 E4 6E D0 07 C5 6D D0 03 4C 62;
14D8: E5 85 5E 86 5F A0 00 B1 5E AA C8 B1 5E 08 C8 B1 5E 65 94 85 94 C8 B1 5E;
14F0: 65 95 85 95 28 10 D3 8A 30 D0 C8 B1 5E A0 00 0A;
1500: 69 05 65 5E 85 5E 90 02 E6 5F A6 5F E4 95 D0 04 C5 94 F0 BA 20 23 E5 F0;
1518: F3 B1 5E 30 35 C8 B1 5E 10 30 C8 B1 5E F0 2B C8 B1 5E AA C8 B1 5E C5 70;
1530: 90 06 D0 1E E4 6F B0 1A C5 9C 90 16 D0 04 E4 9B 90 10 86 9B 85 9C A5 5E;
1548: A6 5F 85 8A 86 8B A5 8F 85 91 A5 8F 18 65 5E 85 5E 90 02 E6 5F A6 5F A0;
1560: 00 60 A6 8B F0 F7 A5 91 29 04 4A A8 85 91 B1 8A 65 9B 85 96 A5 9C 69 00;
1578: 85 97 A5 6F A6 70 85 94 86 95 20 9A D3 A4 91 C8 A5 94 91 8A AA E6 95 A5;
1590: 95 C8 91 8A 4C 88 E4 A5 A1 48 A5 A0 48 20 60 DE 20 6C DD 68 85 AB 68 85;
15A8: AC A0 00 B1 AB 18 71 A0 90 05 A2 B0 4C 12 D4 20 D5 E3 20 D4 E5 A5 8C A4;
15C0: 8D 20 04 E6 20 E6 E5 A5 AB A4 AC 20 04 E6 20 2A E4 4C 95 DD A0 00 B1 AB;
15D8: 48 C8 B1 AB AA C8 B1 AB A8 68 86 5E 84 5F A8 F0 0A 48 88 B1 5E 91 71 98;
15F0: D0 F8 68 18 65 71 85 71 90 02 E6 72 60 20 6C DD A5 A0 A4 A1 85 5E 84 5F;
1608: 20 35 E6 08 A0 00 B1 5E 48 C8 B1 5E AA C8 B1 5E A8 68 28 D0 13 C4 70 D0;
1620: 0F E4 6F D0 0B 48 18 65 6F 85 6F 90 02 E6 70 68 86 5E 84 5F 60 C4 54 D0;
1638: 0C C5 53 D0 08 85 52 E9 03 85 53 A0 00 60 20 FB E6 8A 48 A9 01 20 DD E3;
1650: 68 A0 00 91 9E 68 68 4C 2A E4 20 B9 E6 D1 8C 98 90 04 B1 8C AA 98 48 8A;
1668: 48 20 DD E3 A5 8C A4 8D 20 04 E6 68 A8 68 18 65 5E 85 5E 90 02 E6 5F 98;
1680: 20 E6 E5 4C 2A E4 20 B9 E6 18 F1 8C 49 FF 4C 60 E6 A9 FF 85 A1 20 B7 00;
1698: C9 29 F0 06 20 BE DE 20 F8 E6 20 B9 E6 CA 8A 48 18 A2 00 F1 8C B0 B8 49;
16B0: FF C5 A1 90 B3 A5 A1 B0 AF 20 B8 DE 68 A8 68 85 91 68 68 68 AA 68 85 8C;
16C8: 68 85 8D A5 91 48 98 48 A0 00 8A F0 1D 60 20 DC E6 4C 01 E3 20 FD E5 A2;
16E0: 00 86 11 A8 60 20 DC E6 F0 08 A0 00 B1 5E A8 4C 01 E3 4C 99 E1 20 B1 00;
16F8: 20 67 DD 20 08 E1 A6 A0 D0 F0 A6 A1 4C B7 00 20 DC E6 D0 03 4C 4E E8 A6;
1710: B8 A4 B9 86 AD 84 AE A6 5E 86 B8 18 65 5E 85 60 A6 5F 86 B9 90 01 E8 86;
1728: 61 A0 00 B1 60 48 A9 00 91 60 20 B7 00 20 4A EC 68 A0 00 91 60 A6 AD A4;
1740: AE 86 B8 84 B9 60 20 67 DD 20 52 E7 20 BE DE 4C F8 E6 A5 9D C9 91 B0 9A;
1758: 20 F2 EB A5 A0 A4 A1 84 50 85 51 60 A5 50 48 A5 51 48 20 52 E7 A0 00 B1;
1770: 50 A8 68 85 51 68 85 50 4C 01 E3 20 46 E7 8A A0 00 91 50 60 20 46 E7 86;
1788: 85 A2 00 20 B7 00 F0 03 20 4C E7 86 86 A0 00 B1 50 45 86 25 85 F0 F8 60;
17A0: A9 64 A0 EE 4C BE E7 20 E3 E9 A5 A2 49 FF 85 A2 45 AA 85 AB A5 9D 4C C1;
17B8: E7 20 F0 E8 90 3C 20 E3 E9 D0 03 4C 53 EB A6 AC 86 92 A2 A5 A5 A5 A8 F0;
17D0: CE 38 E5 9D F0 24 90 12 84 9D A4 AA 84 A2 49 FF 69 00 A0 00 84 92 A2 9D;
17E8: D0 04 A0 00 84 AC C9 F9 30 C7 A8 A5 AC 56 01 20 07 E9 24 AB 10 57 A0 9D;
1800: E0 A5 F0 02 A0 A5 38 49 FF 65 92 85 AC B9 04 00 F5 04 85 A1 B9 03 00 F5;
1818: 03 85 A0 B9 02 00 F5 02 85 9F B9 01 00 F5 01 85 9E B0 03 20 9E E8 A0 00;
1830: 98 18 A6 9E D0 4A A6 9F 86 9E A6 A0 86 9F A6 A1 86 A0 A6 AC 86 A1 84 AC;
1848: 69 08 C9 20 D0 E4 A9 00 85 9D 85 A2 60 65 92 85 AC A5 A1 65 A9 85 A1 A5;
1860: A0 65 A8 85 A0 A5 9F 65 A7 85 9F A5 9E 65 A6 85 9E 4C 8D E8 69 01 06 AC;
1878: 26 A1 26 A0 26 9F 26 9E 10 F2 38 E5 9D B0 C7 49 FF 69 01 85 9D 90 0E E6;
1890: 9D F0 42 66 9E 66 9F 66 A0 66 A1 66 AC 60 A5 A2 49 FF 85 A2 A5 9E 49 FF;
18A8: 85 9E A5 9F 49 FF 85 9F A5 A0 49 FF 85 A0 A5 A1 49 FF 85 A1 A5 AC 49 FF;
18C0: 85 AC E6 AC D0 0E E6 A1 D0 0A E6 A0 D0 06 E6 9F D0 02 E6 9E 60 A2 45 4C;
18D8: 12 D4 A2 61 B4 04 84 AC B4 03 94 04 B4 02 94 03 B4 01 94 02 A4 A4 94 01;
18F0: 69 08 30 E8 F0 E6 E9 08 A8 A5 AC B0 14 16 01 90 02 F6 01 76 01 76 01 76;
1908: 02 76 03 76 04 6A C8 D0 EC 18 60 81 00 00 00 00 03 7F 5E 56 CB 79 80 13;
1920: 9B 0B 64 80 76 38 93 16 82 38 AA 3B 20 80 35 04 F3 34 81 35 04 F3 34 80;
1938: 80 00 00 00 80 31 72 17 F8 20 82 EB F0 02 10 03 4C 99 E1 A5 9D E9 7F 48;
1950: A9 80 85 9D A9 2D A0 E9 20 BE E7 A9 32 A0 E9 20 66 EA A9 13 A0 E9 20 A7;
1968: E7 A9 18 A0 E9 20 5C EF A9 37 A0 E9 20 BE E7 68 20 D5 EC A9 3C A0 E9 20;
1980: E3 E9 D0 03 4C E2 E9 20 0E EA A9 00 85 62 85 63 85 64 85 65 A5 AC 20 B0;
1998: E9 A5 A1 20 B0 E9 A5 A0 20 B0 E9 A5 9F 20 B0 E9 A5 9E 20 B5 E9 4C E6 EA;
19B0: D0 03 4C DA E8 4A 09 80 A8 90 19 18 A5 65 65 A9 85 65 A5 64 65 A8 85 64;
19C8: A5 63 65 A7 85 63 A5 62 65 A6 85 62 66 62 66 63 66 64 66 65 66 AC 98 4A;
19E0: D0 D6 60 85 5E 84 5F A0 04 B1 5E 85 A9 88 B1 5E 85 A8 88 B1 5E 85 A7 88;
19F8: B1 5E 85 AA 45 A2 85 AB A5 AA 09 80 85 A6 88 B1 5E 85 A5 A5 9D 60 A5 A5;
1A10: F0 1F 18 65 9D 90 04 30 1D 18 2C 10 14 69 80 85 9D D0 03 4C 52 E8 A5 AB;
1A28: 85 A2 60 A5 A2 49 FF 30 05 68 68 4C 4E E8 4C D5 E8 20 63 EB AA F0 10 18;
1A40: 69 02 B0 F2 A2 00 86 AB 20 CE E7 E6 9D F0 E7 60 84 20 00 00 00 20 63 EB;
1A58: A9 50 A0 EA A2 00 86 AB 20 F9 EA 4C 69 EA 20 E3 E9 F0 76 20 72 EB A9 00;
1A70: 38 E5 9D 85 9D 20 0E EA E6 9D F0 BA A2 FC A9 01 A4 A6 C4 9E D0 10 A4 A7;
1A88: C4 9F D0 0A A4 A8 C4 A0 D0 04 A4 A9 C4 A1 08 2A 90 09 E8 95 65 F0 32 10;
1AA0: 34 A9 01 28 B0 0E 06 A9 26 A8 26 A7 26 A6 B0 E6 30 CE 10 E2 A8 A5 A9 E5;
1AB8: A1 85 A9 A5 A8 E5 A0 85 A8 A5 A7 E5 9F 85 A7 A5 A6 E5 9E 85 A6 98 4C A6;
1AD0: EA A9 40 D0 CE 0A 0A 0A 0A 0A 0A 85 AC 28 4C E6 EA A2 85 4C 12 D4 A5 62;
1AE8: 85 9E A5 63 85 9F A5 64 85 A0 A5 65 85 A1 4C 2E E8 85 5E 84 5F A0 04 B1;
1B00: 5E 85 A1 88 B1 5E 85 A0 88 B1 5E 85 9F 88 B1 5E 85 A2 09 80 85 9E 88 B1;
1B18: 5E 85 9D 84 AC 60 A2 98 2C A2 93 A0 00 F0 04 A6 85 A4 86 20 72 EB 86 5E;
1B30: 84 5F A0 04 A5 A1 91 5E 88 A5 A0 91 5E 88 A5 9F 91 5E 88 A5 A2 09 7F 25;
1B48: 9E 91 5E 88 A5 9D 91 5E 84 AC 60 A5 AA 85 A2 A2 05 B5 A4 95 9C CA D0 F9;
1B60: 86 AC 60 20 72 EB A2 06 B5 9C 95 A4 CA D0 F9 86 AC 60 A5 9D F0 FB 06 AC;
1B78: 90 F7 20 C6 E8 D0 F2 4C 8F E8 A5 9D F0 09 A5 A2 2A A9 FF B0 02 A9 01 60;
1B90: 20 82 EB 85 9E A9 00 85 9F A2 88 A5 9E 49 FF 2A A9 00 85 A1 85 A0 86 9D;
1BA8: 85 AC 85 A2 4C 29 E8 46 A2 60 85 60 84 61 A0 00 B1 60 C8 AA F0 C4 B1 60;
1BC0: 45 A2 30 C2 E4 9D D0 21 B1 60 09 80 C5 9E D0 19 C8 B1 60 C5 9F D0 12 C8;
1BD8: B1 60 C5 A0 D0 0B C8 A9 7F C5 AC B1 60 E5 A1 F0 28 A5 A2 90 02 49 FF 4C;
1BF0: 88 EB A5 9D F0 4A 38 E9 A0 24 A2 10 09 AA A9 FF;
1C00: 85 A4 20 A4 E8 8A A2 9D C9 F9 10 06 20 F0 E8 84 A4 60 A8 A5 A2 29 80 46;
1C18: 9E 05 9E 85 9E 20 07 E9 84 A4 60 A5 9D C9 A0 B0 20 20 F2 EB 84 AC A5 A2;
1C30: 84 A2 49 80 2A A9 A0 85 9D A5 A1 85 0D 4C 29 E8 85 9E 85 9F 85 A0 85 A1;
1C48: A8 60 A0 00 A2 0A 94 99 CA 10 FB 90 0F C9 2D D0 04 86 A3 F0 04 C9 2B D0;
1C60: 05 20 B1 00 90 5B C9 2E F0 2E C9 45 D0 30 20 B1 00 90 17 C9 C9 F0 0E C9;
1C78: 2D F0 0A C9 C8 F0 08 C9 2B F0 04 D0 07 66 9C 20 B1 00 90 5C 24 9C 10 0E;
1C90: A9 00 38 E5 9A 4C A0 EC 66 9B 24 9B 50 C3 A5 9A 38 E5 99 85 9A F0 12 10;
1CA8: 09 20 55 EA E6 9A D0 F9 F0 07 20 39 EA C6 9A D0 F9 A5 A3 30 01 60 4C D0;
1CC0: EE 48 24 9B 10 02 E6 99 20 39 EA 68 38 E9 30 20 D5 EC 4C 61 EC 48 20 63;
1CD8: EB 68 20 93 EB A5 AA 45 A2 85 AB A6 9D 4C C1 E7 A5 9A C9 0A 90 09 A9 64;
1CF0: 24 9C 30 11 4C D5 E8 0A 0A 18 65 9A 0A 18 A0 00 71 B8 38 E9 30 85 9A 4C;
1D08: 87 EC 9B 3E BC 1F FD 9E 6E 6B 27 FD 9E 6E 6B 28 00 A9 58 A0 D3 20 31 ED;
1D20: A5 76 A6 75 85 9E 86 9F A2 90 38 20 A0 EB 20 34 ED 4C 3A DB A0 01 A9 2D;
1D38: 88 24 A2 10 04 C8 99 FF 00 85 A2 84 AD C8 A9 30 A6 9D D0 03 4C 57 EE A9;
1D50: 00 E0 80 F0 02 B0 09 A9 14 A0 ED 20 7F E9 A9 F7 85 99 A9 0F A0 ED 20 B2;
1D68: EB F0 1E 10 12 A9 0A A0 ED 20 B2 EB F0 02 10 0E 20 39 EA C6 99 D0 EE 20;
1D80: 55 EA E6 99 D0 DC 20 A0 E7 20 F2 EB A2 01 A5 99 18 69 0A 30 09 C9 0B B0;
1D98: 06 69 FF AA A9 02 38 E9 02 85 9A 86 99 8A F0 02 10 13 A4 AD A9 2E C8 99;
1DB0: FF 00 8A F0 06 A9 30 C8 99 FF 00 84 AD A0 00 A2 80 A5 A1 18 79 6C EE 85;
1DC8: A1 A5 A0 79 6B EE 85 A0 A5 9F 79 6A EE 85 9F A5 9E 79 69 EE 85 9E E8 B0;
1DE0: 04 10 DE 30 02 30 DA 8A 90 04 49 FF 69 0A 69 2F C8 C8 C8 C8 84 83 A4 AD;
1DF8: C8 AA 29 7F 99 FF 00 C6 99 D0 06 A9 2E C8 99 FF 00 84 AD A4 83 8A 49 FF;
1E10: 29 80 AA C0 24 D0 AA A4 AD B9 FF 00 88 C9 30 F0 F8 C9 2E F0 01 C8 A9 2B;
1E28: A6 9A F0 2E 10 08 A9 00 38 E5 9A AA A9 2D 99 01 01 A9 45 99 00 01 8A A2;
1E40: 2F 38 E8 E9 0A B0 FB 69 3A 99 03 01 8A 99 02 01 A9 00 99 04 01 F0 08 99;
1E58: FF 00 A9 00 99 00 01 A9 00 A0 01 60 80 00 00 00 00 FA 0A 1F 00 00 98 96;
1E70: 80 FF F0 BD C0 00 01 86 A0 FF FF D8 F0 00 00 03 E8 FF FF FF 9C 00 00 00;
1E88: 0A FF FF FF FF 20 63 EB A9 64 A0 EE 20 F9 EA F0 70 A5 A5 D0 03 4C 50 E8;
1EA0: A2 8A A0 00 20 2B EB A5 AA 10 0F 20 23 EC A9 8A A0 00 20 B2 EB D0 03 98;
1EB8: A4 0D 20 55 EB 98 48 20 41 E9 A9 8A A0 00 20 7F E9 20 09 EF 68 4A 90 0A;
1ED0: A5 9D F0 06 A5 A2 49 FF 85 A2 60 81 38 AA 3B 29 07 71 34 58 3E 56 74 16;
1EE8: 7E B3 1B 77 2F EE E3 85 7A 1D 84 1C 2A 7C 63 59 58 0A 7E 75 FD E7 C6 80;
1F00: 31 72 18 10 81 00 00 00 00 A9 DB A0 EE 20 7F E9 A5 AC 69 50 90 03 20 7A;
1F18: EB 85 92 20 66 EB A5 9D C9 88 90 03 20 2B EA 20 23 EC A5 0D 18 69 81 F0;
1F30: F3 38 E9 01 48 A2 05 B5 A5 B4 9D 95 9D 94 A5 CA 10 F5 A5 92 85 AC 20 AA;
1F48: E7 20 D0 EE A9 E0 A0 EE 20 72 EF A9 00 85 AB 68 20 10 EA 60 85 AD 84 AE;
1F60: 20 21 EB A9 93 20 7F E9 20 76 EF A9 93 A0 00 4C 7F E9 85 AD 84 AE 20 1E;
1F78: EB B1 AD 85 A3 A4 AD C8 98 D0 02 E6 AE 85 AD A4 AE 20 7F E9 A5 AD A4 AE;
1F90: 18 69 05 90 01 C8 85 AD 84 AE 20 BE E7 A9 98 A0 00 C6 A3 D0 E4 60 98 35;
1FA8: 44 7A 68 28 B1 46 20 82 EB AA 30 18 A9 C9 A0 00 20 F9 EA 8A F0 E7 A9 A6;
1FC0: A0 EF 20 7F E9 A9 AA A0 EF 20 BE E7 A6 A1 A5 9E 85 A1 86 9E A9 00 85 A2;
1FD8: A5 9D 85 AC A9 80 85 9D 20 2E E8 A2 C9 A0 00 4C 2B EB A9 66 A0 F0 20 BE;
1FF0: E7 20 63 EB A9 6B A0 F0 A6 AA 20 5E EA 20 63 EB 20 23 EC A9 00 85 AB 20;
2008: AA E7 A9 70 A0 F0 20 A7 E7 A5 A2 48 10 0D 20 A0 E7 A5 A2 30 09 A5 16 49;
2020: FF 85 16 20 D0 EE A9 70 A0 F0 20 BE E7 68 10 03 20 D0 EE A9 75 A0 F0 4C;
2038: 5C EF 20 21 EB A9 00 85 16 20 F1 EF A2 8A A0 00 20 E7 EF A9 93 A0 00 20;
2050: F9 EA A9 00 85 A2 A5 16 20 62 F0 A9 8A A0 00 4C 66 EA 48 4C 23 F0 81 49;
2068: 0F DA A2 83 49 0F DA A2 7F 00 00 00 00 05 84 E6 1A 2D 1B 86 28 07 FB F8;
2080: 87 99 68 89 01 87 23 35 DF E1 86 A5 5D E7 28 83 49 0F DA A2 A6 D3 C1 C8;
2098: D4 C8 D5 C4 CE CA A5 A2 48 10 03 20 D0 EE A5 9D 48 C9 81 90 07 A9 13 A0;
20B0: E9 20 66 EA A9 CE A0 F0 20 5C EF 68 C9 81 90 07 A9 66 A0 F0 20 A7 E7 68;
20C8: 10 03 4C D0 EE 60 0B 76 B3 83 BD D3 79 1E F4 A6 F5 7B 83 FC B0 10 7C 0C;
20E0: 1F 67 CA 7C DE 53 CB C1 7D 14 64 70 4C 7D B7 EA 51 7A 7D 63 30 88 7E 7E;
20F8: 92 44 99 3A 7E 4C CC 91 C7 7F AA AA AA 13 81 00 00 00 00 E6 B8 D0 02 E6;
2110: B9 AD 60 EA C9 3A B0 0A C9 20 F0 EF 38 E9 30 38 E9 D0 60 80 4F C7 52 58;
2128: A2 FF 86 76 A2 FB 9A A9 28 A0 F1 85 01 84 02 85 04 84 05 20 73 F2 A9 4C;
2140: 85 00 85 03 85 90 85 0A A9 99 A0 E1 85 0B 84 0C A2 1C BD 0A F1 95 B0 86;
2158: F1 CA D0 F6 86 F2 8A 85 A4 85 54 48 A9 03 85 8F 20 FB DA A9 01 8D FD 01;
2170: 8D FC 01 A2 55 86 52 A9 00 A0 08 85 50 84 51 A0 00 E6 51 B1 50 49 FF 91;
2188: 50 D1 50 D0 08 49 FF 91 50 D1 50 F0 EC A4 50 A5 51 29 F0 84 73 85 74 84;
21A0: 6F 85 70 A2 00 A0 08 86 67 84 68 A0 00 84 D6 98 91 67 E6 67 D0 02 E6 68;
21B8: A5 67 A4 68 20 E3 D3 20 4B D6 A9 3A A0 DB 85 04 84 05 A9 3C A0 D4 85 01;
21D0: 84 02 6C 01 00 20 67 DD 20 52 E7 6C 50 00 20 F8 E6 8A 4C 8B FE 20 F8 E6;
21E8: 8A 4C 95 FE 20 F8 E6 E0 30 B0 13 86 F0 A9 2C 20 C0 DE 20 F8 E6 E0 30 B0;
2200: 05 86 2C 86 2D 60 4C 99 E1 20 EC F1 E4 F0 B0 08 A5 F0 85 2C 85 2D 86 F0;
2218: A9 C5 20 C0 DE 20 F8 E6 E0 30 B0 E2 60 20 EC F1 8A A4 F0 C0 28 B0 D7 4C;
2230: 00 F8 20 09 F2 8A A4 2C C0 28 B0 CA A4 F0 4C 19 F8 20 09 F2 8A A8 C0 28;
2248: B0 BC A5 F0 4C 28 F8 20 F8 E6 8A 4C 64 F8 20 F8 E6 CA 8A C9 18 B0 A7 4C;
2260: 5B FB 20 F8 E6 8A 49 FF AA E8 86 F1 60 38 90 18 66 F2 60 A9 FF D0 02 A9;
2278: 3F A2 00 85 32 86 F3 60 A9 7F A2 40 D0 F5 20 67 DD 20 52 E7 A5 50 C5 6D;
2290: A5 51 E5 6E B0 03 4C 10 D4 A5 50 85 73 85 6F A5 51 85 74 85 70 60 20 67;
22A8: DD 20 52 E7 A5 50 C5 73 A5 51 E5 74 B0 E0 A5 50 C5 69 A5 51 E5 6A 90 D6;
22C0: A5 50 85 69 A5 51 85 6A 4C 6C D6 A9 AB 20 C0 DE A5 B8 85 F4 A5 B9 85 F5;
22D8: 38 66 D8 A5 75 85 F6 A5 76 85 F7 20 A6 D9 4C 98 D9 86 DE A6 F8 86 DF A5;
22F0: 75 85 DA A5 76 85 DB A5 79 85 DC A5 7A 85 DD A5;
2300: F4 85 B8 A5 F5 85 B9 A5 F6 85 75 A5 F7 85 76 20 B7 00 20 3E D9 4C D2 D7;
2318: A5 DA 85 75 A5 DB 85 76 A5 DC 85 B8 A5 DD 85 B9 A6 DF 9A 4C D2 D7 4C C9;
2330: DE B0 FB A6 AF 86 69 A6 B0 86 6A 20 0C DA 20 1A D6 A5 9B 85 60 A5 9C 85;
2348: 61 A9 2C 20 C0 DE 20 0C DA E6 50 D0 02 E6 51 20 1A D6 A5 9B C5 60 A5 9C;
2360: E5 61 B0 01 60 A0 00 B1 9B 91 60 E6 9B D0 02 E6 9C E6 60 D0 02 E6 61 A5;
2378: 69 C5 9B A5 6A E5 9C B0 E6 A6 61 A4 60 D0 01 CA 88 86 6A 84 69 4C F2 D4;
2390: AD 56 C0 AD 53 C0 4C 40 FB AD 54 C0 4C 39 FB 20 D9 F7 A0 03 B1 9B AA 88;
23A8: B1 9B E9 01 B0 01 CA 85 50 86 51 20 CD FE 20 BC F7 4C CD FE 20 D9 F7 20;
23C0: FD FE A0 02 B1 9B C5 50 C8 B1 9B E5 51 B0 03 4C 10 D4 20 BC F7 4C FD FE;
23D8: 2C 55 C0 2C 52 C0 A9 40 D0 08 A9 20 2C 54 C0 2C 53 C0 85 E6 AD 57 C0 AD;
23F0: 50 C0 A9 00 85 1C A5 E6 85 1B A0 00 84 1A A5 1C 91 1A 20 7E F4 C8 D0 F6;
2408: E6 1B A5 1B 29 1F D0 EE 60 85 E2 86 E0 84 E1 48 29 C0 85 26 4A 4A 05 26;
2420: 85 26 68 85 27 0A 0A 0A 26 27 0A 26 27 0A 66 26 A5 27 29 1F 05 E6 85 27;
2438: 8A C0 00 F0 05 A0 23 69 04 C8 E9 07 B0 FB 84 E5 AA BD B9 F4 85 30 98 4A;
2450: A5 E4 85 1C B0 28 60 20 11 F4 A5 1C 51 26 25 30 51 26 91 26 60 10 23 A5;
2468: 30 4A B0 05 49 C0 85 30 60 88 10 02 A0 27 A9 C0 85 30 84 E5 A5 1C 0A C9;
2480: C0 10 06 A5 1C 49 7F 85 1C 60 A5 30 0A 49 80 30 DD A9 81 C8 C0 28 90 E0;
2498: A0 00 B0 DC 18 A5 D1 29 04 F0 25 A9 7F 25 30 31 26 D0 19 E6 EA A9 7F 25;
24B0: 30 10 11 18 A5 D1 29 04 F0 0E B1 26 45 1C 25 30 D0 02 E6 EA 51 26 91 26;
24C8: A5 D1 65 D3 29 03 C9 02 6A B0 92 30 30 18 A5 27 2C B9 F5 D0 22 06 26 B0;
24E0: 1A 2C CD F4 F0 05 69 1F 38 B0 12 69 23 48 A5 26 69 B0 B0 02 69 F0 85 26;
24F8: 68 B0 02 69 1F 66 26 69 FC 85 27 60 18 A5 27 69 04 2C B9 F5 D0 F3 06 26;
2510: 90 18 69 E0 18 2C 08 F5 F0 12 A5 26 69 50 49 F0 F0 02 49 F0 85 26 A5 E6;
2528: 90 02 69 E0 66 26 90 D1 48 A9 00 85 E0 85 E1 85 E2 68 48 38 E5 E0 48 8A;
2540: E5 E1 85 D3 B0 0A 68 49 FF 69 01 48 A9 00 E5 D3 85 D1 85 D5 68 85 D0 85;
2558: D4 68 85 E0 86 E1 98 18 E5 E2 90 04 49 FF 69 FE 85 D2 84 E2 66 D3 38 E5;
2570: D0 AA A9 FF E5 D1 85 1D A4 E5 B0 05 0A 20 65 F4 38 A5 D4 65 D2 85 D4 A5;
2588: D5 E9 00 85 D5 B1 26 45 1C 25 30 51 26 91 26 E8 D0 04 E6 1D F0 62 A5 D3;
25A0: B0 DA 20 D3 F4 18 A5 D4 65 D0 85 D4 A5 D5 65 D1 50 D9 81 82 84 88 90 A0;
25B8: C0 1C FF FE FA F4 EC E1 D4 C5 B4 A1 8D 78 61 49 31 18 FF A5 26 0A A5 27;
25D0: 29 03 2A 05 26 0A 0A 0A 85 E2 A5 27 4A 4A 29 07 05 E2 85 E2 A5 E5 0A 65;
25E8: E5 0A AA CA A5 30 29 7F E8 4A D0 FC 85 E1 8A 18 65 E5 90 02 E6 E1 85 E0;
2600: 60 86 1A 84 1B AA 4A 4A 4A 4A 85 D3 8A 29 0F AA BC BA F5 84 D0 49 0F AA;
2618: BC BB F5 C8 84 D2 A4 E5 A2 00 86 EA A1 1A 85 D1 A2 80 86 D4 86 D5 A6 E7;
2630: A5 D4 38 65 D0 85 D4 90 04 20 B3 F4 18 A5 D5 65 D2 85 D5 90 03 20 B4 F4;
2648: CA D0 E5 A5 D1 4A 4A 4A D0 D4 E6 1A D0 02 E6 1B A1 1A D0 CA 60 86 1A 84;
2660: 1B AA 4A 4A 4A 4A 85 D3 8A 29 0F AA BC BA F5 84 D0 49 0F AA BC BB F5 C8;
2678: 84 D2 A4 E5 A2 00 86 EA A1 1A 85 D1 A2 80 86 D4 86 D5 A6 E7 A5 D4 38 65;
2690: D0 85 D4 90 04 20 9C F4 18 A5 D5 65 D2 85 D5 90 03 20 9D F4 CA D0 E5 A5;
26A8: D1 4A 4A 4A D0 D4 E6 1A D0 02 E6 1B A1 1A D0 CA 60 20 67 DD 20 52 E7 A4;
26C0: 51 A6 50 C0 01 90 06 D0 1D E0 18 B0 19 8A 48 98 48 A9 2C 20 C0 DE 20 F8;
26D8: E6 E0 C0 B0 09 86 9D 68 A8 68 AA A5 9D 60 4C 06 F2 20 F8 E6 E0 08 B0 F6;
26F0: BD F6 F6 85 E4 60 00 2A 55 7F 80 AA D5 FF C9 C1 F0 0D 20 B9 F6 20 57 F4;
2708: 20 B7 00 C9 C1 D0 E6 20 C0 DE 20 B9 F6 84 9D A8 8A A6 9D 20 3A F5 4C 08;
2720: F7 20 F8 E6 86 F9 60 20 F8 E6 86 E7 60 20 F8 E6 A5 E8 85 1A A5 E9 85 1B;
2738: 8A A2 00 C1 1A F0 02 B0 A5 0A 90 03 E6 1B 18 A8 B1 1A 65 1A AA C8 B1 1A;
2750: 65 E9 85 1B 86 1A 20 B7 00 C9 C5 D0 09 20 C0 DE 20 B9 F6 20 11 F4 A5 F9;
2768: 60 20 2D F7 4C 05 F6 20 2D F7 4C 61 F6 A9 00 85 3D 85 3F A0 50 84 3C C8;
2780: 84 3E 20 FD FE 18 A5 73 AA CA 86 3E E5 50 48 A5 74 A8 E8 D0 01 88 84 3F;
2798: E5 51 C5 6E 90 02 D0 03 4C 10 D4 85 74 85 70 85 3D 85 E9 68 85 E8 85 73;
27B0: 85 6F 85 3C 20 FA FC A9 03 4C 02 FF 18 A5 9B 65 50 85 3E A5 9C 65 51 85;
27C8: 3F A0 04 B1 9B 20 EF E0 A5 94 85 3C A5 95 85 3D 60 A9 40 85 14 20 E3 DF;
27E0: A9 00 85 14 4C F0 D8 20 F8 E6 CA 8A C9 28 90 0A E9 28 48 20 FB DA 68 4C;
27F8: EC F7 85 24 60 CB D2 D7 4A 08 20 47 F8 28 A9 0F 90 02 69 E0 85 2E B1 26;
2810: 45 30 25 2E 51 26 91 26 60 20 00 F8 C4 2C B0 11 C8 20 0E F8 90 F6 69 01;
2828: 48 20 00 F8 68 C5 2D 90 F5 60 A0 2F D0 02 A0 27 84 2D A0 27 A9 00 85 30;
2840: 20 28 F8 88 10 F6 60 48 4A 29 03 09 04 85 27 68 29 18 90 02 69 7F 85 26;
2858: 0A 0A 05 26 85 26 60 A5 30 18 69 03 29 0F 85 30 0A 0A 0A 0A 05 30 85 30;
2870: 60 4A 08 20 47 F8 B1 26 28 90 04 4A 4A 4A 4A 29 0F 60 A6 3A A4 3B 20 96;
2888: FD 20 48 F9 A1 3A A8 4A 90 09 6A B0 10 C9 A2 F0 0C 29 87 4A AA BD 62 F9;
28A0: 20 79 F8 D0 04 A0 80 A9 00 AA BD A6 F9 85 2E 29 03 85 2F 98 29 8F AA 98;
28B8: A0 03 E0 8A F0 0B 4A 90 08 4A 4A 09 20 88 D0 FA C8 88 D0 F2 60 FF FF FF;
28D0: 20 82 F8 48 B1 3A 20 DA FD A2 01 20 4A F9 C4 2F C8 90 F1 A2 03 C0 04 90;
28E8: F2 68 A8 B9 C0 F9 85 2C B9 00 FA 85 2D A9 00 A0 05 06 2D 26 2C 2A 88 D0;
2900: F8 69 BF 20 ED FD CA D0 EC 20 48 F9 A4 2F A2 06 E0 03 F0 1C 06 2E 90 0E;
2918: BD B3 F9 20 ED FD BD B9 F9 F0 03 20 ED FD CA D0 E7 60 88 30 E7 20 DA FD;
2930: A5 2E C9 E8 B1 3A 90 F2 20 56 F9 AA E8 D0 01 C8 98 20 DA FD 8A 4C DA FD;
2948: A2 03 A9 A0 20 ED FD CA D0 F8 60 38 A5 2F A4 3B AA 10 01 88 65 3A 90 01;
2960: C8 60 04 20 54 30 0D 80 04 90 03 22 54 33 0D 80 04 90 04 20 54 33 0D 80;
2978: 04 90 04 20 54 3B 0D 80 04 90 00 22 44 33 0D C8 44 00 11 22 44 33 0D C8;
2990: 44 A9 01 22 44 33 0D 80 04 90 01 22 44 33 0D 80 04 90 26 31 87 9A 00 21;
29A8: 81 82 00 00 59 4D 91 92 86 4A 85 9D AC A9 AC A3 A8 A4 D9 00 D8 A4 A4 00;
29C0: 1C 8A 1C 23 5D 8B 1B A1 9D 8A 1D 23 9D 8B 1D A1 00 29 19 AE 69 A8 19 23;
29D8: 24 53 1B 23 24 53 19 A1 00 1A 5B 5B A5 69 24 24 AE AE A8 AD 29 00 7C 00;
29F0: 15 9C 6D 9C A5 69 29 53 84 13 34 11 A5 69 23 A0;
2A00: D8 62 5A 48 26 62 94 88 54 44 C8 54 68 44 E8 94 00 B4 08 84 74 B4 28 6E;
2A18: 74 F4 CC 4A 72 F2 A4 8A 00 AA A2 A2 74 74 74 72 44 68 B2 32 B2 00 22 00;
2A30: 1A 1A 26 26 72 72 88 C8 C4 CA 26 48 44 44 A2 C8 85 45 68 48 0A 0A 0A 30;
2A48: 03 6C FE 03 28 20 4C FF 68 85 3A 68 85 3B 6C F0 03 20 82 F8 20 DA FA 4C;
2A60: 65 FF D8 20 84 FE 20 2F FB 20 93 FE 20 89 FE AD 58 C0 AD 5A C0 AD 5D C0;
2A78: AD 5F C0 AD FF CF 2C 10 C0 D8 20 3A FF AD F3 03 49 A5 CD F4 03 D0 17 AD;
2A90: F2 03 D0 0F A9 E0 CD F3 03 D0 08 A0 03 8C F2 03 4C 00 E0 6C F2 03 20 60;
2AA8: FB A2 05 BD FC FA 9D EF 03 CA D0 F7 A9 C8 86 00 85 01 A0 07 C6 01 A5 01;
2AC0: C9 C0 F0 D7 8D F8 07 B1 00 D9 01 FB D0 EC 88 88 10 F5 6C 00 00 EA EA 20;
2AD8: 8E FD A9 45 85 40 A9 00 85 41 A2 FB A9 A0 20 ED FD BD 1E FA 20 ED FD A9;
2AF0: BD 20 ED FD B5 4A 20 DA FD E8 30 E8 60 59 FA 00 E0 45 20 FF 00 FF 03 FF;
2B08: 3C C1 D0 D0 CC C5 A0 DD DB C4 C2 C1 FF C3 FF FF FF C1 D8 D9 D0 D3 AD 70;
2B20: C0 A0 00 EA EA BD 64 C0 10 04 C8 D0 F8 88 60 A9 00 85 48 AD 56 C0 AD 54;
2B38: C0 AD 51 C0 A9 00 F0 0B AD 50 C0 AD 53 C0 20 36 F8 A9 14 85 22 A9 00 85;
2B50: 20 A9 28 85 21 A9 18 85 23 A9 17 85 25 4C 22 FC 20 58 FC A0 08 B9 08 FB;
2B68: 99 0E 04 88 D0 F7 60 AD F3 03 49 A5 8D F4 03 60 C9 8D D0 18 AC 00 C0 10;
2B80: 13 C0 93 D0 0F 2C 10 C0 AC 00 C0 10 FB C0 83 F0 03 2C 10 C0 4C FD FB 38;
2B98: 4C 2C FC A8 B9 48 FA 20 97 FB 20 0C FD C9 CE B0 EE C9 C9 90 EA C9 CC F0;
2BB0: E6 D0 E8 EA EA EA EA EA EA EA EA EA EA EA EA EA EA 48 4A 29 03 09 04 85;
2BC8: 29 68 29 18 90 02 69 7F 85 28 0A 0A 05 28 85 28 60 C9 87 D0 12 A9 40 20;
2BE0: A8 FC A0 C0 A9 0C 20 A8 FC AD 30 C0 88 D0 F5 60 A4 24 91 28 E6 24 A5 24;
2BF8: C5 21 B0 66 60 C9 A0 B0 EF A8 10 EC C9 8D F0 5A C9 8A F0 5A C9 88 D0 C9;
2C10: C6 24 10 E8 A5 21 85 24 C6 24 A5 22 C5 25 B0 0B C6 25 A5 25 20 C1 FB 65;
2C28: 20 85 28 60 49 C0 F0 28 69 FD 90 C0 F0 DA 69 FD 90 2C F0 DE 69 FD 90 5C;
2C40: D0 E9 A4 24 A5 25 48 20 24 FC 20 9E FC A0 00 68 69 00 C5 23 90 F0 B0 CA;
2C58: A5 22 85 25 A0 00 84 24 F0 E4 A9 00 85 24 E6 25 A5 25 C5 23 90 B6 C6 25;
2C70: A5 22 48 20 24 FC A5 28 85 2A A5 29 85 2B A4 21 88 68 69 01 C5 23 B0 0D;
2C88: 48 20 24 FC B1 28 91 2A 88 10 F9 30 E1 A0 00 20 9E FC B0 86 A4 24 A9 A0;
2CA0: 91 28 C8 C4 21 90 F9 60 38 48 E9 01 D0 FC 68 E9 01 D0 F6 60 E6 42 D0 02;
2CB8: E6 43 A5 3C C5 3E A5 3D E5 3F E6 3C D0 02 E6 3D 60 A0 4B 20 DB FC D0 F9;
2CD0: 69 FE B0 F5 A0 21 20 DB FC C8 C8 88 D0 FD 90 05 A0 32 88 D0 FD AC 20 C0;
2CE8: A0 2C CA 60 A2 08 48 20 FA FC 68 2A A0 3A CA D0 F5 60 20 FD FC 88 AD 60;
2D00: C0 45 2F 10 F8 45 2F 85 2F C0 80 60 A4 24 B1 28 48 29 3F 09 40 91 28 68;
2D18: 6C 38 00 E6 4E D0 02 E6 4F 2C 00 C0 10 F5 91 28 AD 00 C0 2C 10 C0 60 20;
2D30: 0C FD 20 A5 FB 20 0C FD C9 9B F0 F3 60 A5 32 48 A9 FF 85 32 BD 00 02 20;
2D48: ED FD 68 85 32 BD 00 02 C9 88 F0 1D C9 98 F0 0A E0 F8 90 03 20 3A FF E8;
2D60: D0 13 A9 DC 20 ED FD 20 8E FD A5 33 20 ED FD A2 01 8A F0 F3 CA 20 35 FD;
2D78: C9 95 D0 02 B1 28 C9 E0 90 02 29 DF 9D 00 02 C9 8D D0 B2 20 9C FC A9 8D;
2D90: D0 5B A4 3D A6 3C 20 8E FD 20 40 F9 A0 00 A9 AD 4C ED FD A5 3C 09 07 85;
2DA8: 3E A5 3D 85 3F A5 3C 29 07 D0 03 20 92 FD A9 A0 20 ED FD B1 3C 20 DA FD;
2DC0: 20 BA FC 90 E8 60 4A 90 EA 4A 4A A5 3E 90 02 49 FF 65 3C 48 A9 BD 20 ED;
2DD8: FD 68 48 4A 4A 4A 4A 20 E5 FD 68 29 0F 09 B0 C9 BA 90 02 69 06 6C 36 00;
2DF0: C9 A0 90 02 25 32 84 35 48 20 78 FB 68 A4 35 60 C6 34 F0 9F CA D0 16 C9;
2E08: BA D0 BB 85 31 A5 3E 91 40 E6 40 D0 02 E6 41 60 A4 34 B9 FF 01 85 31 60;
2E20: A2 01 B5 3E 95 42 95 44 CA 10 F7 60 B1 3C 91 42 20 B4 FC 90 F7 60 B1 3C;
2E38: D1 42 F0 1C 20 92 FD B1 3C 20 DA FD A9 A0 20 ED FD A9 A8 20 ED FD B1 42;
2E50: 20 DA FD A9 A9 20 ED FD 20 B4 FC 90 D9 60 20 75 FE A9 14 48 20 D0 F8 20;
2E68: 53 F9 85 3A 84 3B 68 38 E9 01 D0 EF 60 8A F0 07 B5 3C 95 3A CA 10 F9 60;
2E80: A0 3F D0 02 A0 FF 84 32 60 A9 00 85 3E A2 38 A0 1B D0 08 A9 00 85 3E A2;
2E98: 36 A0 F0 A5 3E 29 0F F0 06 09 C0 A0 00 F0 02 A9 FD 94 00 95 01 60 EA EA;
2EB0: 4C 00 E0 4C 03 E0 20 75 FE 20 3F FF 6C 3A 00 4C D7 FA 60 EA 60 EA EA EA;
2EC8: EA EA 4C F8 03 A9 40 20 C9 FC A0 27 A2 00 41 3C 48 A1 3C 20 ED FE 20 BA;
2EE0: FC A0 1D 68 90 EE A0 22 20 ED FE F0 4D A2 10 0A 20 D6 FC D0 FA 60 20 00;
2EF8: FE 68 68 D0 6C 20 FA FC A9 16 20 C9 FC 85 2E 20 FA FC A0 24 20 FD FC B0;
2F10: F9 20 FD FC A0 3B 20 EC FC 81 3C 45 2E 85 2E 20 BA FC A0 35 90 F0 20 EC;
2F28: FC C5 2E F0 0D A9 C5 20 ED FD A9 D2 20 ED FD 20 ED FD A9 87 4C ED FD A5;
2F40: 48 48 A5 45 A6 46 A4 47 28 60 85 45 86 46 84 47 08 68 85 48 BA 86 49 D8;
2F58: 60 20 84 FE 20 2F FB 20 93 FE 20 89 FE D8 20 3A FF A9 AA 85 33 20 67 FD;
2F70: 20 C7 FF 20 A7 FF 84 34 A0 17 88 30 E8 D9 CC FF D0 F8 20 BE FF A4 34 4C;
2F88: 73 FF A2 03 0A 0A 0A 0A 0A 26 3E 26 3F CA 10 F8 A5 31 D0 06 B5 3F 95 3D;
2FA0: 95 41 E8 F0 F3 D0 06 A2 00 86 3E 86 3F B9 00 02 C8 49 B0 C9 0A 90 D3 69;
2FB8: 88 C9 FA B0 CD 60 A9 FE 48 B9 E3 FF 48 A5 31 A0 00 84 31 60 BC B2 BE B2;
2FD0: EF C4 B2 A9 BB A6 A4 06 95 07 02 05 F0 00 EB 93 A7 C6 99 B2 C9 BE C1 35;
2FE8: 8C C4 96 AF 17 17 2B 1F 83 7F 5D CC B5 FC 17 17 F5 03 FB 03 62 FA 40 FA;
END;

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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: roms.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY roms IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END roms;
ARCHITECTURE SYN OF roms IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../roms.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 14,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../roms.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../roms.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL roms_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 49152,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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//
// ddram.v
//
// DE10-nano DDR3 memory interface
//
// Copyright (c) 2017 Sorgelig
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
// 8-bit version
module ddram
(
input reset,
input DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
input [27:0] addr, // 256MB at the end of 1GB
output [7:0] dout, // data output to cpu
input [7:0] din, // data input from cpu
input we, // cpu requests write
input rd, // cpu requests read
output ready // dout is valid. Ready to accept new read/write.
);
assign DDRAM_BURSTCNT = 1;
assign DDRAM_BE = (8'd1<<ram_address[2:0]) | {8{ram_read}};
assign DDRAM_ADDR = {4'b0011, ram_address[27:3]}; // RAM at 0x30000000
assign DDRAM_RD = ram_read;
assign DDRAM_DIN = ram_cache;
assign DDRAM_WE = ram_write;
assign dout = ram_q;
assign ready = ~busy;
reg [7:0] ram_q;
reg [27:0] ram_address;
reg ram_read;
reg [63:0] ram_cache;
reg ram_write;
reg [7:0] cached;
reg busy;
always @(posedge DDRAM_CLK)
begin
reg old_rd, old_we;
reg old_reset;
reg state;
old_reset <= reset;
if(old_reset && ~reset)
begin
busy <= 0;
state <= 0;
cached <= 0;
end
if(!DDRAM_BUSY)
begin
ram_write <= 0;
ram_read <= 0;
if(state)
begin
if(DDRAM_DOUT_READY)
begin
ram_q <= DDRAM_DOUT[{ram_address[2:0], 3'b000} +:8];
ram_cache <= DDRAM_DOUT;
cached <= 8'hFF;
state <= 0;
busy <= 0;
end
end
else
begin
old_rd <= rd;
old_we <= we;
busy <= 0;
if(~old_we && we)
begin
ram_cache[{addr[2:0], 3'b000} +:8] <= din;
ram_address <= addr;
busy <= 1;
ram_write <= 1;
cached <= ((ram_address[27:3] == addr[27:3]) ? cached : 8'h00) | (8'd1<<addr[2:0]);
end
if(~old_rd && rd)
begin
busy <= 1;
if((ram_address[27:3] == addr[27:3]) && (cached & (8'd1<<addr[2:0])))
begin
ram_q <= ram_cache[{addr[2:0], 3'b000} +:8];
end
else
begin
ram_address <= addr;
ram_read <= 1;
state <= 1;
cached <= 0;
end
end
end
end
end
endmodule

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module hdmi_config
(
// Host Side
input iCLK,
input iRST_N,
// 0 - 480i
// 1 - 480p
// 2 - 576i
// 3 - 576p
// 4 - 720p
// 5-7 - reserved
input [2:0] iRES,
// 0 - 4:3
// 1 - 16:9
input iAR,
input audio_48k,
// I2C Side
output I2C_SCL,
inout I2C_SDA
);
// Internal Registers/Wires
reg mI2C_GO = 0;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [7:0] LUT_INDEX = 0;
I2C_Controller #(50_000_000, 400_000) i2c_av
(
.CLK(iCLK),
.I2C_SCL(I2C_SCL), // I2C CLOCK
.I2C_SDA(I2C_SDA), // I2C DATA
.I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
.START(mI2C_GO), // START transfer
.END(mI2C_END), // END transfer
.ACK(mI2C_ACK) // ACK
);
////////////////////// Config Control ////////////////////////////
always@(posedge iCLK or negedge iRST_N) begin
reg [1:0] mSetup_ST = 0;
if(!iRST_N) begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end else begin
if(init_data[LUT_INDEX] != 16'hFFFF) begin
case(mSetup_ST)
0: begin
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: if(~mI2C_END) mSetup_ST <= 2;
2: begin
mI2C_GO <= 0;
if(mI2C_END) begin
mSetup_ST <= 0;
if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
end
end
endcase
end
end
end
wire [15:0] res480i[6] = '{'h35_1D, 'h36_92, 'h37_05, 'h38_A0, 'h39_0F, 'h3A_00};
wire [15:0] res480p[6] = '{'h35_1F, 'h36_E8, 'h37_05, 'h38_A0, 'h39_1E, 'h3A_00};
wire [15:0] res576i[6] = '{'h35_20, 'h36_D6, 'h37_05, 'h38_A0, 'h39_12, 'h3A_00};
wire [15:0] res576p[6] = '{'h35_20, 'h36_EC, 'h37_05, 'h38_A0, 'h39_24, 'h3A_00};
wire [15:0] res720p[6] = '{'h35_40, 'h36_D9, 'h37_0A, 'h38_00, 'h39_2D, 'h3A_00};
reg [15:0] resVar[6];
always_comb begin
case(iRES)
0: resVar <= res480i;
1: resVar <= res480p;
2: resVar <= res576i;
3: resVar <= res576p;
4: resVar <= res720p;
default: resVar <= res720p;
endcase
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
wire [15:0] init_data[58] =
'{
16'h4110, // Power Down control
16'h9803, // ADI required Write.
16'h9A70, // ADI required Write.
16'h9C30, // ADI required Write.
{8'h9D, 8'b0110_0001}, // [7:4] must be b0110!.
// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
// [1:0] must be b01!
16'hA2A4, // ADI required Write.
16'hA3A4, // ADI required Write.
16'hE0D0, // ADI required Write.
resVar[0],
resVar[1],
resVar[2],
resVar[3],
resVar[4],
resVar[5],
{8'h16, 8'b0011_1000}, // Output Format 444 [7]=0.
// [6] must be 0!
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
// DDR Input Edge falling [1]=0 (not using DDR atm).
// Output Colour Space RGB [0]=0.
// {8'h16, 8'b1011_0101}, // Output Format 422 [7]=1.
// [6] must be 0!
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
// Input Style [3:2] b01 = Style 2.
// DDR Input Edge falling [1]=0 (not using DDR atm).
// Output Colour Space YPrPb [0]=1.
// {8'h17, 8'b0110_0000}, // Aspect ratio 4:3 [1]=0. DE Generation DISabled [0]=0.
// Vsync polarity HIGH [6]=0, LOW [6]=1.
// Hsync polarity HIGH [5]=0, LOW [5]=1.
// {8'h17, 8'b0110_0001}, // Aspect ratio 4:3 [1]=0. DE Generation ENabled [0]=1.
// {8'h17, 8'b0110_0011}, // Aspect ratio 16:9 [1]=1. DE Generation ENabled [0]=1.
{8'h17, 6'b011000, iAR, 1'b0}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
{8'h18, 8'b0100_0110}, // CSC disabled [7]=0.
// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
// CSC Equation 3 [4:0] b00110.
// {8'h3B, 8'b0000_1010}, // Pixel repetition [6:5] b00 AUTO. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
// {8'h3B, 8'b0110_1010}, // Pixel repetition [6:5] b11 MANUAL. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
// {8'h3C, 8'b0000_0110}, // VIC#6 480i-60, 2x clk, 4:3.
// {8'h3C, 8'b0000_0001}, // VIC#1 VGA (640x480), 2x clk, 4:3.
// {8'h3C, 8'b0000_0010}, // VIC#2 480p (720x480), 2x clk, 4:3.
16'h4000, // General Control Packet Enable
{8'h48, 8'b0000_1000}, // [6]=0 Normal bus order!
// [5] DDR Alignment.
// [4:3] b01 Data right justified (for YCbCr 422 input modes).
16'h49A8, // ADI required Write.
16'h4C00, // ADI required Write.
{8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
// {8'h55, 8'b0101_0000}, // [7] must be 0!. Set YCbCr 444 in AVinfo Frame [6:5], Set active format [4].
// {8'h55, 8'b0011_0001}, // [7] must be 0!. Set YCbCr 422 in AVinfo Frame [6:5].
// AVI InfoFrame Valid [4].
// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
// {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
16'h7301,
16'h9400, // HPD Interrupt disabled.
16'h9902, // ADI required Write.
16'h9B18, // ADI required Write.
16'h9F00, // ADI required Write.
{8'hA1, 8'b0100_0000}, // [6]=1 Monitor Sense Power Down DISabled.
16'hA408, // ADI required Write.
16'hA504, // ADI required Write.
16'hA600, // ADI required Write.
16'hA700, // ADI required Write.
16'hA800, // ADI required Write.
16'hA900, // ADI required Write.
16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write.
{8'hAF, 8'b0001_0110}, // [7]=0 HDCP Disabled.
// [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [3:2] must be b01!
// [1]=1 HDMI Mode.
// [0] must be b0!
16'hB900, // ADI required Write.
{8'hBA, 8'b0110_0000}, // [7:5] Input Clock delay...
// b000 = -1.2ns.
// b001 = -0.8ns.
// b010 = -0.4ns.
// b011 = No delay.
// b100 = 0.4ns.
// b101 = 0.8ns.
// b110 = 1.2ns.
// b111 = 1.6ns.
16'hBB00, // ADI required Write.
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
// 00 = HPD is from both HPD pin or CDC HPD
// 01 = HPD is from CDC HPD
// 10 = HPD is from HPD pin
// 11 = HPD is always high
16'hDE9C, // ADI required Write.
16'hE460, // ADI required Write.
16'hFA7D, // Nbr of times to search for good phase
// (Audio stuff on Programming Guide, Page 66)...
{8'h0A, 8'b0000_0000}, // [6:4] Audio Select. b000 = I2S.
// [3:2] Audio Mode. (HBR stuff, leave at 00!).
{8'h0B, 8'b0000_1110}, //
{8'h0C, 8'b0000_0100}, // [7] 0 = Use sampling rate from I2S stream. 1 = Use samp rate from I2C Register.
// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
// [2] 1 = I2S0 Enable.
// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
{8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified.
{8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits.
{8'h15, ~audio_48k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
// {8'h15, 8'b0010_0001}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:0] b0001 (1) = 16, 20, 24 bit YCbCr 4:2:2 with Separate Syncs.
// {8'h15, 8'b0010_0011}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
// Input ID [3:0] b0011 (3) = 16, 20, 24 bit YCbCr 4:2:2 (2x Pixel Clock, with Separate Syncs).
// Audio Clock Config
16'h0100, //
audio_48k ? 16'h0218 : 16'h0230, // Set N Value 12288/6144
16'h0300, //
16'h0701, //
16'h0822, // Set CTS Value 74250
16'h090A, //
16'hFFFF // END
};
////////////////////////////////////////////////////////////////////
endmodule

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//
// hps_io.v
//
// mist_io-like module for the Terasic DE10 board
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig (port to DE10-nano)
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = CLK_SYS/(PS2DIV*2)
//
// WIDE=1 for 16 bit file I/O
// VDNUM 1-4
module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
(
input clk_sys,
inout [43:0] HPS_BUS,
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
output reg [15:0] joystick_0,
output reg [15:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output forced_scandoubler,
output reg [31:0] status,
// SD config
output reg [VD:0] img_mounted, // signaling that new image has been mounted
output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted
output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted
// SD block level access
input [31:0] sd_lba,
input [VD:0] sd_rd, // only single sd_rd can be active at any given time
input [VD:0] sd_wr, // only single sd_wr can be active at any given time
output reg sd_ack,
// do not use in new projects.
// CID and CSD are fake except CSD image size field.
input sd_conf,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [AW:0] sd_buff_addr,
output reg [DW:0] sd_buff_dout,
input [DW:0] sd_buff_din,
output reg sd_buff_wr,
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr,
output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2
output reg [DW:0] ioctl_dout,
input ioctl_wait,
// RTC MSM6242B layout
output reg [64:0] RTC,
// Seconds since 1970-01-01 00:00:00
output reg [32:0] TIMESTAMP,
// ps2 keyboard emulation
output ps2_kbd_clk_out,
output ps2_kbd_data_out,
input ps2_kbd_clk_in,
input ps2_kbd_data_in,
input [2:0] ps2_kbd_led_status,
input [2:0] ps2_kbd_led_use,
output ps2_mouse_clk_out,
output ps2_mouse_data_out,
input ps2_mouse_clk_in,
input ps2_mouse_data_in,
// ps2 alternative interface.
output reg [65:0] ps2_key = 0, // up to 8 bytes per key (pause)
output reg [24:0] ps2_mouse = 0
);
localparam DW = (WIDE) ? 15 : 7;
localparam AW = (WIDE) ? 7 : 8;
localparam VD = VDNUM-1;
wire io_wait = ioctl_wait;
wire io_enable= |HPS_BUS[35:34];
wire io_strobe= HPS_BUS[33];
wire io_wide = (WIDE) ? 1'b1 : 1'b0;
wire [15:0] io_din = HPS_BUS[31:16];
reg [15:0] io_dout;
assign HPS_BUS[37] = io_wait;
assign HPS_BUS[36] = clk_sys;
assign HPS_BUS[32] = io_wide;
assign HPS_BUS[15:0] = io_dout;
reg [7:0] cfg;
assign buttons = cfg[1:0];
//cfg[2] - vga_scaler handled in sys_top
//cfg[3] - csync handled in sys_top
assign forced_scandoubler = cfg[4];
//cfg[5] - ypbpr handled in sys_top
// command byte read by the io controller
wire [15:0] sd_cmd =
{
2'b00,
(VDNUM>=4) ? sd_wr[3] : 1'b0,
(VDNUM>=3) ? sd_wr[2] : 1'b0,
(VDNUM>=2) ? sd_wr[1] : 1'b0,
(VDNUM>=4) ? sd_rd[3] : 1'b0,
(VDNUM>=3) ? sd_rd[2] : 1'b0,
(VDNUM>=2) ? sd_rd[1] : 1'b0,
4'h5, sd_conf, 1'b1,
sd_wr[0],
sd_rd[0]
};
///////////////// calc video parameters //////////////////
wire clk_100 = HPS_BUS[43];
wire clk_vid = HPS_BUS[42];
wire ce_pix = HPS_BUS[41];
wire de = HPS_BUS[40];
wire hs = HPS_BUS[39];
wire vs = HPS_BUS[38];
reg [31:0] vid_hcnt = 0;
reg [31:0] vid_vcnt = 0;
reg [7:0] vid_nres = 0;
integer hcnt;
always @(posedge clk_vid) begin
integer vcnt;
reg old_vs= 0, old_de = 0;
reg calch = 0;
if(ce_pix) begin
old_vs <= vs;
old_de <= de;
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
if(calch & de) hcnt <= hcnt + 1;
if(old_de & ~de) calch <= 0;
if(old_vs & ~vs) begin
if(hcnt && vcnt) begin
if(vid_hcnt != hcnt || vid_vcnt != vcnt) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
end
vcnt <= 0;
hcnt <= 0;
calch <= 1;
end
end
end
reg [31:0] vid_htime = 0;
reg [31:0] vid_vtime = 0;
reg [31:0] vid_pix = 0;
always @(posedge clk_100) begin
integer vtime, htime, hcnt;
reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
reg calch = 0;
old_vs <= vs;
old_hs <= hs;
old_vs2 <= old_vs;
old_hs2 <= old_hs;
vtime <= vtime + 1'd1;
htime <= htime + 1'd1;
if(~old_vs2 & old_vs) begin
vid_pix <= hcnt;
vid_vtime <= vtime;
vtime <= 0;
hcnt <= 0;
end
if(old_vs2 & ~old_vs) calch <= 1;
if(~old_hs2 & old_hs) begin
vid_htime <= htime;
htime <= 0;
end
old_de <= de;
old_de2 <= old_de;
if(calch & old_de) hcnt <= hcnt + 1;
if(old_de2 & ~old_de) calch <= 0;
end
/////////////////////////////////////////////////////////
always@(posedge clk_sys) begin
reg [15:0] cmd;
reg [9:0] byte_cnt; // counts bytes
reg [2:0] b_wr;
reg [2:0] stick_idx;
reg ps2skip = 0;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
ps2_key[65] <= kbd_txempty;
if(~io_enable) begin
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5 && !ps2skip) ps2_key[64] <= ~ps2_key[64];
if(cmd == 'h22) RTC[64] <= ~RTC[64];
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
cmd <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
io_dout <= 0;
ps2skip <= 0;
end else begin
if(io_strobe) begin
io_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
if(byte_cnt == 0) begin
cmd <= io_din;
case(io_din)
'h19: sd_ack_conf <= 1;
'h17,
'h18: sd_ack <= 1;
endcase
sd_buff_addr <= 0;
img_mounted <= 0;
if(io_din == 5) ps2_key[63:0] <= 0;
end else begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din[7:0];
'h02: joystick_0 <= io_din;
'h03: joystick_1 <= io_din;
// store incoming ps2 mouse bytes
'h04: begin
mouse_data <= io_din[7:0];
mouse_we <= 1;
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) begin
case(byte_cnt)
1: ps2_mouse[7:0] <= io_din[7:0];
2: ps2_mouse[15:8] <= io_din[7:0];
3: ps2_mouse[23:16] <= io_din[7:0];
endcase
end
end
// store incoming ps2 keyboard bytes
'h05: begin
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) ps2_key[63:0] <= {ps2_key[55:0], io_din[7:0]};
kbd_data <= io_din[7:0];
kbd_we <= 1;
end
// reading config string
'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
end
// reading sd card status
'h16: begin
case(byte_cnt)
1: io_dout <= sd_cmd;
2: io_dout <= sd_lba[15:0];
3: io_dout <= sd_lba[31:16];
endcase
end
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
'h19,
// send sector IO -> FPGA
// flag that download begins
'h17: begin
sd_buff_dout <= io_din[DW:0];
b_wr <= 1;
end
// reading sd card write data
'h18: begin
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
io_dout <= sd_buff_din;
end
// joystick analog
'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= io_din[2:0];
if(byte_cnt == 2) begin
if(stick_idx == 0) joystick_analog_0 <= io_din;
if(stick_idx == 1) joystick_analog_1 <= io_din;
end
end
// notify image selection
'h1c: begin
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
img_readonly <= io_din[7];
end
// send image info
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
// status, 32bit version
'h1e: if(byte_cnt==1) status[15:0] <= io_din;
else if(byte_cnt==2) status[31:16] <= io_din;
// reading keyboard LED status
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
// reading ps2 keyboard/mouse control
'h21: begin
if(byte_cnt == 1) begin
io_dout <= kbd_data_host;
kbd_rd <= 1;
end
if(byte_cnt == 2) begin
io_dout <= mouse_data_host;
mouse_rd <= 1;
end
end
//RTC
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//Video res.
'h23: begin
case(byte_cnt)
1: io_dout <= vid_nres;
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
5: io_dout <= vid_vcnt[31:16];
6: io_dout <= vid_htime[15:0];
7: io_dout <= vid_htime[31:16];
8: io_dout <= vid_vtime[15:0];
9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16];
endcase
end
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
endcase
end
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
reg [7:0] kbd_data;
reg kbd_we;
wire [8:0] kbd_data_host;
reg kbd_rd;
wire kbd_txempty;
ps2_device keyboard
(
.clk_sys(clk_sys),
.wdata(kbd_data),
.we(kbd_we),
.ps2_clk(clk_ps2),
.ps2_clk_out(ps2_kbd_clk_out),
.ps2_dat_out(ps2_kbd_data_out),
.tx_empty(kbd_txempty),
.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
.rdata(kbd_data_host),
.rd(kbd_rd)
);
reg [7:0] mouse_data;
reg mouse_we;
wire [8:0] mouse_data_host;
reg mouse_rd;
ps2_device mouse
(
.clk_sys(clk_sys),
.wdata(mouse_data),
.we(mouse_we),
.ps2_clk(clk_ps2),
.ps2_clk_out(ps2_mouse_clk_out),
.ps2_dat_out(ps2_mouse_data_out),
.ps2_clk_in(ps2_mouse_clk_in || !PS2WE),
.ps2_dat_in(ps2_mouse_data_in || !PS2WE),
.rdata(mouse_data_host),
.rd(mouse_rd)
);
/////////////////////////////// DOWNLOADING ///////////////////////////////
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
always@(posedge clk_sys) begin
reg [15:0] cmd;
reg has_cmd;
reg [24:0] addr;
reg wr;
ioctl_wr <= wr;
wr <= 0;
if(~io_enable) has_cmd <= 0;
else begin
if(io_strobe) begin
if(!has_cmd) begin
cmd <= io_din;
has_cmd <= 1;
end else begin
case(cmd)
UIO_FILE_INDEX:
begin
ioctl_index <= io_din[7:0];
end
UIO_FILE_TX:
begin
if(io_din[7:0]) begin
addr <= 0;
ioctl_download <= 1;
end else begin
ioctl_addr <= addr;
ioctl_download <= 0;
end
end
UIO_FILE_TX_DAT:
begin
ioctl_addr <= addr;
ioctl_dout <= io_din[DW:0];
wr <= 1;
addr <= addr + (WIDE ? 2'd2 : 2'd1);
end
endcase
end
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
module ps2_device #(parameter PS2_FIFO_BITS=5)
(
input clk_sys,
input [7:0] wdata,
input we,
input ps2_clk,
output reg ps2_clk_out,
output reg ps2_dat_out,
output reg tx_empty,
input ps2_clk_in,
input ps2_dat_in,
output [8:0] rdata,
input rd
);
(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] wptr;
reg [PS2_FIFO_BITS-1:0] rptr;
reg [2:0] rx_state = 0;
reg [3:0] tx_state = 0;
reg has_data;
reg [7:0] data;
assign rdata = {has_data, data};
always@(posedge clk_sys) begin
reg [7:0] tx_byte;
reg parity;
reg r_inc;
reg old_clk;
reg [1:0] timeout;
reg [3:0] rx_cnt;
reg c1,c2,d1;
tx_empty <= ((wptr == rptr) && (tx_state == 0));
if(we) begin
fifo[wptr] <= wdata;
wptr <= wptr + 1'd1;
end
if(rd) has_data <= 0;
c1 <= ps2_clk_in;
c2 <= c1;
d1 <= ps2_dat_in;
if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
rx_state <= rx_state + 1'b1;
ps2_dat_out <= 1;
end
old_clk <= ps2_clk;
if(~old_clk & ps2_clk) begin
if(rx_state) begin
case(rx_state)
1: begin
rx_state <= rx_state + 1'b1;
rx_cnt <= 0;
end
2: begin
if(rx_cnt <= 7) data <= {d1, data[7:1]};
else rx_state <= rx_state + 1'b1;
rx_cnt <= rx_cnt + 1'b1;
end
3: if(d1) begin
rx_state <= rx_state + 1'b1;
ps2_dat_out <= 0;
end
4: begin
ps2_dat_out <= 1;
has_data <= 1;
rx_state <= 0;
end
endcase
end else begin
// transmitter is idle?
if(tx_state == 0) begin
// data in fifo present?
if(c2 && c1 && d1 && wptr != rptr) begin
timeout <= timeout - 1'd1;
if(!timeout) begin
tx_byte <= fifo[rptr];
rptr <= rptr + 1'd1;
// reset parity
parity <= 1;
// start transmitter
tx_state <= 1;
// put start bit on data line
ps2_dat_out <= 0; // start bit is 0
end
end
end else begin
// transmission of 8 data bits
if((tx_state >= 1)&&(tx_state < 9)) begin
ps2_dat_out <= tx_byte[0]; // data bits
tx_byte[6:0] <= tx_byte[7:1]; // shift down
if(tx_byte[0])
parity <= !parity;
end
// transmission of parity
if(tx_state == 9) ps2_dat_out <= parity;
// transmission of stop bit
if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1
// advance state machine
if(tx_state < 11) tx_state <= tx_state + 1'd1;
else tx_state <= 0;
end
end
end
if(~old_clk & ps2_clk) ps2_clk_out <= 1;
if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
end
endmodule

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//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <= 1024 ? 9 : \
N <= 2048 ?10 : 11 )
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
wire curbuf = y[0];
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [23:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [23:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [23:0] h2rgb;
input [11:0] v;
begin
h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
end
endfunction
function [11:0] rgb2h;
input [23:0] v;
begin
rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
(
.clk(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
offs <= offs + 1'd1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
prevbuf <= curbuf;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output logic [DWIDTH:0] q
);
logic [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
q <= ram[rdaddress];
end
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [23:0] rgb1,
input [23:0] rgb2,
output result
);
wire [7:0] r = rgb1[7:1] - rgb2[7:1];
wire [7:0] g = rgb1[15:9] - rgb2[15:9];
wire [7:0] b = rgb1[23:17] - rgb2[23:17];
wire [8:0] t = $signed(r) + $signed(b);
wire [8:0] gx = {g[7], g};
wire [9:0] y = $signed(t) + $signed(gx);
wire [8:0] u = $signed(r) - $signed(b);
wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-96..96)
wire y_inside = (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
wire u_inside = (u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
wire v_inside = (v < 10'h18 || v >= 10'h3e8);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [10:0] Amul = mul8x3(A, Op[7:5]);
wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
wire [10:0] At = Amul;
wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [11:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[11:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
input [23:0] D,
input [23:0] F,
input [23:0] H,
output [23:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [23:0] Input1 = E;
wire [23:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [23:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]);
InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]);
InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
endmodule

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module I2C_Controller
(
input CLK,
input START,
input [23:0] I2C_DATA,
output reg END = 1,
output reg ACK = 0,
//I2C bus
output I2C_SCL,
inout I2C_SDA
);
// Clock Setting
parameter CLK_Freq = 50_000_000; // 50 MHz
parameter I2C_Freq = 400_000; // 400 KHz
reg I2C_CLOCK;
always@(negedge CLK) begin
integer mI2C_CLK_DIV = 0;
if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin
mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
end else begin
mI2C_CLK_DIV <= 0;
I2C_CLOCK <= ~I2C_CLOCK;
end
end
assign I2C_SCL = SCLK | I2C_CLOCK;
assign I2C_SDA = SDO ? 1'bz : 1'b0;
reg SCLK = 1, SDO = 1;
always @(posedge CLK) begin
reg old_clk;
reg old_st;
reg [5:0] SD_COUNTER = 'b111111;
reg [0:31] SD;
old_clk <= I2C_CLOCK;
old_st <= START;
if(~old_st && START) begin
SCLK <= 1;
SDO <= 1;
ACK <= 0;
END <= 0;
SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011};
SD_COUNTER <= 0;
end else begin
if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
SD_COUNTER <= SD_COUNTER + 6'd1;
case(SD_COUNTER)
01: SCLK <= 0;
10,19,28: ACK <= ACK | I2C_SDA;
29: SCLK <= 1;
32: END <= 1;
endcase
end
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]];
end
end
endmodule

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module i2s
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_DW = 16,
parameter AUDIO_RATE = 96000
)
(
input reset,
input clk_sys,
input half_rate,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
always @(posedge clk_sys) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg [7:0] bit_cnt;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
reg msclk;
reg ce;
if (reset) begin
count_q <= 0;
error_q <= 0;
ce <= 0;
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
sclk <= msclk;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) begin
msclk <= ~msclk;
if(msclk) begin
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= left_chan;
right <= right_chan;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
end
endmodule

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// avalon_combiner.v
`timescale 1 ps / 1 ps
module avalon_combiner
(
input wire clk, // clock.clk
input wire rst, // reset.reset
output wire [6:0] mixer_address, // ctl_mixer.address
output wire [3:0] mixer_byteenable, // .byteenable
output wire mixer_write, // .write
output wire [31:0] mixer_writedata, // .writedata
input wire mixer_waitrequest, // .waitrequest
output wire [6:0] scaler_address, // ctl_scaler.address
output wire [3:0] scaler_byteenable, // .byteenable
input wire scaler_waitrequest, // .waitrequest
output wire scaler_write, // .write
output wire [31:0] scaler_writedata, // .writedata
output wire [7:0] video_address, // ctl_video.address
output wire [3:0] video_byteenable, // .byteenable
input wire video_waitrequest, // .waitrequest
output wire video_write, // .write
output wire [31:0] video_writedata, // .writedata
output wire clock, // control.clock
output wire reset, // .reset
input wire [8:0] address, // .address
input wire write, // .write
input wire [31:0] writedata, // .writedata
output wire waitrequest // .waitrequest
);
assign clock = clk;
assign reset = rst;
assign mixer_address = address[6:0];
assign scaler_address = address[6:0];
assign video_address = address[7:0];
assign mixer_byteenable = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable = 4'b1111;
wire en_scaler = (address[8:7] == 0);
wire en_mixer = (address[8:7] == 1);
wire en_video = address[8];
assign mixer_write = en_mixer & write;
assign scaler_write = en_scaler & write;
assign video_write = en_video & write;
assign mixer_writedata = writedata;
assign scaler_writedata = writedata;
assign video_writedata = writedata;
assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
endmodule

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# TCL File Generated by Component Editor 16.1
# Sat Mar 25 22:55:53 CST 2017
# DO NOT MODIFY
#
# avalon_combiner "avalon_combiner" v1.0
# 2017.03.25.22:55:53
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module avalon_combiner
#
set_module_property DESCRIPTION ""
set_module_property NAME avalon_combiner
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR sorgelig
set_module_property DISPLAY_NAME avalon_combiner
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset rst reset Input 1
#
# connection point ctl_mixer
#
add_interface ctl_mixer avalon start
set_interface_property ctl_mixer addressUnits WORDS
set_interface_property ctl_mixer associatedClock clock
set_interface_property ctl_mixer associatedReset reset
set_interface_property ctl_mixer bitsPerSymbol 8
set_interface_property ctl_mixer burstOnBurstBoundariesOnly false
set_interface_property ctl_mixer burstcountUnits WORDS
set_interface_property ctl_mixer doStreamReads false
set_interface_property ctl_mixer doStreamWrites false
set_interface_property ctl_mixer holdTime 0
set_interface_property ctl_mixer linewrapBursts false
set_interface_property ctl_mixer maximumPendingReadTransactions 0
set_interface_property ctl_mixer maximumPendingWriteTransactions 0
set_interface_property ctl_mixer readLatency 0
set_interface_property ctl_mixer readWaitTime 1
set_interface_property ctl_mixer setupTime 0
set_interface_property ctl_mixer timingUnits Cycles
set_interface_property ctl_mixer writeWaitTime 0
set_interface_property ctl_mixer ENABLED true
set_interface_property ctl_mixer EXPORT_OF ""
set_interface_property ctl_mixer PORT_NAME_MAP ""
set_interface_property ctl_mixer CMSIS_SVD_VARIABLES ""
set_interface_property ctl_mixer SVD_ADDRESS_GROUP ""
add_interface_port ctl_mixer mixer_address address Output 7
add_interface_port ctl_mixer mixer_byteenable byteenable Output 4
add_interface_port ctl_mixer mixer_write write Output 1
add_interface_port ctl_mixer mixer_writedata writedata Output 32
add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1
#
# connection point ctl_scaler
#
add_interface ctl_scaler avalon start
set_interface_property ctl_scaler addressUnits WORDS
set_interface_property ctl_scaler associatedClock clock
set_interface_property ctl_scaler associatedReset reset
set_interface_property ctl_scaler bitsPerSymbol 8
set_interface_property ctl_scaler burstOnBurstBoundariesOnly false
set_interface_property ctl_scaler burstcountUnits WORDS
set_interface_property ctl_scaler doStreamReads false
set_interface_property ctl_scaler doStreamWrites false
set_interface_property ctl_scaler holdTime 0
set_interface_property ctl_scaler linewrapBursts false
set_interface_property ctl_scaler maximumPendingReadTransactions 0
set_interface_property ctl_scaler maximumPendingWriteTransactions 0
set_interface_property ctl_scaler readLatency 0
set_interface_property ctl_scaler readWaitTime 1
set_interface_property ctl_scaler setupTime 0
set_interface_property ctl_scaler timingUnits Cycles
set_interface_property ctl_scaler writeWaitTime 0
set_interface_property ctl_scaler ENABLED true
set_interface_property ctl_scaler EXPORT_OF ""
set_interface_property ctl_scaler PORT_NAME_MAP ""
set_interface_property ctl_scaler CMSIS_SVD_VARIABLES ""
set_interface_property ctl_scaler SVD_ADDRESS_GROUP ""
add_interface_port ctl_scaler scaler_address address Output 7
add_interface_port ctl_scaler scaler_byteenable byteenable Output 4
add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1
add_interface_port ctl_scaler scaler_write write Output 1
add_interface_port ctl_scaler scaler_writedata writedata Output 32
#
# connection point ctl_video
#
add_interface ctl_video avalon start
set_interface_property ctl_video addressUnits WORDS
set_interface_property ctl_video associatedClock clock
set_interface_property ctl_video associatedReset reset
set_interface_property ctl_video bitsPerSymbol 8
set_interface_property ctl_video burstOnBurstBoundariesOnly false
set_interface_property ctl_video burstcountUnits WORDS
set_interface_property ctl_video doStreamReads false
set_interface_property ctl_video doStreamWrites false
set_interface_property ctl_video holdTime 0
set_interface_property ctl_video linewrapBursts false
set_interface_property ctl_video maximumPendingReadTransactions 0
set_interface_property ctl_video maximumPendingWriteTransactions 0
set_interface_property ctl_video readLatency 0
set_interface_property ctl_video readWaitTime 1
set_interface_property ctl_video setupTime 0
set_interface_property ctl_video timingUnits Cycles
set_interface_property ctl_video writeWaitTime 0
set_interface_property ctl_video ENABLED true
set_interface_property ctl_video EXPORT_OF ""
set_interface_property ctl_video PORT_NAME_MAP ""
set_interface_property ctl_video CMSIS_SVD_VARIABLES ""
set_interface_property ctl_video SVD_ADDRESS_GROUP ""
add_interface_port ctl_video video_address address Output 8
add_interface_port ctl_video video_byteenable byteenable Output 4
add_interface_port ctl_video video_waitrequest waitrequest Input 1
add_interface_port ctl_video video_write write Output 1
add_interface_port ctl_video video_writedata writedata Output 32
#
# connection point control
#
add_interface control conduit end
set_interface_property control associatedClock clock
set_interface_property control associatedReset reset
set_interface_property control ENABLED true
set_interface_property control EXPORT_OF ""
set_interface_property control PORT_NAME_MAP ""
set_interface_property control CMSIS_SVD_VARIABLES ""
set_interface_property control SVD_ADDRESS_GROUP ""
add_interface_port control address address Input 9
add_interface_port control write write Input 1
add_interface_port control writedata writedata Input 32
add_interface_port control waitrequest waitrequest Output 1
add_interface_port control clock clock Output 1
add_interface_port control reset reset Output 1

3706
sys/ip/de10_hps_hw.tcl Normal file
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48
sys/ip/reset_source.v Normal file
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// reset_source.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module reset_source
(
input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset
input wire reset_req, // .reset_req
input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
);
assign reset_cold = cold_req;
assign reset_warm = warm_req;
assign reset = reset_sys;
assign reset_sys = sys_reset | reset_hps | reset_req;
reg sys_reset = 1;
always @(posedge clk) begin
integer timeout = 0;
reg reset_lock = 0;
reset_lock <= reset_lock | cold_req;
if(timeout < 2000000) begin
sys_reset <= 1;
timeout <= timeout + 1;
reset_lock <= 0;
end
else begin
sys_reset <= reset_lock;
end
end
endmodule

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# TCL File Generated by Component Editor 16.1
# Thu Apr 20 14:20:36 CST 2017
# DO NOT MODIFY
#
# reset_source "reset_source" v1.0
# Sorgelig 2017.04.20.14:20:36
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module reset_source
#
set_module_property DESCRIPTION ""
set_module_property NAME reset_source
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME reset_source
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_hps
#
add_interface reset_hps reset end
set_interface_property reset_hps associatedClock ""
set_interface_property reset_hps synchronousEdges NONE
set_interface_property reset_hps ENABLED true
set_interface_property reset_hps EXPORT_OF ""
set_interface_property reset_hps PORT_NAME_MAP ""
set_interface_property reset_hps CMSIS_SVD_VARIABLES ""
set_interface_property reset_hps SVD_ADDRESS_GROUP ""
add_interface_port reset_hps reset_hps reset Input 1
#
# connection point reset_sys
#
add_interface reset_sys reset start
set_interface_property reset_sys associatedClock ""
set_interface_property reset_sys associatedDirectReset ""
set_interface_property reset_sys associatedResetSinks ""
set_interface_property reset_sys synchronousEdges NONE
set_interface_property reset_sys ENABLED true
set_interface_property reset_sys EXPORT_OF ""
set_interface_property reset_sys PORT_NAME_MAP ""
set_interface_property reset_sys CMSIS_SVD_VARIABLES ""
set_interface_property reset_sys SVD_ADDRESS_GROUP ""
add_interface_port reset_sys reset_sys reset Output 1
#
# connection point reset_ctl
#
add_interface reset_ctl conduit end
set_interface_property reset_ctl associatedClock ""
set_interface_property reset_ctl associatedReset ""
set_interface_property reset_ctl ENABLED true
set_interface_property reset_ctl EXPORT_OF ""
set_interface_property reset_ctl PORT_NAME_MAP ""
set_interface_property reset_ctl CMSIS_SVD_VARIABLES ""
set_interface_property reset_ctl SVD_ADDRESS_GROUP ""
add_interface_port reset_ctl cold_req cold_req Input 1
add_interface_port reset_ctl reset reset Output 1
add_interface_port reset_ctl reset_req reset_req Input 1
add_interface_port reset_ctl warm_req warm_req Input 1
#
# connection point reset_warm
#
add_interface reset_warm reset start
set_interface_property reset_warm associatedClock ""
set_interface_property reset_warm associatedDirectReset ""
set_interface_property reset_warm associatedResetSinks ""
set_interface_property reset_warm synchronousEdges NONE
set_interface_property reset_warm ENABLED true
set_interface_property reset_warm EXPORT_OF ""
set_interface_property reset_warm PORT_NAME_MAP ""
set_interface_property reset_warm CMSIS_SVD_VARIABLES ""
set_interface_property reset_warm SVD_ADDRESS_GROUP ""
add_interface_port reset_warm reset_warm reset Output 1
#
# connection point reset_cold
#
add_interface reset_cold reset start
set_interface_property reset_cold associatedClock ""
set_interface_property reset_cold associatedDirectReset ""
set_interface_property reset_cold associatedResetSinks ""
set_interface_property reset_cold synchronousEdges NONE
set_interface_property reset_cold ENABLED true
set_interface_property reset_cold EXPORT_OF ""
set_interface_property reset_cold PORT_NAME_MAP ""
set_interface_property reset_cold CMSIS_SVD_VARIABLES ""
set_interface_property reset_cold SVD_ADDRESS_GROUP ""
add_interface_port reset_cold reset_cold reset Output 1

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sys/lpf48k.sv Normal file
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// low pass filter
// Revision 1.00
//
// Copyright (c) 2008 Takayuki Hara.
// All rights reserved.
//
// Redistribution and use of this source code or any derivative works, are
// permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// 3. Redistributions may not be sold, nor may they be used in a commercial
// product or activity without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// LPF (cut off 48kHz at 3.58MHz)
module lpf48k #(parameter MSB = 15)
(
input RESET,
input CLK,
input CE,
input ENABLE,
input [MSB:0] IDATA,
output [MSB:0] ODATA
);
wire [7:0] LPF_TAP_DATA[0:71] =
'{
8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09,
8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B,
8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D,
8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D,
8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B,
8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09,
8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51
};
reg [7:0] FF_ADDR = 0;
reg [MSB+10:0] FF_INTEG = 0;
wire [MSB+8:0] W_DATA;
wire W_ADDR_END;
assign W_ADDR_END = ((FF_ADDR == 71));
reg [MSB:0] OUT;
assign ODATA = ENABLE ? OUT : IDATA;
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_ADDR <= 0;
else
begin
if (CE) begin
if (W_ADDR_END) FF_ADDR <= 0;
else FF_ADDR <= FF_ADDR + 1'd1;
end
end
end
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_INTEG <= 0;
else
begin
if (CE) begin
if (W_ADDR_END) FF_INTEG <= 0;
else FF_INTEG <= FF_INTEG + W_DATA;
end
end
end
always @(posedge RESET or posedge CLK) begin
if (RESET) OUT <= 0;
else
begin
if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10];
end
end
endmodule

168
sys/osd.v Normal file
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@ -0,0 +1,168 @@
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd
(
input clk_sys,
input io_osd,
input io_strobe,
input [7:0] io_din,
input clk_video,
input [23:0] din,
output [23:0] dout,
input de
);
parameter OSD_COLOR = 3'd4;
parameter OSD_X_OFFSET = 12'd0;
parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
// this core supports only the display related OSD commands
// of the minimig v1
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096]; // the OSD buffer itself
reg highres = 0;
// the OSD has its own SPI interface to the io controller
always@(posedge clk_sys) begin
reg [11:0] bcnt;
reg [7:0] cmd;
reg has_cmd;
reg old_strobe;
old_strobe <= io_strobe;
if(~io_osd) begin
bcnt <= 0;
has_cmd <= 0;
end else begin
if(~old_strobe & io_strobe) begin
if(!has_cmd) begin
has_cmd <= 1;
cmd <= io_din;
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(io_din[7:4] == 4'b0100) begin
osd_enable <= io_din[0];
if(!io_din[0]) highres <= 0;
end
bcnt <= {io_din[3:0], 8'h00};
if(io_din[7:3] == 5'b00101) highres <= 1;
end else begin
// command 0x20: OSDCMDWRITE
if(cmd[7:4] == 4'b0010) begin
osd_buffer[bcnt] <= io_din;
bcnt <= bcnt + 1'd1;
end
end
end
end
end
reg ce_pix;
always @(negedge clk_video) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg deD;
cnt <= cnt + 1;
deD <= de;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(~deD && de) cnt <= 0;
if(deD && ~de) begin
pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
pixcnt <= 0;
end
end
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] dsp_height;
reg [7:0] osd_byte;
reg [21:0] osd_vcnt;
reg [21:0] fheight;
wire [21:0] hrheight = (OSD_HEIGHT<<highres);
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
if(ce_pix) begin
deD <= de;
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
// falling edge of de
if(!de && deD) dsp_width <= h_cnt[21:0];
// rising edge of de
if(de && !deD) begin
v_cnt <= v_cnt + 1'd1;
if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 0;
dsp_height <= v_cnt;
if(v_cnt<320) begin
multiscan <= 0;
fheight <= hrheight;
end
else if(v_cnt<640) begin
multiscan <= 1;
fheight <= hrheight << 1;
end
else if(v_cnt<960) begin
multiscan <= 2;
fheight <= hrheight + (hrheight<<1);
end
else begin
multiscan <= 3;
fheight <= hrheight << 2;
end
end
h_cnt <= 0;
osd_div <= osd_div + 1'd1;
if(osd_div == multiscan) begin
osd_div <= 0;
osd_vcnt <= osd_vcnt + 1'd1;
end
if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
end
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
end
end
// area in which OSD is being displayed
wire [21:0] h_osd_start = ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
wire [21:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [21:0] v_osd_start = ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
wire [21:0] v_osd_end = v_osd_start + fheight;
wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1;
wire osd_de = osd_enable &&
(h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
wire osd_pixel = osd_byte[osd_vcnt[2:0]];
assign dout = !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
endmodule

120
sys/pattern_vg.v Normal file
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@ -0,0 +1,120 @@
module pattern_vg
#(
parameter B=8, // number of bits per channel
X_BITS=13,
Y_BITS=13,
FRACTIONAL_BITS = 12
)
(
input reset, clk_in,
input wire [X_BITS-1:0] x,
input wire [Y_BITS-1:0] y,
input wire vn_in, hn_in, dn_in,
input wire [B-1:0] r_in, g_in, b_in,
output reg vn_out, hn_out, den_out,
output reg [B-1:0] r_out, g_out, b_out,
input wire [X_BITS-1:0] total_active_pix,
input wire [Y_BITS-1:0] total_active_lines,
input wire [7:0] pattern,
input wire [B+FRACTIONAL_BITS-1:0] ramp_step
);
reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values
//wire bar_0 = y<90;
wire bar_1 = y>=90 & y<180;
wire bar_2 = y>=180 & y<270;
wire bar_3 = y>=270 & y<360;
wire bar_4 = y>=360 & y<450;
wire bar_5 = y>=450 & y<540;
wire bar_6 = y>=540 & y<630;
wire bar_7 = y>=630 & y<720;
wire red_enable = bar_1 | bar_3 | bar_5 | bar_7;
wire green_enable = bar_2 | bar_3 | bar_6 | bar_7;
wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7;
always @(posedge clk_in)
begin
vn_out <= vn_in;
hn_out <= hn_in;
den_out <= dn_in;
if (reset)
ramp_values <= 0;
else if (pattern == 8'b0) // no pattern
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
else if (pattern == 8'b1) // border
begin
if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else // Double-border (OzOnE)...
if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
begin
r_out <= 8'hD0;
g_out <= 8'hB0;
b_out <= 8'hB0;
end
else
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
end
else if (pattern == 8'd2) // moireX
begin
if ((dn_in) && x[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd3) // moireY
begin
if ((dn_in) && y[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd4) // Simple RAMP
begin
r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
if ((x == total_active_pix - 1) && (dn_in))
ramp_values <= 0;
else if ((x == 0) && (dn_in))
ramp_values <= ramp_step;
else if (dn_in)
ramp_values <= ramp_values + ramp_step;
end
end
endmodule

337
sys/pll.qip Normal file
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@ -0,0 +1,337 @@
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjguMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::NTAwMA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::NDM0MCBwcw==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NjMw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjEw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::ODAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::ODA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MjEuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::NTAwMCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Nyw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwxMywxMiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDI1LDI1LDQsNCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw3MDAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"

255
sys/pll.v Normal file
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@ -0,0 +1,255 @@
// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="28.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="14.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="5000" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="4340 ps" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="10.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="30.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="80.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="21.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v

4
sys/pll/pll_0002.qip Normal file
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@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

90
sys/pll/pll_0002.v Normal file
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@ -0,0 +1,90 @@
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("28.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("14.000000 MHz"),
.phase_shift1("5000 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

337
sys/pll_hdmi.qip Normal file
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@ -0,0 +1,337 @@
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk="
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NzQuMjU=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NzQuMjUwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDMsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyMCw0MDAwLDQ0NS40OTk5OTkgTUh6LDM5MDg0MjAxNTMsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"]
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"

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sys/pll_hdmi.v Normal file
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// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll_hdmi.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_hdmi (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
pll_hdmi_0002 pll_hdmi_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="74.25" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll_hdmi.vo
// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v

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set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

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`timescale 1ns/10ps
module pll_hdmi_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("74.250000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
output ce_pix_out,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input hb_in,
input vb_in,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output hb_out,
output vb_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
assign vs_out = vs_in;
assign ce_pix_out = ce_x4;
//Compensate picture shift after HQ2x
assign vb_out = vbo[2];
assign hb_out = &hbo[5:4];
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
req_line_reset <= 0;
if(hb_in) req_line_reset <= 1;
end
end
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4),
.inputpixel({b_d,g_d,r_d}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h;
reg [1:0] sd_line;
reg [2:0] vbo;
reg [5:0] hbo;
reg [DWIDTH:0] r_d;
reg [DWIDTH:0] g_d;
reg [DWIDTH:0] b_d;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg [11:0] hde_start, hde_end;
reg hs, hs2, vs, hb;
if(ce_x1) begin
hs <= hs_in;
hb <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
if(hb && !hb_in) begin
hde_start <= {hcnt,1'b0};
vbo <= {vbo[1:0], vb_in};
end
if(!hb && hb_in) hde_end <= {hcnt,1'b0};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
hbo[5:1] <= hbo[4:0];
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
if(~&hbo) sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
//prepare to read in advance
if(sd_hcnt == (hde_start-2)) begin
sd_h <= 0;
sd_line <= sd_line + 1'd1;
end
if(sd_hcnt == hde_start) hbo[0] <= 0;
if(sd_hcnt == hde_end) hbo[0] <= 1;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
end
end
endmodule

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//
// sdram.v
//
// Static RAM controller implementation using SDRAM MT48LC16M16A2
//
// Copyright (c) 2015,2016 Sorgelig
//
// Some parts of SDRAM code used from project:
// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
// v2.1 - Add universal 8/16 bit mode.
//
module sdram
(
input init, // reset to initialize RAM
input clk, // clock ~100MHz
//
// SDRAM_* - signals to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, //
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
output SDRAM_CKE, // clock enable
//
input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte,
// 8bit mode: 2'b00 - use addr[0] to decide which byte to write
// Ignored while reading.
//
input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
output [15:0] dout, // data output to cpu
input [15:0] din, // data input from cpu
input we, // cpu requests write
input rd, // cpu requests read
output reg ready // dout is valid. Ready to accept new read/write.
);
assign SDRAM_nCS = command[3];
assign SDRAM_nRAS = command[2];
assign SDRAM_nCAS = command[1];
assign SDRAM_nWE = command[0];
assign SDRAM_CKE = cke;
assign dout = latched ? data_l : data_d;
// no burst configured
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
localparam cycles_per_refresh = 14'd780; // (64000*100)/8192-1 Calc'd as (64ms @ 100MHz)/8192 rose
localparam startup_refresh_max = 14'b11111111111111;
// SDRAM commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
reg [3:0] command = CMD_INHIBIT;
reg cke = 0;
reg [24:0] save_addr;
reg latched;
reg [15:0] data;
wire[15:0] data_l = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]};
wire[15:0] data_d = save_addr[0] ? {SDRAM_DQ[7:0], SDRAM_DQ[15:8]} : {SDRAM_DQ[15:8], SDRAM_DQ[7:0]};
typedef enum
{
STATE_STARTUP,
STATE_OPEN_1, STATE_OPEN_2,
STATE_WRITE,
STATE_READ,
STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
} state_t;
always @(posedge clk) begin
reg old_we, old_rd;
reg [CAS_LATENCY:0] data_ready_delay;
reg [15:0] new_data;
reg [1:0] new_wtbt;
reg new_we;
reg new_rd;
reg save_we = 1;
state_t state = STATE_STARTUP;
command <= CMD_NOP;
refresh_count <= refresh_count+1'b1;
data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
// make it ready 1T in advance
if(data_ready_delay[1]) {latched, ready} <= {1'b0, 1'b1};
if(data_ready_delay[0]) {latched, data} <= {1'b1, SDRAM_DQ};
case(state)
STATE_STARTUP: begin
//------------------------------------------------------------------------
//-- This is the initial startup state, where we wait for at least 100us
//-- before starting the start sequence
//--
//-- The initialisation is sequence is
//-- * de-assert SDRAM_CKE
//-- * 100us wait,
//-- * assert SDRAM_CKE
//-- * wait at least one cycle,
//-- * PRECHARGE
//-- * wait 2 cycles
//-- * REFRESH,
//-- * tREF wait
//-- * REFRESH,
//-- * tREF wait
//-- * LOAD_MODE_REG
//-- * 2 cycles wait
//------------------------------------------------------------------------
cke <= 1;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
SDRAM_DQML <= 1;
SDRAM_DQMH <= 1;
SDRAM_A <= 0;
SDRAM_BA <= 0;
// All the commands during the startup are NOPS, except these
if(refresh_count == startup_refresh_max-31) begin
// ensure all rows are closed
command <= CMD_PRECHARGE;
SDRAM_A[10] <= 1; // all banks
SDRAM_BA <= 2'b00;
end else if (refresh_count == startup_refresh_max-23) begin
// these refreshes need to be at least tREF (66ns) apart
command <= CMD_AUTO_REFRESH;
end else if (refresh_count == startup_refresh_max-15)
command <= CMD_AUTO_REFRESH;
else if (refresh_count == startup_refresh_max-7) begin
// Now load the mode register
command <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
end
//------------------------------------------------------
//-- if startup is complete then go into idle mode,
//-- get prepared to accept a new command, and schedule
//-- the first refresh cycle
//------------------------------------------------------
if(!refresh_count) begin
state <= STATE_IDLE;
ready <= 1;
refresh_count <= 0;
end
end
STATE_IDLE_7: state <= STATE_IDLE_6;
STATE_IDLE_6: state <= STATE_IDLE_5;
STATE_IDLE_5: state <= STATE_IDLE_4;
STATE_IDLE_4: state <= STATE_IDLE_3;
STATE_IDLE_3: state <= STATE_IDLE_2;
STATE_IDLE_2: state <= STATE_IDLE_1;
STATE_IDLE_1: begin
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
state <= STATE_IDLE;
// mask possible refresh to reduce colliding.
if(refresh_count > cycles_per_refresh) begin
//------------------------------------------------------------------------
//-- Start the refresh cycle.
//-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
//------------------------------------------------------------------------
state <= STATE_IDLE_7;
command <= CMD_AUTO_REFRESH;
refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
end
end
STATE_IDLE: begin
// Priority is to issue a refresh if one is outstanding
if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
else if(new_rd | new_we) begin
new_we <= 0;
new_rd <= 0;
save_addr<= addr;
save_we <= new_we;
state <= STATE_OPEN_1;
command <= CMD_ACTIVE;
SDRAM_A <= addr[13:1];
SDRAM_BA <= addr[24:23];
end
end
// ACTIVE-to-READ or WRITE delay >20ns (-75)
STATE_OPEN_1: state <= STATE_OPEN_2;
STATE_OPEN_2: begin
SDRAM_A <= {4'b0010, save_addr[22:14]};
SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]);
SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
state <= save_we ? STATE_WRITE : STATE_READ;
end
STATE_READ: begin
state <= STATE_IDLE_5;
command <= CMD_READ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
// Schedule reading the data values off the bus
data_ready_delay[CAS_LATENCY] <= 1;
end
STATE_WRITE: begin
state <= STATE_IDLE_5;
command <= CMD_WRITE;
SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
ready <= 1;
end
endcase
if(init) begin
state <= STATE_STARTUP;
refresh_count <= startup_refresh_max - sdram_startup_cycles;
end
old_we <= we;
if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
old_rd <= rd;
if(rd & ~old_rd) begin
if(ready & ~save_we & (save_addr[24:1] == addr[24:1])) save_addr <= addr;
else {ready, new_rd} <= {1'b0, 1'b1};
end
end
endmodule

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//
// PWM DAC
//
// MSBI is the highest bit number. NOT amount of bits!
//
module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1)
(
output reg DACout, //Average Output feeding analog lowpass
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
input CLK,
input RESET
);
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*) DeltaAdder = DACin + DeltaB;
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge CLK or posedge RESET) begin
if(RESET) begin
SigmaLatch <= 1'b1 << (MSBI+1);
DACout <= INV;
end else begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[MSBI+2] ^ INV;
end
end
endmodule

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//-----------------------------------------------------------------
// SPDIF Transmitter
// V0.1
// Ultra-Embedded.com
// Copyright 2012
//
// Email: admin@ultra-embedded.com
//
// License: GPL
// If you would like a version with a more permissive license for
// use in closed source commercial applications please contact me
// for details.
//-----------------------------------------------------------------
//
// This file is open source HDL; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as
// published by the Free Software Foundation; either version 2 of
// the License, or (at your option) any later version.
//
// This file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this file; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//-----------------------------------------------------------------
// altera message_off 10762
// altera message_off 10240
module spdif
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_RATE = 48000,
// Generated params
parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128),
parameter ERROR_BASE = 10000,
parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input half_rate,
// Output
output spdif_o,
// Audio interface (16-bit x 2 = RL)
input [15:0] audio_r,
input [15:0] audio_l,
output sample_req_o
);
reg bit_clk_q;
// Clock pulse generator
always @ (posedge rst_i or posedge clk_i) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg ce;
if (rst_i) begin
count_q <= 0;
error_q <= 0;
bit_clk_q <= 1;
ce <= 0;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
bit_clk_q <= 0;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) bit_clk_q <= 1;
end
end
end
//-----------------------------------------------------------------
// Core SPDIF
//-----------------------------------------------------------------
wire [31:0] sample_i = {audio_r, audio_l};
spdif_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.bit_out_en_i(bit_clk_q),
.spdif_o(spdif_o),
.sample_i(sample_i),
.sample_req_o(sample_req_o)
);
endmodule
module spdif_core
(
input clk_i,
input rst_i,
// SPDIF bit output enable
// Single cycle pulse synchronous to clk_i which drives
// the output bit rate.
// For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
// For 48KHz, 48000×32×2×2 = 6,144,000Hz
input bit_out_en_i,
// Output
output spdif_o,
// Audio interface (16-bit x 2 = RL)
input [31:0] sample_i,
output reg sample_req_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [15:0] audio_sample_q;
reg [8:0] subframe_count_q;
reg load_subframe_q;
reg [7:0] preamble_q;
wire [31:0] subframe_w;
reg [5:0] bit_count_q;
reg bit_toggle_q;
reg spdif_out_q;
reg [5:0] parity_count_q;
//-----------------------------------------------------------------
// Subframe Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
subframe_count_q <= 9'd0;
else if (load_subframe_q)
begin
// 192 frames (384 subframes) in an audio block
if (subframe_count_q == 9'd383)
subframe_count_q <= 9'd0;
else
subframe_count_q <= subframe_count_q + 9'd1;
end
end
//-----------------------------------------------------------------
// Sample capture
//-----------------------------------------------------------------
reg [15:0] sample_buf_q;
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
audio_sample_q <= 16'h0000;
sample_buf_q <= 16'h0000;
sample_req_o <= 1'b0;
end
else if (load_subframe_q)
begin
// Start of frame (first subframe)?
if (subframe_count_q[0] == 1'b0)
begin
// Use left sample
audio_sample_q <= sample_i[15:0];
// Store right sample
sample_buf_q <= sample_i[31:16];
// Request next sample
sample_req_o <= 1'b1;
end
else
begin
// Use right sample
audio_sample_q <= sample_buf_q;
sample_req_o <= 1'b0;
end
end
else
sample_req_o <= 1'b0;
end
// Timeslots 3 - 0 = Preamble
assign subframe_w[3:0] = 4'b0000;
// Timeslots 7 - 4 = 24-bit audio LSB
assign subframe_w[7:4] = 4'b0000;
// Timeslots 11 - 8 = 20-bit audio LSB
assign subframe_w[11:8] = 4'b0000;
// Timeslots 27 - 12 = 16-bit audio
assign subframe_w[27:12] = audio_sample_q;
// Timeslots 28 = Validity
assign subframe_w[28] = 1'b0; // Valid
// Timeslots 29 = User bit
assign subframe_w[29] = 1'b0;
// Timeslots 30 = Channel status bit
assign subframe_w[30] = 1'b0;
// Timeslots 31 = Even Parity bit (31:4)
assign subframe_w[31] = 1'b0;
//-----------------------------------------------------------------
// Preamble
//-----------------------------------------------------------------
localparam PREAMBLE_Z = 8'b00010111;
localparam PREAMBLE_Y = 8'b00100111;
localparam PREAMBLE_X = 8'b01000111;
reg [7:0] preamble_r;
always @ *
begin
// Start of audio block?
// Z(B) - Left channel
if (subframe_count_q == 9'd0)
preamble_r = PREAMBLE_Z; // Z(B)
// Right Channel?
else if (subframe_count_q[0] == 1'b1)
preamble_r = PREAMBLE_Y; // Y(W)
// Left Channel (but not start of block)?
else
preamble_r = PREAMBLE_X; // X(M)
end
always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
preamble_q <= 8'h00;
else if (load_subframe_q)
preamble_q <= preamble_r;
//-----------------------------------------------------------------
// Parity Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
parity_count_q <= 6'd0;
end
// Time to output a bit?
else if (bit_out_en_i)
begin
// Preamble bits?
if (bit_count_q < 6'd8)
begin
parity_count_q <= 6'd0;
end
// Normal timeslots
else if (bit_count_q < 6'd62)
begin
// On first pass through this timeslot, count number of high bits
if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
parity_count_q <= parity_count_q + 6'd1;
end
end
end
//-----------------------------------------------------------------
// Bit Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
begin
if (rst_i == 1'b1)
begin
bit_count_q <= 6'b0;
load_subframe_q <= 1'b1;
end
// Time to output a bit?
else if (bit_out_en_i)
begin
// 32 timeslots (x2 for double frequency)
if (bit_count_q == 6'd63)
begin
bit_count_q <= 6'd0;
load_subframe_q <= 1'b1;
end
else
begin
bit_count_q <= bit_count_q + 6'd1;
load_subframe_q <= 1'b0;
end
end
else
load_subframe_q <= 1'b0;
end
//-----------------------------------------------------------------
// Bit half toggle
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
if (rst_i == 1'b1)
bit_toggle_q <= 1'b0;
// Time to output a bit?
else if (bit_out_en_i)
bit_toggle_q <= ~bit_toggle_q;
//-----------------------------------------------------------------
// Output bit (BMC encoded)
//-----------------------------------------------------------------
reg bit_r;
always @ *
begin
bit_r = spdif_out_q;
// Time to output a bit?
if (bit_out_en_i)
begin
// Preamble bits?
if (bit_count_q < 6'd8)
begin
bit_r = preamble_q[bit_count_q[2:0]];
end
// Normal timeslots
else if (bit_count_q < 6'd62)
begin
if (subframe_w[bit_count_q / 2] == 1'b0)
begin
if (bit_toggle_q == 1'b0)
bit_r = ~spdif_out_q;
else
bit_r = spdif_out_q;
end
else
bit_r = ~spdif_out_q;
end
// Parity timeslot
else
begin
// Even number of high bits, make odd
if (parity_count_q[0] == 1'b0)
begin
if (bit_toggle_q == 1'b0)
bit_r = ~spdif_out_q;
else
bit_r = spdif_out_q;
end
else
bit_r = ~spdif_out_q;
end
end
end
always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
spdif_out_q <= 1'b0;
else
spdif_out_q <= bit_r;
assign spdif_o = spdif_out_q;
endmodule

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module sync_vg
#(
parameter X_BITS=12,
Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire interlaced,
input wire [Y_BITS-1:0] v_total_0,
input wire [Y_BITS-1:0] v_fp_0,
input wire [Y_BITS-1:0] v_bp_0,
input wire [Y_BITS-1:0] v_sync_0,
input wire [Y_BITS-1:0] v_total_1,
input wire [Y_BITS-1:0] v_fp_1,
input wire [Y_BITS-1:0] v_bp_1,
input wire [Y_BITS-1:0] v_sync_1,
input wire [X_BITS-1:0] h_total,
input wire [X_BITS-1:0] h_fp,
input wire [X_BITS-1:0] h_bp,
input wire [X_BITS-1:0] h_sync,
input wire [X_BITS-1:0] hv_offset_0,
input wire [X_BITS-1:0] hv_offset_1,
output reg vs_out,
output reg hs_out,
output reg hde_out,
output reg vde_out,
output reg [Y_BITS:0] v_count_out,
output reg [X_BITS-1:0] h_count_out,
output reg [X_BITS-1:0] x_out,
output reg [Y_BITS:0] y_out,
output reg field_out,
output wire clk_out
);
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
reg field;
reg [Y_BITS-1:0] v_total;
reg [Y_BITS-1:0] v_fp;
reg [Y_BITS-1:0] v_bp;
reg [Y_BITS-1:0] v_sync;
reg [X_BITS-1:0] hv_offset;
assign clk_out = !clk;
/* horizontal counter */
always @(posedge clk)
if (reset)
h_count <= 0;
else
if (h_count < h_total - 1)
h_count <= h_count + 1'd1;
else
h_count <= 0;
/* vertical counter */
always @(posedge clk)
if (reset)
v_count <= 0;
else
if (h_count == h_total - 1)
begin
if (v_count == v_total - 1)
v_count <= 0;
else
v_count <= v_count + 1'd1;
end
/* field */
always @(posedge clk)
if (reset)
begin
field <= 0;
v_total <= v_total_0;
v_fp <= interlaced ? v_fp_1 : v_fp_0; // In the interlaced mode this value must be inverted as v_fp_1 is still in field0
v_bp <= v_bp_0;
v_sync <= v_sync_0;
hv_offset <= hv_offset_0;
end
else
if ((interlaced) && ((v_count == v_total - 1) && (h_count == h_total - 1)))
begin
field <= field + interlaced;
v_total <= field ? v_total_0 : v_total_1;
v_fp <= field ? v_fp_1 : v_fp_0; // This order is inverted as v_fp_1 is still in field0
v_bp <= field ? v_bp_0 : v_bp_1;
v_sync <= field ? v_sync_0 : v_sync_1;
hv_offset <= field ? hv_offset_0 : hv_offset_1;
end
always @(posedge clk)
if (reset)
{ vs_out, hs_out, hde_out, vde_out, field_out } <= 4'b0;
else begin
hs_out <= ((h_count < h_sync));
hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
if ((v_count == 0) && (h_count == hv_offset))
vs_out <= 1'b1;
else if ((v_count == v_sync) && (h_count == hv_offset))
vs_out <= 1'b0;
/* H_COUNT_OUT and V_COUNT_OUT */
h_count_out <= h_count;
if (field)
v_count_out <= v_count + v_total_0;
else
v_count_out <= v_count;
/* X and Y coords <EFBFBD> for a backend pattern generator */
x_out <= h_count - (h_sync + h_bp);
if (interlaced)
y_out <= { (v_count - (v_sync + v_bp)) , field };
else
y_out <= { 1'b0, (v_count - (v_sync + v_bp)) };
field_out <= field;
end
endmodule

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set_global_assignment -name VERILOG_FILE sys/sys_top.v
set_global_assignment -name SDC_FILE sys/sys_top.sdc
set_global_assignment -name QIP_FILE sys/pll.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name SYSTEMVERILOG_FILE sys/sdram.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
set_global_assignment -name VERILOG_FILE sys/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
set_global_assignment -name VERILOG_FILE sys/osd.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv
set_global_assignment -name VERILOG_FILE sys/sync_vg.v
set_global_assignment -name VERILOG_FILE sys/pattern_vg.v
set_global_assignment -name VERILOG_FILE sys/i2c.v
set_global_assignment -name VERILOG_FILE sys/i2s.v
set_global_assignment -name VERILOG_FILE sys/spdif.v
set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
set_global_assignment -name VERILOG_FILE sys/hps_io.v

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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
derive_pll_clocks
#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
derive_clock_uncertainty
#set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
#set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
-to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-setup 2
#set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_false_path -from * -to [get_ports {LED_*}]
set_false_path -from * -to [get_ports {BTN_*}]
set_false_path -from * -to [get_ports {VGA_*}]
set_false_path -from * -to [get_ports {AUDIO_L}]
set_false_path -from * -to [get_ports {AUDIO_R}]

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//============================================================================
//
// DE10-nano HAL top module
// (c)2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module sys_top
(
/////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
//////////// VGA ///////////
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
input VGA_EN,
/////////// AUDIO //////////
output AUDIO_L,
output AUDIO_R,
output AUDIO_SPDIF,
//////////// HDMI //////////
output HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
output HDMI_MCLK,
output HDMI_SCLK,
output HDMI_LRCLK,
output HDMI_I2S,
output HDMI_TX_CLK,
output HDMI_TX_DE,
output [23:0] HDMI_TX_D,
output HDMI_TX_HS,
output HDMI_TX_VS,
//////////// SDR ///////////
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE,
//////////// I/O ///////////
output LED_USER,
output LED_HDD,
output LED_POWER,
input BTN_USER,
input BTN_OSD,
input BTN_RESET,
//////////// SDIO ///////////
inout [3:0] SDIO_DAT,
inout SDIO_CMD,
output SDIO_CLK,
input SDIO_CD,
////////// MB KEY ///////////
input [1:0] KEY,
////////// MB LED ///////////
output [7:0] LED
);
assign SDIO_DAT[2:1] = 2'bZZ;
////////////////////////// LEDs ///////////////////////////////////////
wire led_p = led_power[1] ? ~led_power[0] : 1'b0;
wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
wire led_u = ~led_user;
assign LED_POWER = led_p ? 1'bZ : 1'b0;
assign LED_HDD = led_d ? 1'bZ : 1'b0;
assign LED_USER = led_u ? 1'bZ : 1'b0;
//LEDs on main board
assign LED = {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u};
////////////////////////// Buttons ///////////////////////////////////
reg btn_user, btn_osd;
always @(posedge FPGA_CLK2_50) begin
integer div;
reg [7:0] deb_user;
reg [7:0] deb_osd;
div <= div + 1'b1;
if(div > 100000) div <= 0;
if(!div) begin
deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])};
if(&deb_user) btn_user <= 1;
if(!deb_user) btn_user <= 0;
deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])};
if(&deb_osd) btn_osd <= 1;
if(!deb_osd) btn_osd <= 0;
end
end
reg btn_reset = 1;
always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET;
///////////////////////// HPS I/O /////////////////////////////////////
// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
// used to avoid lockups while JTAG loading
wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout};
wire [31:0] gp_out;
wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future.
wire io_wait;
wire io_wide;
wire [15:0] io_dout;
wire [15:0] io_din = gp_outr[15:0];
wire io_clk = gp_outr[17];
wire io_fpga = gp_outr[18];
wire io_osd = gp_outr[19];
wire io_uio = gp_outr[20];
//wire io_sdd = gp_outr[21]; // used only in ST core
reg io_ack;
reg rack;
wire io_strobe = ~rack & io_clk;
always @(posedge clk_sys) begin
if(~io_wait | io_strobe) begin
rack <= io_clk;
io_ack <= rack;
end
end
reg [31:0] gp_outr;
always @(posedge clk_sys) begin
reg [31:0] gp_outd;
gp_outr <= gp_outd;
gp_outd <= gp_out;
end
wire [7:0] core_type = 'hA4; // A4 - generic core.
// HPS will not communicate to core if magic is different
wire [31:0] core_magic = {24'h5CA623, core_type};
cyclonev_hps_interface_mpu_general_purpose h2f_gp
(
.gp_in({~gp_out[31] ? core_magic : gp_in}),
.gp_out(gp_out)
);
reg [15:0] cfg;
reg cfg_ready = 0;
wire audio_96k = cfg[6];
wire ypbpr_en = cfg[5];
wire csync = cfg[3];
`ifndef LITE
wire vga_scaler= cfg[2];
`endif
always@(posedge clk_sys) begin
reg [7:0] cmd;
reg has_cmd;
reg old_strobe;
old_strobe <= io_strobe;
if(~io_uio) has_cmd <= 0;
else
if(~old_strobe & io_strobe) begin
if(!has_cmd) begin
has_cmd <= 1;
cmd <= io_din[7:0];
end
else
if(cmd == 1) begin
cfg <= io_din;
cfg_ready <= 1;
end
end
end
/////////////////////////// RESET ///////////////////////////////////
reg reset_req = 0;
always @(posedge FPGA_CLK2_50) begin
reg [1:0] resetd, resetd2;
reg old_reset;
//latch the reset
old_reset <= reset;
if(~old_reset & reset) reset_req <= 1;
//special combination to set/clear the reset
//preventing of accidental reset control
if(resetd==1) reset_req <= 1;
if(resetd==2 && resetd2==0) reset_req <= 0;
resetd <= gp_out[31:30];
resetd2 <= resetd;
end
// 100MHz
wire ctl_clk;
///////////////////////// VIP version ///////////////////////////////
`ifndef LITE
wire reset;
vip vip
(
//Reset/Clock
.reset_reset_req(reset_req),
.reset_reset(reset),
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
.reset_cold_req(~btn_reset),
.reset_warm_req(0),
//control
.ctl_address(ctl_address),
.ctl_write(ctl_write),
.ctl_writedata(ctl_writedata),
.ctl_waitrequest(ctl_waitrequest),
.ctl_clock(ctl_clk),
.ctl_reset(ctl_reset),
//64-bit DDR3 RAM access
.ramclk1_clk(ram_clk),
.ram1_address(ram_address),
.ram1_burstcount(ram_burstcount),
.ram1_waitrequest(ram_waitrequest),
.ram1_readdata(ram_readdata),
.ram1_readdatavalid(ram_readdatavalid),
.ram1_read(ram_read),
.ram1_writedata(ram_writedata),
.ram1_byteenable(ram_byteenable),
.ram1_write(ram_write),
//Spare 64-bit DDR3 RAM access
//currently unused
//can combine with ram1 to make a wider RAM bus (although will increase the latency)
.ramclk2_clk(0),
.ram2_address(0),
.ram2_burstcount(0),
.ram2_waitrequest(),
.ram2_readdata(),
.ram2_readdatavalid(),
.ram2_read(0),
.ram2_writedata(0),
.ram2_byteenable(0),
.ram2_write(0),
//Video input
.in_vid_clk(clk_vid),
.in_vid_data({r_out, g_out, b_out}),
.in_vid_de(de),
.in_vid_v_sync(vs),
.in_vid_h_sync(hs),
.in_vid_datavalid(ce_pix),
.in_vid_locked(1),
.in_vid_f(0),
.in_vid_color_encoding(0),
.in_vid_bit_width(0),
//HDMI output
.hdmi_vid_clk(~HDMI_TX_CLK),
.hdmi_vid_data(hdmi_data),
.hdmi_vid_datavalid(HDMI_TX_DE),
.hdmi_vid_v_sync(HDMI_TX_VS),
.hdmi_vid_h_sync(HDMI_TX_HS)
);
wire [8:0] ctl_address;
wire ctl_write;
wire [31:0] ctl_writedata;
wire ctl_waitrequest;
wire ctl_reset;
wire [7:0] ARX, ARY;
vip_config vip_config
(
.clk(ctl_clk),
.reset(ctl_reset),
.ARX(ARX),
.ARY(ARY),
.address(ctl_address),
.write(ctl_write),
.writedata(ctl_writedata),
.waitrequest(ctl_waitrequest)
);
`endif
///////////////////////// Lite version ////////////////////////////////
`ifdef LITE
wire INTERLACED = 0;
wire [11:0] V_TOTAL_0 = 750;
wire [11:0] V_FP_0 = 5;
wire [11:0] V_BP_0 = 20;
wire [11:0] V_SYNC_0 = 5;
wire [11:0] V_TOTAL_1 = 0;
wire [11:0] V_FP_1 = 0;
wire [11:0] V_BP_1 = 0;
wire [11:0] V_SYNC_1 = 0;
wire [11:0] H_TOTAL = 1650;
wire [11:0] H_FP = 110;
wire [11:0] H_BP = 220;
wire [11:0] H_SYNC = 40;
wire [11:0] HV_OFFSET_0 = 0;
wire [11:0] HV_OFFSET_1 = 0;
wire [11:0] x;
wire [12:0] y;
sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
(
.clk(HDMI_TX_CLK),
.reset(reset),
.interlaced(INTERLACED),
.clk_out(), // inverted output clock - unconnected
.v_total_0(V_TOTAL_0),
.v_fp_0(V_FP_0),
.v_bp_0(V_BP_0),
.v_sync_0(V_SYNC_0),
.v_total_1(V_TOTAL_1),
.v_fp_1(V_FP_1),
.v_bp_1(V_BP_1),
.v_sync_1(V_SYNC_1),
.h_total(H_TOTAL),
.h_fp(H_FP),
.h_bp(H_BP),
.h_sync(H_SYNC),
.hv_offset_0(HV_OFFSET_0),
.hv_offset_1(HV_OFFSET_1),
.vde_out(vde),
.hde_out(hde),
.vs_out(vs_hdmi),
.v_count_out(),
.h_count_out(),
.x_out(x),
.y_out(y),
.hs_out(hs_hdmi),
.field_out(field)
);
wire vde, hde;
wire vs_hdmi;
wire hs_hdmi;
wire field;
pattern_vg
#(
.B(8), // Bits per channel
.X_BITS(12),
.Y_BITS(12),
.FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern
)
pattern_vg
(
.reset(reset),
.clk_in(HDMI_TX_CLK),
.x(x),
.y(y[11:0]),
.vn_in(vs_hdmi),
.hn_in(hs_hdmi),
.dn_in(vde & hde),
.r_in(0),
.g_in(0),
.b_in(0),
.vn_out(HDMI_TX_VS),
.hn_out(HDMI_TX_HS),
.den_out(HDMI_TX_DE),
.r_out(hdmi_data[23:16]),
.g_out(hdmi_data[15:8]),
.b_out(hdmi_data[7:0]),
.total_active_pix(H_TOTAL - (H_FP + H_BP + H_SYNC)),
.total_active_lines(INTERLACED ? (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0)) + (V_TOTAL_1 - (V_FP_1 + V_BP_1 + V_SYNC_1)) : (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0))), // originally: 13'd480
.pattern(4),
.ramp_step(20'h0333)
);
wire reset;
sysmem_lite sysmem
(
//Reset/Clock
.reset_reset_req(reset_req),
.reset_reset(reset),
.ctl_clock(ctl_clk),
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
.reset_cold_req(~btn_reset),
.reset_warm_req(0),
//64-bit DDR3 RAM access
.ramclk1_clk(ram_clk),
.ram1_address(ram_address),
.ram1_burstcount(ram_burstcount),
.ram1_waitrequest(ram_waitrequest),
.ram1_readdata(ram_readdata),
.ram1_readdatavalid(ram_readdatavalid),
.ram1_read(ram_read),
.ram1_writedata(ram_writedata),
.ram1_byteenable(ram_byteenable),
.ram1_write(ram_write),
//Spare 64-bit DDR3 RAM access
//currently unused
//can combine with ram1 to make a wider RAM bus (although will increase the latency)
.ramclk2_clk(0),
.ram2_address(0),
.ram2_burstcount(0),
.ram2_waitrequest(),
.ram2_readdata(),
.ram2_readdatavalid(),
.ram2_read(0),
.ram2_writedata(0),
.ram2_byteenable(0),
.ram2_write(0)
);
`endif
///////////////////////// HDMI output /////////////////////////////////
pll_hdmi pll_hdmi
(
.refclk(FPGA_CLK1_50),
.rst(reset),
.outclk_0(HDMI_TX_CLK)
);
hdmi_config hdmi_config
(
.iCLK(FPGA_CLK1_50),
.iRST_N(cfg_ready),
.I2C_SCL(HDMI_I2C_SCL),
.I2C_SDA(HDMI_I2C_SDA),
.audio_48k(~audio_96k),
.iRES(4), // 720p
.iAR(1) // Aspect Ratio
);
wire [23:0] hdmi_data;
osd hdmi_osd
(
.clk_sys(clk_sys),
.io_osd(io_osd),
.io_strobe(io_strobe),
.io_din(io_din[7:0]),
.clk_video(HDMI_TX_CLK),
.din(hdmi_data),
.dout(HDMI_TX_D),
.de(HDMI_TX_DE)
);
assign HDMI_MCLK = 0;
i2s i2s
(
.reset(~cfg_ready),
.clk_sys(FPGA_CLK1_50),
.half_rate(~audio_96k),
.sclk(HDMI_SCLK),
.lrclk(HDMI_LRCLK),
.sdata(HDMI_I2S),
//Could inverse the MSB but it will shift 0 level to -MAX level
.left_chan (audio_l >> !audio_s),
.right_chan(audio_r >> !audio_s)
);
///////////////////////// VGA output //////////////////////////////////
wire [23:0] vga_q;
osd vga_osd
(
.clk_sys(clk_sys),
.io_osd(io_osd),
.io_strobe(io_strobe),
.io_din(io_din[7:0]),
.clk_video(clk_vid),
.din(de ? {r_out, g_out, b_out} : 24'd0),
.dout(vga_q),
.de(de)
);
wire [23:0] vga_o;
vga_out vga_out
(
.ypbpr_full(1),
.ypbpr_en(ypbpr_en),
.dout(vga_o),
`ifdef LITE
.din(vga_q)
`else
.din(vga_scaler ? HDMI_TX_D : vga_q)
`endif
);
`ifdef LITE
wire vs1 = vs;
wire hs1 = hs;
`else
wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
`endif
assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1;
assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1;
assign VGA_R = VGA_EN ? 6'bZZZZZZ : vga_o[23:18];
assign VGA_G = VGA_EN ? 6'bZZZZZZ : vga_o[15:10];
assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
///////////////////////// Audio output ////////////////////////////////
sigma_delta_dac #(15) dac_l
(
.CLK(FPGA_CLK3_50),
.RESET(reset),
.DACin({audio_l[15] ^ audio_s, audio_l[14:0]}),
.DACout(AUDIO_L)
);
sigma_delta_dac #(15) dac_r
(
.CLK(FPGA_CLK3_50),
.RESET(reset),
.DACin({audio_r[15] ^ audio_s, audio_r[14:0]}),
.DACout(AUDIO_R)
);
spdif toslink
(
.clk_i(FPGA_CLK3_50),
.rst_i(reset),
.half_rate(0),
.audio_l(audio_l >> !audio_s),
.audio_r(audio_r >> !audio_s),
.spdif_o(AUDIO_SPDIF)
);
/////////////////// User module connection ////////////////////////////
wire [15:0] audio_l, audio_r;
wire audio_s;
wire [7:0] r_out, g_out, b_out;
wire vs, hs, de;
wire clk_sys, clk_vid, ce_pix;
wire ram_clk;
wire [28:0] ram_address;
wire [7:0] ram_burstcount;
wire ram_waitrequest;
wire [63:0] ram_readdata;
wire ram_readdatavalid;
wire ram_read;
wire [63:0] ram_writedata;
wire [7:0] ram_byteenable;
wire ram_write;
wire led_user;
wire [1:0] led_power;
wire [1:0] led_disk;
wire vs_emu, hs_emu;
sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs);
sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs);
emu emu
(
.CLK_50M(FPGA_CLK3_50),
.RESET(reset),
.HPS_BUS({ctl_clk, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
.VGA_R(r_out),
.VGA_G(g_out),
.VGA_B(b_out),
.VGA_HS(hs_emu),
.VGA_VS(vs_emu),
.VGA_DE(de),
.LED_USER(led_user),
.LED_POWER(led_power),
.LED_DISK(led_disk),
`ifndef LITE
.VIDEO_ARX(ARX),
.VIDEO_ARY(ARY),
`endif
.AUDIO_L(audio_l),
.AUDIO_R(audio_r),
.AUDIO_S(audio_s),
.TAPE_IN(0),
// SCK -> CLK
// MOSI -> CMD
// MISO <- DAT0
// Z -> DAT1
// Z -> DAT2
// CS -> DAT3
.SD_SCK(SDIO_CLK),
.SD_MOSI(SDIO_CMD),
.SD_MISO(SDIO_DAT[0]),
.SD_CS(SDIO_DAT[3]),
.DDRAM_CLK(ram_clk),
.DDRAM_ADDR(ram_address),
.DDRAM_BURSTCNT(ram_burstcount),
.DDRAM_BUSY(ram_waitrequest),
.DDRAM_DOUT(ram_readdata),
.DDRAM_DOUT_READY(ram_readdatavalid),
.DDRAM_RD(ram_read),
.DDRAM_DIN(ram_writedata),
.DDRAM_BE(ram_byteenable),
.DDRAM_WE(ram_write),
.SDRAM_DQ(SDRAM_DQ),
.SDRAM_A(SDRAM_A),
.SDRAM_DQML(SDRAM_DQML),
.SDRAM_DQMH(SDRAM_DQMH),
.SDRAM_BA(SDRAM_BA),
.SDRAM_nCS(SDRAM_nCS),
.SDRAM_nWE(SDRAM_nWE),
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_CLK(SDRAM_CLK),
.SDRAM_CKE(SDRAM_CKE)
);
endmodule
module sync_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule

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set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v

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sys/sysmem.sv Normal file
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`timescale 1 ps / 1 ps
module sysmem_lite
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
output ctl_clock,
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req // .warm_req
);
assign ctl_clock = clk_vip_clk;
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
wire clk_vip_clk;
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (0), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (0), // .burstcount
.f2h_sdram0_WAITREQUEST (), // .waitrequest
.f2h_sdram0_READDATA (), // .readdata
.f2h_sdram0_READDATAVALID (), // .readdatavalid
.f2h_sdram0_READ (0), // .read
.f2h_sdram0_WRITEDATA (0), // .writedata
.f2h_sdram0_BYTEENABLE (0), // .byteenable
.f2h_sdram0_WRITE (0), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
`timescale 1 ps / 1 ps
module sysmem
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input [27:0] ram_vip_address, // ram_vip.address
input [7:0] ram_vip_burstcount, // .burstcount
output ram_vip_waitrequest, // .waitrequest
output [127:0] ram_vip_readdata, // .readdata
output ram_vip_readdatavalid, // .readdatavalid
input ram_vip_read, // .read
input [127:0] ram_vip_writedata, // .writedata
input [15:0] ram_vip_byteenable, // .byteenable
input ram_vip_write, // .write
output clk_vip_clk, // clk_vip.clk
output reset_vip_reset // reset_vip.reset
);
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (ram_vip_readdata), // .readdata
.f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (ram_vip_read), // .read
.f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable
.f2h_sdram0_WRITE (ram_vip_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (reset_vip_reset), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
module sysmem_HPS_fpga_interfaces
(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// h2f_user0_clock
,output wire [1 - 1 : 0 ] h2f_user0_clk
// f2h_sdram0_data
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_sdram1_data
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
// f2h_sdram1_clock
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
// f2h_sdram2_data
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
);
wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_rfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.cfg_wfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.rd_ready_3({
1'b1 // 0:0
})
,.cmd_port_clk_2({
intermediate[28:28] // 0:0
})
,.rd_ready_2({
1'b1 // 0:0
})
,.cmd_port_clk_1({
intermediate[19:19] // 0:0
})
,.rd_ready_1({
1'b1 // 0:0
})
,.cmd_port_clk_0({
intermediate[10:10] // 0:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.wrack_ready_2({
1'b1 // 0:0
})
,.wrack_ready_1({
1'b1 // 0:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_ready_2({
intermediate[21:21] // 0:0
})
,.cmd_ready_1({
intermediate[12:12] // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.cfg_port_width({
12'b000000010110 // 11:0
})
,.rd_valid_3({
f2h_sdram2_READDATAVALID[0:0] // 0:0
})
,.rd_valid_2({
f2h_sdram1_READDATAVALID[0:0] // 0:0
})
,.rd_valid_1({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.rd_clk_3({
intermediate[22:22] // 0:0
})
,.rd_data_3({
f2h_sdram2_READDATA[63:0] // 63:0
})
,.rd_clk_2({
intermediate[13:13] // 0:0
})
,.rd_data_2({
f2h_sdram1_READDATA[63:0] // 63:0
})
,.rd_clk_1({
intermediate[3:3] // 0:0
})
,.rd_data_1({
f2h_sdram0_READDATA[127:64] // 63:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[63:0] // 63:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cmd_valid_2({
intermediate[26:26] // 0:0
})
,.cmd_valid_1({
intermediate[17:17] // 0:0
})
,.cmd_valid_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_data_3({
2'b00 // 89:88
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram2_WRITEDATA[63:0] // 63:0
})
,.wr_data_2({
2'b00 // 89:88
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram1_WRITEDATA[63:0] // 63:0
})
,.wr_data_1({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[127:64] // 63:0
})
,.cfg_cport_type({
12'b000000111111 // 11:0
})
,.wr_data_0({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[63:0] // 63:0
})
,.cfg_cport_wfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_clk_3({
intermediate[24:24] // 0:0
})
,.wr_clk_2({
intermediate[15:15] // 0:0
})
,.wr_clk_1({
intermediate[6:6] // 0:0
})
,.wr_clk_0({
intermediate[5:5] // 0:0
})
,.cmd_data_2({
18'b000000000000000000 // 59:42
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram2_ADDRESS[28:0] // 30:2
,intermediate[25:25] // 1:1
,intermediate[23:23] // 0:0
})
,.cmd_data_1({
18'b000000000000000000 // 59:42
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram1_ADDRESS[28:0] // 30:2
,intermediate[16:16] // 1:1
,intermediate[14:14] // 0:0
})
,.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,4'b0000 // 33:30
,f2h_sdram0_ADDRESS[27:0] // 29:2
,intermediate[7:7] // 1:1
,intermediate[4:4] // 0:0
})
);
endmodule

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module vga_out
(
input ypbpr_full,
input ypbpr_en,
input [23:0] din,
output [23:0] dout
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
wire [5:0] red = din[23:18];
wire [5:0] green = din[15:10];
wire [5:0] blue = din[7:2];
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8];
assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
endmodule

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//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
input scandoubler,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// High quality 2x scaling
input hq2x,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// Positive pulses.
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output reg VGA_DE
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.hb_in(HBlank),
.vb_in(VBlank),
.r_in(R),
.g_in(G),
.b_in(B),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
.vs_out(vs_sd),
.hb_out(hb_sd),
.vb_out(vb_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler ? R_sd : R);
wire [DWIDTH:0] gt = (scandoubler ? G_sd : G);
wire [DWIDTH:0] bt = (scandoubler ? B_sd : B);
generate
if(HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [7:0] r = rt;
wire [7:0] g = gt;
wire [7:0] b = bt;
end
endgenerate
wire hs = (scandoubler ? hs_sd : HSync);
wire vs = (scandoubler ? vs_sd : VSync);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~HBlank;
wire vde = scandoubler ? ~vb_sd : ~VBlank;
always @(posedge clk_sys) begin
reg old_hde;
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
VGA_R <= {1'b0, r[7:1]};
VGA_G <= {1'b0, g[7:1]};
VGA_B <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
VGA_R <= {2'b00, r[7:2]};
VGA_G <= {2'b00, g[7:2]};
VGA_B <= {2'b00, b[7:2]};
end
default: begin
VGA_R <= r;
VGA_G <= g;
VGA_B <= b;
end
endcase
VGA_VS <= vs;
VGA_HS <= hs;
old_hde <= hde;
if(~old_hde && hde && vde) VGA_DE <= 1;
if(old_hde && ~hde) VGA_DE <= 0;
end
endmodule

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set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name QIP_FILE sys/vip/synthesis/vip.qip

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module vip_config
(
input clk,
input reset,
input [7:0] ARX,
input [7:0] ARY,
output reg [8:0] address,
output reg write,
output reg [31:0] writedata,
input waitrequest
);
//Any input video resolution up to 1920x1080 is supported.
//Output video parameters.
//It's good to keep 1280x720@60 resolution among all cores as most compatible resolution.
parameter WIDTH = 1280;
parameter HEIGHT = 720;
parameter HFP = 110;
parameter HBP = 220;
parameter HS = 40;
parameter VFP = 5;
parameter VBP = 20;
parameter VS = 5;
reg [31:0] wcalc;
reg [31:0] hcalc;
wire [31:0] videow = (wcalc > WIDTH) ? WIDTH : wcalc;
wire [31:0] videoh = (hcalc > HEIGHT) ? HEIGHT : hcalc;
wire [31:0] posx = (WIDTH - videow)>>1;
wire [31:0] posy = (HEIGHT- videoh)>>1;
always @(posedge clk) begin
reg [7:0] state = 0;
reg [7:0] arx, ary;
integer timeout = 0;
if(reset || (!state && ((arx != ARX) || (ary != ARY)))) begin
arx <= ARX;
ary <= ARY;
timeout <= 0;
write <= 0;
end
else
if(timeout < 1000000)
begin
timeout <= timeout + 1;
write <= 0;
state <= 1;
end
else
if(~waitrequest && state)
begin
state <= state + 1'd1;
write <= 1;
case(state)
01: begin
wcalc <= (HEIGHT*arx)/ary;
hcalc <= (WIDTH*ary)/arx;
end
endcase
if(state&3) write <= 0;
else
case(state>>2)
//scaler
01: begin
address <= 'h003; //Output Width
writedata <= videow;
end
02: begin
address <= 'h004; //Output Height
writedata <= videoh;
end
03: begin
address <= 'h000; //Go
writedata <= 1;
end
//mixer
10: begin
address <= 'h083; //Bkg Width
writedata <= WIDTH;
end
11: begin
address <= 'h084; //Bkg Height
writedata <= HEIGHT;
end
12: begin
address <= 'h088; //Pos X
writedata <= posx;
end
13: begin
address <= 'h089; //Pos Y
writedata <= posy;
end
14: begin
address <= 'h08A; //Enable Video 0
writedata <= 1;
end
15: begin
address <= 'h080; //Go
writedata <= 1;
end
//video mode
20: begin
address <= 'h104; //Bank
writedata <= 0;
end
21: begin
address <= 'h105; //Progressive/Interlaced
writedata <= 0;
end
22: begin
address <= 'h106; //Active pixel count
writedata <= WIDTH;
end
23: begin
address <= 'h107; //Active line count
writedata <= HEIGHT;
end
24: begin
address <= 'h109; //Horizontal Front Porch
writedata <= HFP;
end
25: begin
address <= 'h10A; //Horizontal Sync Length
writedata <= HS;
end
26: begin
address <= 'h10B; //Horizontal Blanking (HFP+HBP+HSync)
writedata <= HFP+HBP+HS;
end
27: begin
address <= 'h10C; //Vertical Front Porch
writedata <= VFP;
end
28: begin
address <= 'h10D; //Vertical Sync Length
writedata <= VS;
end
29: begin
address <= 'h10E; //Vertical blanking (VFP+VBP+VSync)
writedata <= VFP+VBP+VS;
end
30: begin
address <= 'h11E; //Valid
writedata <= 1;
end
31: begin
address <= 'h100; //Go
writedata <= 1;
end
default: write <= 0;
endcase
end
end
endmodule

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-------------------------------------------------------------------------------
--
-- Apple ][ Timing logic
--
-- Stephen A. Edwards, sedwards@cs.columbia.edu
--
-- Taken more-or-less verbatim from the schematics in the
-- Apple ][ reference manual
--
-- This takes a 14.31818 MHz master clock and divides it down to generate
-- the various lower-frequency signals (e.g., 7M, phase 0, colorburst)
-- as well as horizontal and vertical blanking and sync signals for the video
-- and the video addresses.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timing_generator is
port (
CLK_14M : in std_logic; -- 14.31818 MHz master clock
CLK_7M : buffer std_logic := '0';
Q3 : buffer std_logic := '0'; -- 2 MHz signal in phase with PHI0
RAS_N : buffer std_logic := '0';
CAS_N : buffer std_logic := '0';
AX : buffer std_logic := '0';
PHI0 : buffer std_logic := '0'; -- 1.0 MHz processor clock
PRE_PHI0 : buffer std_logic := '0'; -- One 14M cycle before
COLOR_REF : buffer std_logic := '0'; -- 3.579545 MHz colorburst
TEXT_MODE : in std_logic;
PAGE2 : in std_logic;
HIRES : in std_logic;
VIDEO_ADDRESS : out unsigned(15 downto 0);
H0 : out std_logic;
VA : out std_logic; -- Character row address
VB : out std_logic;
VC : out std_logic;
V2 : out std_logic;
V4 : out std_logic;
HBL : buffer std_logic; -- Horizontal blanking
VBL : buffer std_logic; -- Vertical blanking
BLANK : out std_logic; -- Composite blanking
LDPS_N : out std_logic;
LD194 : out std_logic
);
end timing_generator;
architecture rtl of timing_generator is
signal H : unsigned(6 downto 0) := "0000000";
signal V : unsigned(8 downto 0) := "011111010";
signal COLOR_DELAY_N : std_logic;
begin
-- To generate the once-a-line hiccup: D1 pin 6
COLOR_DELAY_N <=
not (not COLOR_REF and (not AX and not CAS_N) and PHI0 and not H(6));
-- The DRAM signal generator
C2_74S195: process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if Q3 = '1' then -- shift
(Q3, CAS_N, AX, RAS_N) <=
unsigned'(CAS_N, AX, RAS_N, '0');
else -- load
(Q3, CAS_N, AX, RAS_N) <=
unsigned'(RAS_N, AX, COLOR_DELAY_N, AX);
end if;
end if;
end process;
-- The main clock signal generator
B1_74S175 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
COLOR_REF <= CLK_7M xor COLOR_REF;
CLK_7M <= not CLK_7M;
PHI0 <= PRE_PHI0;
if AX = '1' then
PRE_PHI0 <= not (Q3 xor PHI0); -- B1 pin 10
end if;
end if;
end process;
LDPS_N <= not (PHI0 and not AX and not CAS_N);
LD194 <= not (PHI0 and not AX and not CAS_N and not CLK_7M);
-- Four four-bit presettable binary counters
-- Seven-bit horizontal counter counts 0, 40, 41, ..., 7F (65 states)
-- Nine-bit vertical counter counts $FA .. $1FF (262 states)
D11D12D13D14_74LS161 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
-- True the cycle before the rising edge of LDPS_N: emulates
-- the effects of using LDPS_N as the clock for the video counters
if (PHI0 and not AX and ((Q3 and RAS_N) or
(not Q3 and COLOR_DELAY_N))) = '1' then
if H(6) = '0' then H <= "1000000";
else
H <= H + 1;
if H = "1111111" then
V <= V + 1;
if V = "111111111" then V <= "011111010"; end if;
end if;
end if;
end if;
end if;
end process;
H0 <= H(0);
VA <= V(0);
VB <= V(1);
VC <= V(2);
V2 <= V(5);
V4 <= V(7);
HBL <= not (H(5) or (H(3) and H(4)));
VBL <= V(6) and V(7);
BLANK <= HBL or VBL;
-- V_SYNC <= VBL and V(5) and not V(4) and not V(3) and
-- not V(2) and (H(4) or H(3) or H(5));
-- H_SYNC <= HBL and H(3) and not H(2);
-- SYNC <= not (V_SYNC or H_SYNC);
-- COLOR_BURST <= HBL and H(2) and H(3) and (COLOR_REF or TEXT_MODE);
-- Video address calculation
VIDEO_ADDRESS(2 downto 0) <= H(2 downto 0);
VIDEO_ADDRESS(6 downto 3) <= (not H(5) & V(6) & H(4) & H(3)) +
( V(7) & not H(5) & V(7) & '1') +
( "000" & V(6));
VIDEO_ADDRESS(9 downto 7) <= V(5 downto 3);
VIDEO_ADDRESS(14 downto 10) <=
( "00" & HBL & PAGE2 & not PAGE2) when HIRES = '0' else
(PAGE2 & not PAGE2 & V(2 downto 0));
VIDEO_ADDRESS(15) <= '0';
end rtl;

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-------------------------------------------------------------------------------
--
-- A VGA line-doubler for an Apple ][
--
-- Stephen A. Edwards, sedwards@cs.columbia.edu
--
--
-- FIXME: This is all wrong
--
-- The Apple ][ uses a 14.31818 MHz master clock. It outputs a new
-- horizontal line every 65 * 14 + 2 = 912 14M cycles. The extra two
-- are from the "extended cycle" used to keep the 3.579545 MHz
-- colorburst signal in sync. Of these, 40 * 14 = 560 are active video.
--
-- In graphics mode, the Apple effectively generates 140 four-bit pixels
-- output serially (i.e., with 3.579545 MHz pixel clock). In text mode,
-- it generates 280 one-bit pixels (i.e., with a 7.15909 MHz pixel clock).
--
-- We capture 140 four-bit nibbles for each line and interpret them in
-- one of the two modes. In graphics mode, each is displayed as a
-- single pixel of one of 16 colors. In text mode, each is displayed
-- as two black or white pixels.
--
-- The VGA display is nominally 640 X 480, but we use a 14.31818 MHz
-- dot clock. To stay in sync with the Apple, we generate a new line
-- every 912 / 2 = 456 14M cycles= 31.8 us, a 31.4 kHz horizontal
-- refresh rate. Of these, 280 will be active video.
--
-- One set of suggested VGA timings:
--
-- ______________________ ________
-- ________| VIDEO |________| VIDEO
-- |-C-|----------D-----------|-E-|
-- __ ______________________________ ___________
-- |_| |_|
-- |B|
-- |---------------A----------------|
--
-- A = 31.77 us Scanline time
-- B = 3.77 us Horizontal sync time
-- C = 1.89 us Back porch
-- D = 25.17 us Active video
-- E = 0.94 us Front porch
--
-- We use A = 456 / 14.31818 MHz = 31.84 us
-- B = 54 / 14.31818 MHz = 3.77 us
-- C = 106 / 14.31818 MHz = 7.40 us
-- D = 280 / 14.31818 MHz = 19.56 us
-- E = 16 / 14.31818 MHz = 1.12 us
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_controller is
port (
CLK_28M : in std_logic; -- 14.31818 MHz master clock
VIDEO : in std_logic; -- from the Apple video generator
COLOR_LINE : in std_logic;
SCREEN_MODE: in std_logic_vector(1 downto 0); -- 00: Color, 01: B&W, 10: Green, 11: Amber
HBL : in std_logic;
VBL : in std_logic;
LD194 : in std_logic;
VGA_CLK : out std_logic;
VGA_HS : out std_logic; -- Active low
VGA_VS : out std_logic; -- Active low
VGA_DE : out std_logic;
VGA_R : out unsigned(7 downto 0);
VGA_G : out unsigned(7 downto 0);
VGA_B : out unsigned(7 downto 0)
);
end vga_controller;
architecture rtl of vga_controller is
-- Double-ported RAM (one read port, one write port)
-- that holds two lines of 560 pixels
type line_memory_t is array (0 to 2047) of std_logic;
signal line_memory : line_memory_t;
-- RGB values from Linards Ticmanis,
-- http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.apple2/2005-09/msg00534.html
type basis_color is array(0 to 3) of unsigned(7 downto 0);
constant basis_r : basis_color := ( X"88", X"38", X"07", X"38" );
constant basis_g : basis_color := ( X"22", X"24", X"67", X"52" );
constant basis_b : basis_color := ( X"2C", X"A0", X"2C", X"07" );
signal ram_write_addr : unsigned(10 downto 0);
signal ram_we : std_logic;
signal ram_read_addr : unsigned(10 downto 0);
signal ram_data_out : std_logic;
signal shift_reg : unsigned(5 downto 0); -- Last six pixels
signal last_hbl : std_logic;
signal hcount : unsigned(10 downto 0);
signal hcount2 : unsigned(10 downto 0);
signal vcount : unsigned(5 downto 0);
signal even_line : std_logic;
signal hactive, hactive_early2, hactive_early1 : std_logic;
constant VGA_SCANLINE : integer := 456*2; -- Must be 456*2 (set by the Apple)
constant VGA_HSYNC : integer := 54 * 2;
constant VGA_BACK_PORCH : integer := 66 * 2;
constant VGA_ACTIVE : integer := 282 * 2;
constant VGA_FRONT_PORCH : integer := 54 * 2;
-- VGA_HSYNC + VGA_BACK_PORCH + VGA_ACTIVE + VGA_FRONT_PORCH = VGA_SCANLINE
constant VBL_TO_VSYNC : integer := 33;
constant VGA_VSYNC_LINES : integer := 3;
signal VGA_VS_I, VGA_HS_I : std_logic;
signal video_active : std_logic;
signal vbl_delayed, vbl_delayed2 : std_logic;
signal hbl_delayed : std_logic;
signal color_line_delayed_1, color_line_delayed_2 : std_logic;
begin
delay_hbl : process (CLK_28M)
begin
if rising_edge(CLK_28M) then
if LD194 = '0' then
hbl_delayed <= HBL;
end if;
end if;
end process;
hcount_vcount_control : process (CLK_28M)
begin
if rising_edge(CLK_28M) then
if last_hbl = '1' and hbl_delayed = '0' then -- Falling edge
color_line_delayed_2 <= color_line_delayed_1;
color_line_delayed_1 <= COLOR_LINE;
hcount <= (others => '0');
vbl_delayed2 <= vbl_delayed;
vbl_delayed <= VBL;
if vbl_delayed = '1' then
even_line <= '0';
vcount <= vcount + 1;
else
vcount <= (others => '0');
even_line <= not even_line;
end if;
else
hcount <= hcount + 1;
end if;
last_hbl <= hbl_delayed;
end if;
end process hcount_vcount_control;
hsync_gen : process (CLK_28M)
begin
if rising_edge(CLK_28M) then
if hcount = VGA_ACTIVE + VGA_FRONT_PORCH or
hcount = VGA_SCANLINE + VGA_ACTIVE + VGA_FRONT_PORCH then
VGA_HS_I <= '0';
elsif hcount = VGA_ACTIVE + VGA_FRONT_PORCH + VGA_HSYNC or
hcount = VGA_SCANLINE + VGA_ACTIVE + VGA_FRONT_PORCH + VGA_HSYNC then
VGA_HS_I <= '1';
end if;
hactive <= hactive_early1;
hactive_early1 <= hactive_early2;
if hcount = VGA_SCANLINE - 1 or
hcount = VGA_SCANLINE + VGA_SCANLINE - 1 then
hactive_early2 <= '1';
elsif hcount = VGA_ACTIVE or
hcount = VGA_ACTIVE + VGA_SCANLINE then
hactive_early2 <= '0';
end if;
end if;
end process hsync_gen;
VGA_HS <= VGA_HS_I;
vsync_gen : process (CLK_28M)
begin
if rising_edge(CLK_28M) then
if vcount = VBL_TO_VSYNC then
VGA_VS_I <= '0';
elsif vcount = VBL_TO_VSYNC + VGA_VSYNC_LINES then
VGA_VS_I <= '1';
end if;
end if;
end process vsync_gen;
VGA_VS <= VGA_VS_I;
hcount2 <= hcount - VGA_SCANLINE;
ram_read_addr <=
even_line & hcount(9 downto 0) when hcount < VGA_SCANLINE else
even_line & hcount2(9 downto 0);
shifter: process (CLK_28M)
begin
if rising_edge(CLK_28M) then
shift_reg <= ram_data_out & shift_reg(5 downto 1);
end if;
end process;
ram_write_addr <= (not even_line) & hcount(10 downto 1);
ram_we <= '1' when hcount(0) = '1' else '0';
video_active <= hactive and not vbl_delayed2;
pixel_generator: process (CLK_28M)
variable r, g, b : unsigned(7 downto 0);
begin
if rising_edge(CLK_28M) then
r := X"00";
g := X"00";
b := X"00";
-- alternate background for monochrome modes
case SCREEN_MODE is
when "00" =>
r := X"00"; g := X"00"; b := X"00"; -- color mode background
when "01" =>
r := X"00"; g := X"00"; b := X"00"; -- B&W mode background
when "10" =>
r := X"00"; g := X"0F"; b := X"01"; -- green mode background color
when "11" =>
r := X"20"; g := X"08"; b := X"01"; -- amber mode background color
end case;
if video_active = '1' then
if color_line_delayed_2 = '0' then -- Monochrome mode
if shift_reg(2) = '1' then
-- handle green/amber color modes
case SCREEN_MODE is
when "00" =>
r := X"FF"; g := X"FF"; b := X"FF"; -- white (color mode)
when "01" =>
r := X"FF"; g := X"FF"; b := X"FF"; -- white (B&W mode)
when "10" =>
r := X"00"; g := X"C0"; b := X"01"; -- green
when "11" =>
r := X"FF"; g := X"80"; b := X"01"; -- amber
end case;
end if;
elsif shift_reg(0) = shift_reg(4) and shift_reg(5) = shift_reg(1) then
-- Tint of adjacent pixels is consistent : display the color
if shift_reg(1) = '1' then
r := r + basis_r(to_integer(hcount + 1));
g := g + basis_g(to_integer(hcount + 1));
b := b + basis_b(to_integer(hcount + 1));
end if;
if shift_reg(2) = '1' then
r := r + basis_r(to_integer(hcount + 2));
g := g + basis_g(to_integer(hcount + 2));
b := b + basis_b(to_integer(hcount + 2));
end if;
if shift_reg(3) = '1' then
r := r + basis_r(to_integer(hcount + 3));
g := g + basis_g(to_integer(hcount + 3));
b := b + basis_b(to_integer(hcount + 3));
end if;
if shift_reg(4) = '1' then
r := r + basis_r(to_integer(hcount));
g := g + basis_g(to_integer(hcount));
b := b + basis_b(to_integer(hcount));
end if;
else
-- Tint is changing: display only black, gray, or white
case shift_reg(3 downto 2) is
when "11" => r := X"FF"; g := X"FF"; b := X"FF";
when "01" | "10" => r := X"80"; g := X"80"; b := X"80";
when others => r := X"00"; g := X"00"; b := X"00";
end case;
end if;
end if;
VGA_R <= r;
VGA_G <= g;
VGA_B <= b;
end if;
end process pixel_generator;
-- The two-port RAM that stores the line data
line_storage : process (CLK_28M)
begin
if rising_edge(CLK_28M) then
if ram_we = '1' then
line_memory(to_integer(ram_write_addr)) <= VIDEO;
end if;
ram_data_out <= line_memory(to_integer(ram_read_addr));
end if;
end process line_storage;
VGA_CLK <= CLK_28M;
VGA_DE <= video_active;
end rtl;

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-------------------------------------------------------------------------------
--
-- Apple ][ Video Generation Logic
--
-- Stephen A. Edwards, sedwards@cs.columbia.edu
--
-- This takes data from memory and various mode switches to produce the
-- serial one-bit video data stream.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_generator is
port (
CLK_14M : in std_logic; -- 14.31818 MHz master clock
CLK_7M : in std_logic;
AX : in std_logic;
CAS_N : in std_logic;
TEXT_MODE : in std_logic;
PAGE2 : in std_logic;
HIRES_MODE : in std_logic;
MIXED_MODE : in std_logic;
H0 : in std_logic;
VA : in std_logic;
VB : in std_logic;
VC : in std_logic;
V2 : in std_logic;
V4 : in std_logic;
BLANK : in std_logic;
DL : in unsigned(7 downto 0); -- Data from RAM
LDPS_N : in std_logic;
LD194 : in std_logic;
FLASH_CLK : in std_logic; -- Low-frequency flashing text clock
HIRES : out std_logic;
VIDEO : out std_logic;
COLOR_LINE : out std_logic
);
end video_generator;
architecture rtl of video_generator is
signal char_rom_addr : unsigned(8 downto 0);
signal char_rom_out : unsigned(4 downto 0);
signal text_shiftreg : unsigned(5 downto 0);
signal invert_character : std_logic;
signal text_pixel : std_logic; -- B2 p11
signal blank_delayed : std_logic;
signal video_sig : std_logic; -- output of B10 p5
signal graph_shiftreg : unsigned(7 downto 0);
signal graphics_time_1, graphics_time_2,
graphics_time_3 : std_logic; -- B5 p2, B8 p15, B8 p2
signal lores_time : std_logic; -- A11 p6
signal pixel_select : std_logic_vector(1 downto 0); -- A10 p14, A10 p15
signal hires_delayed : std_logic; -- A11 p9
begin
-----------------------------------------------------------------------------
--
-- Text Mode Circuitry
--
-- The character ROM drives a parallel-to-serial shift register
-- whose output is selectively inverted by inverted or flashing text
--
-----------------------------------------------------------------------------
char_rom_addr <= DL(5 downto 0) & VC & VB & VA;
thecharrom : entity work.character_rom
port map(
addr => char_rom_addr,
clk => CLK_14M, -- FIXME: a lower frequency?
dout => char_rom_out
);
-- Parallel-to-serial shifter for text mode
-- The Apple actually used LDPS_N as the clock, not 14M; this is equivalent
A3_74166: process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if CLK_7M = '0' then
if LDPS_N = '0' then -- load
text_shiftreg <= char_rom_out & "0";
else -- shift
text_shiftreg <= '0' & text_shiftreg(5 downto 1);
end if;
end if;
end if;
end process;
-- Latch and decoder for flashing/inverted text
-- Comprises part of B11, B13, and A10
flash_invert : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if LD194 = '0' then
invert_character <= not (DL(7) or (DL(6) and FLASH_CLK));
end if;
end if;
end process;
text_pixel <= text_shiftreg(0) xor invert_character;
-----------------------------------------------------------------------------
--
-- Lores and Hires Mode Circuitry
--
-- An eight-bit shift register that either shifts (hires mode) or rotates
-- the two nibbles (lores) followed by a mux that selects the video
-- data from the text mode display, the hires shift register (possibly
-- delayed by a 14M clock pulse), or one of the bits in the lores shift
-- register.
--
-----------------------------------------------------------------------------
-- Original Apple clocked this shift register on the rising edge of RAS_N
B5B8_74LS174 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if AX = '1' and CAS_N = '0' then
graphics_time_3 <= graphics_time_2;
graphics_time_2 <= graphics_time_1;
graphics_time_1 <= not (TEXT_MODE or (V2 and V4 and MIXED_MODE));
end if;
end if;
end process;
COLOR_LINE <= graphics_time_1;
HIRES <= HIRES_MODE and graphics_time_3; -- to address generator
lores_time <= not HIRES_MODE and graphics_time_3;
A8A10_74LS194 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if LD194 = '0' then
if lores_time = '1' then -- LORES mode
pixel_select <= VC & H0;
else -- HIRES mode
pixel_select <= graphics_time_1 & DL(7);
end if;
end if;
end if;
end process;
-- Shift hires pixels by one 14M cycle to get orange and blue
A11_74LS74 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
hires_delayed <= graph_shiftreg(0);
end if;
end process;
-- A pair of four-bit universal shift registers that either
-- shift the whole byte (hires mode) or rotate the two nibbles (lores mode)
B4B9_74LS194 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if LD194 = '0' then
graph_shiftreg <= DL;
else
if lores_time = '1' then -- LORES configuration
graph_shiftreg <= graph_shiftreg(4) & graph_shiftreg(7 downto 5) &
graph_shiftreg(0) & graph_shiftreg(3 downto 1);
else -- HIRES configuration
if CLK_7M = '0' then
graph_shiftreg <= graph_shiftreg(4) & graph_shiftreg(7 downto 1);
end if;
end if;
end if;
end if;
end process;
-- Synchronize BLANK to LD194
A10_74LS194: process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if LD194 = '0' then
blank_delayed <= BLANK;
end if;
end if;
end process;
-- Video output mux and flip-flop
A9B10_74LS151 : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
if blank_delayed = '0' then
if lores_time = '1' then -- LORES mode
case pixel_select is
when "00" => video_sig <= graph_shiftreg(0);
when "01" => video_sig <= graph_shiftreg(2);
when "10" => video_sig <= graph_shiftreg(4);
when "11" => video_sig <= graph_shiftreg(6);
when others => video_sig <= 'X';
end case;
else
if pixel_select(1) = '0' then -- TEXT mode
video_sig <= text_pixel;
else -- HIRES mode
if pixel_select(0) = '1' then
video_sig <= hires_delayed;
else
video_sig <= graph_shiftreg(0);
end if;
end if;
end if;
else
video_sig <= '0';
end if;
end if;
end process;
VIDEO <= video_sig;
end rtl;