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WIP: Create _ALT CPP macros for CPU emulation to do direct memaux access

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This commit is contained in:
tomcw
2025-03-08 21:23:02 +00:00
parent 2e1bc77ce3
commit 373d552e68
7 changed files with 357 additions and 150 deletions
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source/CPU.cpp
+36 -74
View File
@@ -379,6 +379,25 @@ static __forceinline void Fetch(BYTE& iOpcode, ULONG uExecutedCycles)
regs.pc++;
}
static __forceinline void Fetch_alt(BYTE& iOpcode, ULONG uExecutedCycles)
{
const USHORT PC = regs.pc;
#if defined(_DEBUG) && defined(DBG_HDD_ENTRYPOINT)
DebugHddEntrypoint(PC);
#endif
WORD addr = regs.pc;
iOpcode = _READ_ALT;
#ifdef USE_SPEECH_API
if ((PC == COUT1 || PC == BASICOUT) && g_Speech.IsEnabled() && !g_bFullSpeed)
CaptureCOUT();
#endif
regs.pc++;
}
//#define ENABLE_NMI_SUPPORT // Not used - so don't enable
static __forceinline bool NMI(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
{
@@ -462,156 +481,99 @@ static __forceinline bool IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn,
//===========================================================================
#define HEATMAP_X(address)
// 6502 & no debugger
#define READ _READ_WITH_IO_F8xx
#define WRITE(value) _WRITE_WITH_IO_F8xx(value)
#define HEATMAP_X(address)
#define POP _POP
#define PUSH(value) _PUSH(value)
#define IABS_NMOS _IABS_NMOS
#include "CPU/cpu6502.h" // MOS 6502
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_NMOS
//-------
// 6502 & no debugger & alt read/write support
#define CPU_ALT
#define READ _READ_ALT
#define WRITE(value) _WRITE_ALT(value)
#define POP _POP_ALT
#define PUSH(value) _PUSH_ALT(value)
#define IABS_NMOS _IABS_NMOS_ALT
#define Cpu6502 Cpu6502_altRW
#define Fetch Fetch_alt
#include "CPU/cpu6502.h" // MOS 6502
#undef Cpu6502
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_NMOS
#undef Fetch
//-------
// 65C02 & no debugger
#define READ _READ
#define WRITE(value) _WRITE(value)
#define POP _POP
#define PUSH(value) _PUSH(value)
#define IABS_CMOS _IABS_CMOS
#include "CPU/cpu65C02.h" // WDC 65C02
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_CMOS
//-------
// 65C02 & no debugger & alt read/write support
#define CPU_ALT
#define READ _READ_ALT
#define WRITE(value) _WRITE_ALT(value)
#define POP _POP_ALT
#define PUSH(value) _PUSH_ALT(value)
#define IABS_CMOS _IABS_CMOS_ALT
#define Cpu65C02 Cpu65C02_altRW
#define Fetch Fetch_alt
#include "CPU/cpu65C02.h" // WDC 65C02
#undef Cpu65C02
#undef Fetch
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_CMOS
#undef HEATMAP_X
//-----------------
#define HEATMAP_X(address) Heatmap_X(address)
#include "CPU/cpu_heatmap.inl"
// 6502 & debugger
#define READ Heatmap_ReadByte_With_IO_F8xx(addr, uExecutedCycles)
#define WRITE(value) Heatmap_WriteByte_With_IO_F8xx(addr, value, uExecutedCycles);
#define HEATMAP_X(address) Heatmap_X(address)
#define POP _POP
#define PUSH(value) _PUSH(value)
#define IABS_NMOS _IABS_NMOS
#include "CPU/cpu_heatmap.inl"
#define Cpu6502 Cpu6502_debug
#include "CPU/cpu6502.h" // MOS 6502
#undef Cpu6502
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_NMOS
//-------
// 6502 & debugger & alt read/write support
#define CPU_ALT
#define READ _READ_ALT
#define WRITE(value) _WRITE_ALT(value)
#define POP _POP_ALT
#define PUSH(value) _PUSH_ALT(value)
#define IABS_NMOS _IABS_NMOS_ALT
#define Cpu6502 Cpu6502_debug_altRW
#define Fetch Fetch_alt
#include "CPU/cpu6502.h" // MOS 6502
#undef Cpu6502
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_NMOS
#undef Fetch
//-------
// 65C02 & debugger
#define READ Heatmap_ReadByte(addr, uExecutedCycles)
#define WRITE(value) Heatmap_WriteByte(addr, value, uExecutedCycles);
#define POP _POP
#define PUSH(value) _PUSH(value)
#define IABS_CMOS _IABS_CMOS
#define Cpu65C02 Cpu65C02_debug
#include "CPU/cpu65C02.h" // WDC 65C02
#undef Cpu65C02
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_CMOS
//-------
// 65C02 & debugger & alt read/write support
#define CPU_ALT
#define READ _READ_ALT
#define WRITE(value) _WRITE_ALT(value)
#define POP _POP_ALT
#define PUSH(value) _PUSH_ALT(value)
#define IABS_CMOS _IABS_CMOS_ALT
#define Cpu65C02 Cpu65C02_debug_altRW
#define Fetch Fetch_alt
#include "CPU/cpu65C02.h" // WDC 65C02
#undef Cpu65C02
#undef Fetch
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_CMOS
#undef HEATMAP_X
//===========================================================================
source/CPU/cpu6502.h
+71
View File
@@ -21,6 +21,53 @@ along with AppleWin; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
// For regular or alternate (slow-path) CPU emulation
#ifndef CPU_ALT
//#define READ _READ
//#define WRITE(value) _WRITE(value)
#define POP _POP
#define PUSH(value) _PUSH(value)
#define ABS _ABS
#define IABSX _IABSX
#define ABSX_CONST _ABSX_CONST
#define ABSX_OPT _ABSX_OPT
#define ABSY_CONST _ABSY_CONST
#define ABSY_OPT _ABSY_OPT
#define IABS_CMOS _IABS_CMOS
#define IABS_NMOS _IABS_NMOS
#define INDX _INDX
#define IMM _IMM
#define INDX _INDX
#define INDY_CONST _INDY_CONST
#define INDY_OPT _INDY_OPT
#define IZPG _IZPG
#define ZPG _ZPG
#define ZPGX _ZPGX
#define ZPGY _ZPGY
#else
//#define READ _READ_ALT
//#define WRITE(value) _WRITE_ALT(value)
#define POP _POP_ALT
#define PUSH(value) _PUSH_ALT(value)
#define ABS _ABS_ALT
#define IABSX _IABSX_ALT
#define ABSX_CONST _ABSX_CONST_ALT
#define ABSX_OPT _ABSX_OPT_ALT
#define ABSY_CONST _ABSY_CONST_ALT
#define ABSY_OPT _ABSY_OPT_ALT
#define IABS_CMOS _IABS_CMOS_ALT
#define IABS_NMOS _IABS_NMOS_ALT
#define INDX _INDX_ALT
#define IMM _IMM_ALT
#define INDX _INDX_ALT
#define INDY_CONST _INDY_CONST_ALT
#define INDY_OPT _INDY_OPT_ALT
#define IZPG _IZPG_ALT
#define ZPG _ZPG_ALT
#define ZPGX _ZPGX_ALT
#define ZPGY _ZPGY_ALT
#endif
//===========================================================================
static uint32_t Cpu6502(uint32_t uTotalCycles, const bool bVideoUpdate)
@@ -339,3 +386,27 @@ static uint32_t Cpu6502(uint32_t uTotalCycles, const bool bVideoUpdate)
}
//===========================================================================
#undef CPU_ALT
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef ABS
#undef IABSX
#undef ABSX_CONST
#undef ABSX_OPT
#undef ABSY_CONST
#undef ABSY_OPT
#undef IABS_CMOS
#undef IABS_NMOS
#undef INDX
#undef IMM
#undef INDX
#undef INDY_CONST
#undef INDY_OPT
#undef IZPG
#undef ZPG
#undef ZPGX
#undef ZPGY
source/CPU/cpu65C02.h
+71
View File
@@ -21,6 +21,53 @@ along with AppleWin; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
// For regular or alternate (slow-path) CPU emulation
#ifndef CPU_ALT
//#define READ _READ
//#define WRITE(value) _WRITE(value)
#define POP _POP
#define PUSH(value) _PUSH(value)
#define ABS _ABS
#define IABSX _IABSX
#define ABSX_CONST _ABSX_CONST
#define ABSX_OPT _ABSX_OPT
#define ABSY_CONST _ABSY_CONST
#define ABSY_OPT _ABSY_OPT
#define IABS_CMOS _IABS_CMOS
#define IABS_NMOS _IABS_NMOS
#define INDX _INDX
#define IMM _IMM
#define INDX _INDX
#define INDY_CONST _INDY_CONST
#define INDY_OPT _INDY_OPT
#define IZPG _IZPG
#define ZPG _ZPG
#define ZPGX _ZPGX
#define ZPGY _ZPGY
#else
//#define READ _READ_ALT
//#define WRITE(value) _WRITE_ALT(value)
#define POP _POP_ALT
#define PUSH(value) _PUSH_ALT(value)
#define ABS _ABS_ALT
#define IABSX _IABSX_ALT
#define ABSX_CONST _ABSX_CONST_ALT
#define ABSX_OPT _ABSX_OPT_ALT
#define ABSY_CONST _ABSY_CONST_ALT
#define ABSY_OPT _ABSY_OPT_ALT
#define IABS_CMOS _IABS_CMOS_ALT
#define IABS_NMOS _IABS_NMOS_ALT
#define INDX _INDX_ALT
#define IMM _IMM_ALT
#define INDX _INDX_ALT
#define INDY_CONST _INDY_CONST_ALT
#define INDY_OPT _INDY_OPT_ALT
#define IZPG _IZPG_ALT
#define ZPG _ZPG_ALT
#define ZPGX _ZPGX_ALT
#define ZPGY _ZPGY_ALT
#endif
//===========================================================================
static uint32_t Cpu65C02(uint32_t uTotalCycles, const bool bVideoUpdate)
@@ -339,3 +386,27 @@ static uint32_t Cpu65C02(uint32_t uTotalCycles, const bool bVideoUpdate)
}
//===========================================================================
#undef CPU_ALT
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef ABS
#undef IABSX
#undef ABSX_CONST
#undef ABSX_OPT
#undef ABSY_CONST
#undef ABSY_OPT
#undef IABS_CMOS
#undef IABS_NMOS
#undef INDX
#undef IMM
#undef INDX
#undef INDY_CONST
#undef INDY_OPT
#undef IZPG
#undef ZPG
#undef ZPGX
#undef ZPGY
source/CPU/cpu_general.inl
+161 -46
View File
@@ -54,7 +54,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define _POP_ALT ( \
(memreadPageType[STACK_PAGE] == MEM_Normal) \
? _POP \
: (*(mem+TEXT_PAGE1_BEGIN+((regs.sp >= 0x1FF) ? (regs.sp = 0x100) : ++regs.sp))) /* memreadPageType[0x01] == MEM_Aux1K */ \
: (*(memaux+((regs.sp >= 0x1FF) ? (regs.sp = 0x100) : ++regs.sp))) /* memreadPageType[0x01] == MEM_Aux1K */ \
)
#define _PUSH(a) *(mem+regs.sp--) = (a); \
if (regs.sp < 0x100) \
@@ -77,7 +77,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
(memreadPageType[addr >> 8] == MEM_Normal) \
? *(mem+addr) \
: (memreadPageType[addr >> 8] == MEM_Aux1K) \
? *(mem+TEXT_PAGE1_BEGIN+(addr&(TEXT_PAGE1_SIZE-1))) \
? *(memaux+(addr&(TEXT_PAGE1_SIZE-1))) \
: (memreadPageType[addr >> 8] == MEM_IORead) \
? IORead[(addr >> 4) & 0xFF](regs.pc, addr, 0, 0, uExecutedCycles) \
: MemReadFloatingBus(uExecutedCycles) \
@@ -155,109 +155,224 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define CHECK_PAGE_CHANGE if ((base ^ addr) & 0xFF00) \
uExtraCycles=1;
#define READ_AUX1K_BYTE(pc) (*(memaux+(pc&(TEXT_PAGE1_SIZE-1))))
#define READ_AUX1K_WORD(pc) (READ_AUX1K_BYTE(pc) | (READ_AUX1K_BYTE(pc+1)<<8))
/****************************************************************************
*
* ADDRESSING MODE MACROS
*
***/
#define ABS addr = *(LPWORD)(mem+regs.pc); regs.pc += 2;
#define IABSX addr = *(LPWORD)(mem+(*(LPWORD)(mem+regs.pc))+(WORD)regs.x); regs.pc += 2;
#define _ABS addr = *(LPWORD)(mem+regs.pc); regs.pc += 2;
#define _ABS_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_ABS; \
} \
else { \
addr = READ_AUX1K_WORD(regs.pc); \
regs.pc += 2; \
}
#define _IABSX addr = *(LPWORD)(mem+(*(LPWORD)(mem+regs.pc))+(WORD)regs.x); regs.pc += 2;
#define _IABSX_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_IABSX; \
} \
else { \
addr = READ_AUX1K_WORD(READ_AUX1K_WORD(regs.pc)+regs.x);\
regs.pc += 2; \
}
// Not optimised for page-cross
#define _ABSX_CONST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2;
#define _ABSX_CONST_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_ABSX_CONST; \
} \
else { \
base = READ_AUX1K_WORD(regs.pc); \
addr = base + (WORD)regs.x; \
regs.pc += 2; \
}
// Optimised for page-cross
#define ABSX_OPT base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
#define _ABSX_OPT _ABSX_CONST; CHECK_PAGE_CHANGE;
#define _ABSX_OPT_ALT _ABSX_CONST_ALT; CHECK_PAGE_CHANGE;
// Not optimised for page-cross
#define ABSX_CONST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2;
#define _ABSY_CONST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2;
#define _ABSY_CONST_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_ABSY_CONST; \
} \
else { \
base = READ_AUX1K_WORD(regs.pc); \
addr = base + (WORD)regs.y; \
regs.pc += 2; \
}
// Optimised for page-cross
#define ABSY_OPT base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
// Not optimised for page-cross
#define ABSY_CONST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2;
#define _ABSY_OPT _ABSY_CONST; CHECK_PAGE_CHANGE;
#define _ABSY_OPT_ALT _ABSY_CONST_ALT; CHECK_PAGE_CHANGE;
// TODO Optimization Note (just for IABSCMOS): uExtraCycles = ((base & 0xFF) + 1) >> 8;
#define _IABS_CMOS base = *(LPWORD)(mem+regs.pc); \
addr = *(LPWORD)(mem+base); \
if ((base & 0xFF) == 0xFF) uExtraCycles=1; \
regs.pc += 2;
#define _IABS_CMOS_ALT base = *(LPWORD)(mem+regs.pc); \
if (memreadPageType[base >> 8] == MEM_Aux1K) \
base = TEXT_PAGE1_BEGIN + (base & (TEXT_PAGE1_SIZE-1)); \
addr = *(LPWORD)(mem+base); \
if ((base & 0xFF) == 0xFF) uExtraCycles=1; \
regs.pc += 2;
#define _IABS_CMOS_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_IABS_CMOS; \
} \
else { \
base = READ_AUX1K_WORD(regs.pc); \
base &= (TEXT_PAGE1_SIZE-1); \
addr = READ_AUX1K_WORD(base); \
if ((base & 0xFF) == 0xFF) uExtraCycles=1; \
regs.pc += 2; \
}
#define _IABS_NMOS base = *(LPWORD)(mem+regs.pc); \
if ((base & 0xFF) == 0xFF) \
addr = *(mem+base)+((WORD)*(mem+(base&0xFF00))<<8);\
else \
addr = *(LPWORD)(mem+base); \
regs.pc += 2;
#define _IABS_NMOS_ALT base = *(LPWORD)(mem+regs.pc); \
if (memreadPageType[base >> 8] == MEM_Aux1K) \
base = TEXT_PAGE1_BEGIN + (base & (TEXT_PAGE1_SIZE-1)); \
if ((base & 0xFF) == 0xFF) \
addr = *(mem+base)+((WORD)*(mem+(base&0xFF00))<<8); \
else \
addr = *(LPWORD)(mem+base); \
regs.pc += 2;
#define _IABS_NMOS_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_IABS_NMOS; \
} \
else { \
base = READ_AUX1K_WORD(regs.pc); \
base &= (TEXT_PAGE1_SIZE-1); \
addr = READ_AUX1K_WORD(base); \
if ((base & 0xFF) == 0xFF) \
addr = READ_AUX1K_BYTE(base) | (READ_AUX1K_BYTE(base&0xFF00)<<8); \
else \
addr = READ_AUX1K_WORD(base); \
regs.pc += 2; \
}
#define IMM addr = regs.pc++;
#define _IMM addr = regs.pc++;
#define _IMM_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_IMM; \
} \
else { \
addr = regs.pc++ & (TEXT_PAGE1_SIZE-1); \
}
#define INDX base = ((*(mem+regs.pc++))+regs.x) & 0xFF; \
#define _INDX base = ((*(mem+regs.pc++))+regs.x) & 0xFF; \
if (base == 0xFF) \
addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
addr = *(LPWORD)(mem+base);
#define _INDX_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_INDX; \
} \
else { \
base = (READ_AUX1K_BYTE(regs.pc++)+regs.x) & 0xFF; \
if (base == 0xFF) \
addr = READ_AUX1K_BYTE(0xFF) | (READ_AUX1K_BYTE(0x00)<<8); \
else \
addr = READ_AUX1K_WORD(base); \
}
// Optimised for page-cross
#define INDY_OPT if (*(mem+regs.pc) == 0xFF) /*incurs an extra cycle for page-crossing*/ \
base = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
base = *(LPWORD)(mem+*(mem+regs.pc)); \
regs.pc++; \
addr = base+(WORD)regs.y; \
CHECK_PAGE_CHANGE;
// Not optimised for page-cross
#define INDY_CONST if (*(mem+regs.pc) == 0xFF) /*no extra cycle for page-crossing*/ \
#define _INDY_CONST if (*(mem+regs.pc) == 0xFF) /*no extra cycle for page-crossing*/ \
base = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
base = *(LPWORD)(mem+*(mem+regs.pc)); \
regs.pc++; \
addr = base+(WORD)regs.y;
#define _INDY_CONST_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_INDY_CONST; \
} \
else { \
if (*(mem+regs.pc) == 0xFF) /*no extra cycle for page-crossing*/ \
base = READ_AUX1K_BYTE(0xFF) | (READ_AUX1K_BYTE(0x00)<<8); \
else \
base = READ_AUX1K_WORD(regs.pc); \
regs.pc++; \
addr = (base+(WORD)regs.y) & (TEXT_PAGE1_SIZE-1); \
}
#define IZPG base = *(mem+regs.pc++); \
// Optimised for page-cross
#define _INDY_OPT _INDY_CONST; CHECK_PAGE_CHANGE;
#define _INDY_OPT_ALT _INDY_CONST_ALT; CHECK_PAGE_CHANGE;
#define _IZPG base = *(mem+regs.pc++); \
if (base == 0xFF) \
addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
addr = *(LPWORD)(mem+base);
#define _IZPG_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_IZPG; \
} \
else { \
base = READ_AUX1K_BYTE(regs.pc++); \
if (base == 0xFF) \
addr = READ_AUX1K_BYTE(0xFF) | (READ_AUX1K_BYTE(0x00)<<8); \
else \
addr = READ_AUX1K_WORD(regs.pc); \
}
#define REL addr = (signed char)*(mem+regs.pc++);
// TODO Optimization Note:
// . Opcodes that generate zero-page addresses can't be accessing $C000..$CFFF
// so they could be paired with special READZP/WRITEZP macros (instead of READ/WRITE)
#define ZPG addr = *(mem+regs.pc++);
#define ZPGX addr = ((*(mem+regs.pc++))+regs.x) & 0xFF;
#define ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
#define _ZPG addr = *(mem+regs.pc++);
#define _ZPGX addr = ((*(mem+regs.pc++))+regs.x) & 0xFF;
#define _ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
#define _ZPG_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_ZPG; \
} \
else { \
addr = READ_AUX1K_BYTE(regs.pc++); \
}
#define _ZPGX_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_ZPGX; \
} \
else { \
addr = (READ_AUX1K_BYTE(regs.pc++) + regs.x) & 0xFF; \
}
#define _ZPGY_ALT \
if (memreadPageType[base >> 8] != MEM_Aux1K) { \
_ZPGY; \
} \
else { \
addr = (READ_AUX1K_BYTE(regs.pc++) + regs.y) & 0xFF; \
}
// Tidy 3 char addressing modes to keep the opcode table visually aligned, clean, and readable.
#undef asl
#undef idx
#undef imm
#undef izp
#undef lsr
#undef rel
#undef rol
#undef ror
#undef zpx
#undef zpy
#define asl ASLA // Arithmetic Shift Left
#define idx INDX
#define imm IMM
#define izp IZPG
#define lsr LSRA // Logical Shift Right
#define rel REL
#define rol ROLA // Rotate Left
#define ror RORA // Rotate Right
#undef idx
#undef imm
#undef izp
#undef zpx
#undef zpy
#define idx INDX
#define imm IMM
#define izp IZPG
#define zpx ZPGX
#define zpy ZPGY
source/Memory.cpp
+10 -12
View File
@@ -235,7 +235,7 @@ LPBYTE mem = NULL;
//
static LPBYTE memaux = NULL;
LPBYTE memaux = NULL;
static LPBYTE memmain = NULL;
LPBYTE memdirty = NULL;
@@ -1327,7 +1327,8 @@ static void UpdatePaging(BOOL initialize)
((*(memdirty+loop) & 1) || (loop <= 1)))
{
*(memdirty+loop) &= ~1;
memcpy(oldshadow[loop],mem+(loop << 8),256);
if (memreadPageType[loop] != MEM_Aux1K) // Writes to std80's 1KiB go directly to memaux (not via mem cache)
memcpy(oldshadow[loop],mem+(loop << 8),256);
}
memcpy(mem+(loop << 8),memshadow[loop],256);
@@ -1373,11 +1374,6 @@ static void UpdatePagingForAltRW(void)
if (SW_AUXREAD || (SW_80STORE && SW_PAGE2))
for (loop = 0x04; loop < 0x08; loop++)
memreadPageType[loop] = MEM_Normal;
#if 1 // Don't need to fix IABS_NMOS / IABS_CMOS (opcode $6C) with this...
if (SW_ALTZP)
memcpy(mem, memaux + 0x400, 0x100);
#endif
}
//
@@ -1414,27 +1410,29 @@ static void UpdatePagingForAltRW(void)
// Map all aux writes into the 1K memory
// . Need to combine with memwriteDirtyPage[], to that the right page is marked as dirty
const uint32_t kBase = 0x0000;
for (loop = 0x00; loop < 0x02; loop++)
if (SW_ALTZP)
memwrite[loop] = mem + TEXT_PAGE1_BEGIN + ((loop & 3) << 8);
memwrite[loop] = memaux + kBase + ((loop & 3) << 8);
for (loop = 0x02; loop < 0xC0; loop++)
if (SW_AUXWRITE)
memwrite[loop] = (memwrite[loop] - (loop << 8)) + TEXT_PAGE1_BEGIN + ((loop & 3) << 8);
memwrite[loop] = memaux + kBase + ((loop & 3) << 8);
for (loop = 0xD0; loop < 0x100; loop++)
if (SW_HIGHRAM && SW_ALTZP)
memwrite[loop] = mem + TEXT_PAGE1_BEGIN + ((loop & 3) << 8);
memwrite[loop] = memaux + kBase + ((loop & 3) << 8);
if (SW_80STORE && SW_PAGE2)
{
for (loop = 0x04; loop < 0x08; loop++)
memwrite[loop] = mem + TEXT_PAGE1_BEGIN + ((loop & 3) << 8);
memwrite[loop] = memaux + kBase + ((loop & 3) << 8);
if (SW_HIRES)
{
for (loop = 0x20; loop < 0x40; loop++)
memwrite[loop] = mem + TEXT_PAGE1_BEGIN + ((loop & 3) << 8);
memwrite[loop] = memaux + kBase + ((loop & 3) << 8);
}
}
}
source/Memory.h
+1
View File
@@ -47,6 +47,7 @@ extern LPBYTE memwrite[0x100];
extern BYTE memreadPageType[0x100];
extern BYTE memwriteDirtyPage[0x100];
extern LPBYTE mem;
extern LPBYTE memaux;
extern LPBYTE memdirty;
extern LPBYTE memVidHD;
test/TestCPU6502/TestCPU6502.cpp
+7 -18
View File
@@ -53,6 +53,11 @@ static __forceinline int Fetch(BYTE& iOpcode, ULONG uExecutedCycles)
return 1;
}
static __forceinline int Fetch_alt(BYTE& iOpcode, ULONG uExecutedCycles)
{
return Fetch(iOpcode, uExecutedCycles);
}
static __forceinline void DoIrqProfiling(uint32_t uCycles)
{
}
@@ -87,36 +92,20 @@ void NTSC_VideoUpdateCycles( long cycles6502 )
#include "../../source/CPU/cpu_general.inl"
#include "../../source/CPU/cpu_instructions.inl"
#define HEATMAP_X(pc)
#define READ _READ_WITH_IO_F8xx
#define WRITE(a) _WRITE_WITH_IO_F8xx(a)
#define HEATMAP_X(pc)
#define POP _POP
#define PUSH(a) _PUSH(a)
#define IABS_NMOS _IABS_NMOS_ALT
#include "../../source/CPU/cpu6502.h" // MOS 6502
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_NMOS
//-------
#define READ _READ
#define WRITE(a) _WRITE(a)
#define POP _POP
#define PUSH(a) _PUSH(a)
#define IABS_CMOS _IABS_CMOS_ALT
#include "../../source/CPU/cpu65C02.h" // WDC 65C02
#undef READ
#undef WRITE
#undef POP
#undef PUSH
#undef IABS_CMOS
#undef HEATMAP_X
//-------------------------------------