mirror of
https://github.com/AppleWin/AppleWin.git
synced 2024-05-31 22:41:34 +00:00
Merged master to savestate branch
This commit is contained in:
commit
5c16c3642a
|
@ -78,6 +78,7 @@
|
|||
<ClInclude Include="source\Pravets.h" />
|
||||
<ClInclude Include="source\Registry.h" />
|
||||
<ClInclude Include="source\Riff.h" />
|
||||
<ClInclude Include="source\SAM.h" />
|
||||
<ClInclude Include="source\SaveState.h" />
|
||||
<ClInclude Include="source\SerialComms.h" />
|
||||
<ClInclude Include="source\SoundCore.h" />
|
||||
|
@ -126,6 +127,7 @@
|
|||
<ClCompile Include="source\Configuration\PropertySheet.cpp" />
|
||||
<ClCompile Include="source\Configuration\PropertySheetHelper.cpp" />
|
||||
<ClCompile Include="source\CPU.cpp" />
|
||||
<ClCompile Include="source\SAM.cpp" />
|
||||
<ClCompile Include="source\Debugger\Debug.cpp" />
|
||||
<ClCompile Include="source\Debugger\Debugger_Assembler.cpp" />
|
||||
<ClCompile Include="source\Debugger\Debugger_Color.cpp" />
|
||||
|
|
|
@ -172,6 +172,9 @@
|
|||
<ClCompile Include="source\Pravets.cpp">
|
||||
<Filter>Source Files\Model</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="source\SAM.cpp">
|
||||
<Filter>Source Files\Emulator</Filter>
|
||||
</ClCompile>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="source\Applewin.h">
|
||||
|
@ -423,6 +426,9 @@
|
|||
<ClInclude Include="source\Pravets.h">
|
||||
<Filter>Source Files\Model</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="source\SAM.h">
|
||||
<Filter>Source Files\Emulator</Filter>
|
||||
</ClInclude>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Image Include="resource\Applewin.bmp">
|
||||
|
@ -591,9 +597,6 @@
|
|||
<Text Include="docs\FAQ.txt">
|
||||
<Filter>Docs</Filter>
|
||||
</Text>
|
||||
<Text Include="docs\History.txt">
|
||||
<Filter>Docs</Filter>
|
||||
</Text>
|
||||
<Text Include="docs\ToDo.txt">
|
||||
<Filter>Docs</Filter>
|
||||
</Text>
|
||||
|
@ -603,6 +606,7 @@
|
|||
<Text Include="docs\Wishlist.txt">
|
||||
<Filter>Docs</Filter>
|
||||
</Text>
|
||||
<Text Include="bin\History.txt" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Filter Include="Docs">
|
||||
|
|
|
@ -362,6 +362,7 @@
|
|||
<ClCompile Include="source\Tape.cpp" />
|
||||
<ClCompile Include="source\z80emu.cpp" />
|
||||
<ClCompile Include="source\CPU.cpp" />
|
||||
<ClCompile Include="source\SAM.cpp" />
|
||||
<ClCompile Include="source\Disk.cpp" />
|
||||
<ClCompile Include="source\DiskImage.cpp" />
|
||||
<ClCompile Include="source\DiskImageHelper.cpp" />
|
||||
|
@ -537,4 +538,4 @@
|
|||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
</ImportGroup>
|
||||
</Project>
|
||||
</Project>
|
||||
|
|
|
@ -1,9 +1,10 @@
|
|||
|
||||
Microsoft Visual Studio Solution File, Format Version 10.00
|
||||
# Visual C++ Express 2008
|
||||
# Visual Studio 2008
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Applewin", "ApplewinExpress9.00.vcproj", "{1DA0C491-B5F4-4EC8-B1D2-CF6BE635DADC}"
|
||||
ProjectSection(ProjectDependencies) = postProject
|
||||
{7935B998-C713-42AE-8F6D-9FF9080A1B1B} = {7935B998-C713-42AE-8F6D-9FF9080A1B1B}
|
||||
{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2} = {2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}
|
||||
{709278B8-C583-4BD8-90DE-4E4F35A3BD8B} = {709278B8-C583-4BD8-90DE-4E4F35A3BD8B}
|
||||
EndProjectSection
|
||||
EndProject
|
||||
|
@ -11,6 +12,8 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "zlib", "zlib\zlib-Express9.
|
|||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "zip_lib", "zip_lib\zip_lib.vcproj", "{709278B8-C583-4BD8-90DE-4E4F35A3BD8B}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "TestCPU6502", "test\TestCPU6502\TestCPU6502.vcproj", "{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Win32 = Debug|Win32
|
||||
|
@ -29,6 +32,10 @@ Global
|
|||
{709278B8-C583-4BD8-90DE-4E4F35A3BD8B}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{709278B8-C583-4BD8-90DE-4E4F35A3BD8B}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{709278B8-C583-4BD8-90DE-4E4F35A3BD8B}.Release|Win32.Build.0 = Release|Win32
|
||||
{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}.Release|Win32.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
|
|
|
@ -26,6 +26,8 @@
|
|||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
Description="Performing unit-test: TestCPU6502"
|
||||
CommandLine=".\Release\TestCPU6502.exe"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
|
@ -130,6 +132,8 @@
|
|||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
Description="Performing unit-test: TestCPU6502"
|
||||
CommandLine=".\Debug\TestCPU6502.exe"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
|
@ -686,6 +690,14 @@
|
|||
RelativePath=".\source\Riff.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\source\SAM.cpp"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\source\SAM.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\source\SaveState.cpp"
|
||||
>
|
||||
|
|
BIN
Disks/SAM Slot 5.dsk
Normal file
BIN
Disks/SAM Slot 5.dsk
Normal file
Binary file not shown.
|
@ -9,6 +9,12 @@ https://github.com/AppleWin/AppleWin/issues/new
|
|||
Tom Charlesworth
|
||||
|
||||
|
||||
1.25.0.4 - 23 Apr 2015
|
||||
----------------------
|
||||
Fixes:
|
||||
. [Bug #276] -d1 command line argument caused AppleWin to quickly exit.
|
||||
|
||||
|
||||
1.25.0.3 - 8 Sep 2014
|
||||
---------------------
|
||||
Note: This is the last planned version to support Win98/ME.
|
||||
|
|
|
@ -1,4 +1,8 @@
|
|||
/*
|
||||
.12 Fixed: [PVS-Studio] Fixed false positive of buffer overflow with MIP_RANDOM
|
||||
.11 Fixed: [PVS-Studio] Fixed missing call to sprintf() in ConfigSave_PrepareHeader()
|
||||
.10 Fixed: [PVS-Studio] Fixed no-op in _6502_GetStackReturnAddress()
|
||||
.9 Added: BLOAD now recognizes the extensions .hgr or .hgr2 to load to $2000, or $4000 respectfully
|
||||
.8 Fixed: Showing/hiding the address and/or opcodes will show long symbolic targets without overflowing into the register info pane Bug #227
|
||||
.7 Fixed: ASC #:# with string containing null byte wouldn't show rest of string
|
||||
.6 Added: Print-Screen when in debugger will copy the debugger window as text
|
||||
|
|
|
@ -154,10 +154,11 @@ BEGIN
|
|||
CONTROL "Slider1",IDC_SPKR_VOLUME,"msctls_trackbar32",TBS_AUTOTICKS | TBS_VERT | TBS_BOTH | WS_TABSTOP,13,47,28,60
|
||||
LTEXT "&Mockingboard:",IDC_STATIC,49,39,51,8
|
||||
CONTROL "Slider1",IDC_MB_VOLUME,"msctls_trackbar32",TBS_AUTOTICKS | TBS_VERT | TBS_BOTH | WS_TABSTOP,59,47,25,60
|
||||
GROUPBOX "Sound Cards",IDC_STATIC,6,122,197,61
|
||||
GROUPBOX "Sound Cards",IDC_STATIC,6,122,197,64
|
||||
CONTROL "Mockingboards (in slots 4 && 5)",IDC_MB_ENABLE,"Button",BS_AUTORADIOBUTTON,10,136,142,8
|
||||
CONTROL "Phasor (in slot 4)",IDC_PHASOR_ENABLE,"Button",BS_AUTORADIOBUTTON,10,149,92,10
|
||||
CONTROL "No sound cards",IDC_SOUNDCARD_DISABLE,"Button",BS_AUTORADIOBUTTON,10,163,78,10
|
||||
CONTROL "SAM/DAC (in slot 5)",IDC_SAM_ENABLE,"Button",BS_AUTORADIOBUTTON,10,162,95,10
|
||||
CONTROL "No sound cards",IDC_SOUNDCARD_DISABLE,"Button",BS_AUTORADIOBUTTON,10,175,78,10
|
||||
END
|
||||
|
||||
IDD_PROPPAGE_DISK DIALOGEX 0, 0, 211, 188
|
||||
|
@ -249,8 +250,8 @@ DISK_ICON ICON "DISK.ICO"
|
|||
//
|
||||
|
||||
VS_VERSION_INFO VERSIONINFO
|
||||
FILEVERSION 1,25,0,3
|
||||
PRODUCTVERSION 1,25,0,3
|
||||
FILEVERSION 1,25,0,4
|
||||
PRODUCTVERSION 1,25,0,4
|
||||
FILEFLAGSMASK 0x3fL
|
||||
#ifdef _DEBUG
|
||||
FILEFLAGS 0x1L
|
||||
|
@ -268,12 +269,12 @@ BEGIN
|
|||
VALUE "Comments", "https://github.com/AppleWin"
|
||||
VALUE "CompanyName", "AppleWin"
|
||||
VALUE "FileDescription", "Apple //e Emulator for Windows"
|
||||
VALUE "FileVersion", "1, 25, 0, 3"
|
||||
VALUE "FileVersion", "1, 25, 0, 4"
|
||||
VALUE "InternalName", "APPLEWIN"
|
||||
VALUE "LegalCopyright", " 1994-2014 Michael O'Brien, Oliver Schmidt, Tom Charlesworth, Michael Pohoreski, Nick Westgate, Linards Ticmanis"
|
||||
VALUE "LegalCopyright", " 1994-2015 Michael O'Brien, Oliver Schmidt, Tom Charlesworth, Michael Pohoreski, Nick Westgate, Linards Ticmanis"
|
||||
VALUE "OriginalFilename", "APPLEWIN.EXE"
|
||||
VALUE "ProductName", "Apple //e Emulator"
|
||||
VALUE "ProductVersion", "1, 25, 0, 3"
|
||||
VALUE "ProductVersion", "1, 25, 0, 4"
|
||||
END
|
||||
END
|
||||
BLOCK "VarFileInfo"
|
||||
|
|
|
@ -67,36 +67,39 @@
|
|||
#define IDC_SPIN_XTRIM 1026
|
||||
#define IDC_SPIN_YTRIM 1027
|
||||
#define IDC_PHASOR_ENABLE 1029
|
||||
#define IDC_SOUNDCARD_DISABLE 1030
|
||||
#define IDC_TFE_SETTINGS_ENABLE_T 1031
|
||||
#define IDC_TFE_SETTINGS_ENABLE 1032
|
||||
#define IDC_TFE_SETTINGS_INTERFACE_T 1033
|
||||
#define IDC_TFE_SETTINGS_INTERFACE 1034
|
||||
#define IDC_TFE_SETTINGS_INTERFACE_NAME 1035
|
||||
#define IDC_TFE_SETTINGS_INTERFACE_DESC 1036
|
||||
#define IDS_TFE_CAPTION 1037
|
||||
#define IDS_TFE_ETHERNET 1038
|
||||
#define IDS_TFE_INTERFACE 1039
|
||||
#define IDS_OK 1040
|
||||
#define IDS_CANCEL 1041
|
||||
#define IDC_ETHERNET 1042
|
||||
#define IDC_SCROLLLOCK_TOGGLE 1043
|
||||
#define IDC_MOUSE_IN_SLOT4 1044
|
||||
#define IDC_THE_FREEZES_F8_ROM_FW 1045
|
||||
#define IDC_MOUSE_CROSSHAIR 1046
|
||||
#define IDC_CLONETYPE 1047
|
||||
#define IDC_MOUSE_RESTRICT_TO_WINDOW 1048
|
||||
#define IDC_CIDERPRESS_BROWSE 1049
|
||||
#define IDC_CIDERPRESS_FILENAME 1050
|
||||
#define IDC_CPM_CONFIG 1051
|
||||
#define IDC_DUMPTOPRINTER 1052
|
||||
#define IDC_PRINTER_DUMP_FILENAME 1053
|
||||
#define IDC_PRINTER_DUMP_FILENAME_BROWSE 1054
|
||||
#define IDC_PRINTER_CONVERT_ENCODING 1055
|
||||
#define IDC_PRINTER_FILTER_UNPRINTABLE 1056
|
||||
#define IDC_PRINTER_APPEND 1057
|
||||
#define IDC_SPIN_PRINTER_IDLE 1058
|
||||
#define IDC_CHECK_HALF_SCAN_LINES 1059
|
||||
#define IDC_SAM_ENABLE 1030
|
||||
#define IDC_SOUNDCARD_DISABLE 1031
|
||||
|
||||
#define IDC_TFE_SETTINGS_ENABLE_T 1032
|
||||
#define IDC_TFE_SETTINGS_ENABLE 1033
|
||||
#define IDC_TFE_SETTINGS_INTERFACE_T 1034
|
||||
#define IDC_TFE_SETTINGS_INTERFACE 1035
|
||||
#define IDC_TFE_SETTINGS_INTERFACE_NAME 1036
|
||||
#define IDC_TFE_SETTINGS_INTERFACE_DESC 1037
|
||||
#define IDS_TFE_CAPTION 1038
|
||||
#define IDS_TFE_ETHERNET 1039
|
||||
#define IDS_TFE_INTERFACE 1040
|
||||
#define IDS_OK 1041
|
||||
#define IDS_CANCEL 1042
|
||||
#define IDC_ETHERNET 1043
|
||||
#define IDC_SCROLLLOCK_TOGGLE 1044
|
||||
#define IDC_MOUSE_IN_SLOT4 1045
|
||||
#define IDC_THE_FREEZES_F8_ROM_FW 1046
|
||||
#define IDC_MOUSE_CROSSHAIR 1047
|
||||
#define IDC_CLONETYPE 1048
|
||||
#define IDC_MOUSE_RESTRICT_TO_WINDOW 1049
|
||||
#define IDC_CIDERPRESS_BROWSE 1050
|
||||
#define IDC_CIDERPRESS_FILENAME 1051
|
||||
#define IDC_CPM_CONFIG 1052
|
||||
#define IDC_DUMPTOPRINTER 1053
|
||||
#define IDC_PRINTER_DUMP_FILENAME 1054
|
||||
#define IDC_PRINTER_DUMP_FILENAME_BROWSE 1055
|
||||
#define IDC_PRINTER_CONVERT_ENCODING 1056
|
||||
#define IDC_PRINTER_FILTER_UNPRINTABLE 1057
|
||||
#define IDC_PRINTER_APPEND 1058
|
||||
#define IDC_SPIN_PRINTER_IDLE 1059
|
||||
|
||||
#define IDC_CHECK_HALF_SCAN_LINES 1060
|
||||
#define IDC_GPL_TEXT 1061
|
||||
#define IDC_GPL_BORDER 1063
|
||||
#define IDC_APPLEWIN_VERSION 1064
|
||||
|
|
|
@ -558,7 +558,7 @@ void SetCurrentImageDir(const char* pszImageDir)
|
|||
strcpy(g_sCurrentDir, pszImageDir);
|
||||
|
||||
int nLen = strlen( g_sCurrentDir );
|
||||
if( g_sCurrentDir[ nLen - 1 ] != '\\' )
|
||||
if ((nLen > 0) && (g_sCurrentDir[ nLen - 1 ] != '\\'))
|
||||
{
|
||||
g_sCurrentDir[ nLen + 0 ] = '\\';
|
||||
g_sCurrentDir[ nLen + 1 ] = 0;
|
||||
|
@ -744,6 +744,7 @@ static int DoDiskInsert(const int nDrive, LPCSTR szFileName)
|
|||
|
||||
int APIENTRY WinMain(HINSTANCE passinstance, HINSTANCE, LPSTR lpCmdLine, int)
|
||||
{
|
||||
bool bShutdown = false;
|
||||
bool bSetFullScreen = false;
|
||||
bool bBoot = false;
|
||||
LPSTR szImageName_drive1 = NULL;
|
||||
|
@ -1011,7 +1012,7 @@ int APIENTRY WinMain(HINSTANCE passinstance, HINSTANCE, LPSTR lpCmdLine, int)
|
|||
if (bShowAboutDlg)
|
||||
{
|
||||
if (!AboutDlg())
|
||||
PostMessage(g_hFrameWindow, WM_DESTROY, 0, 0); // Close everything down
|
||||
bShutdown = true; // Close everything down
|
||||
else
|
||||
RegSaveString(TEXT(REG_CONFIG), TEXT(REGVALUE_VERSION), 1, VERSIONSTRING); // Only save version after user accepts license
|
||||
}
|
||||
|
@ -1027,13 +1028,13 @@ int APIENTRY WinMain(HINSTANCE passinstance, HINSTANCE, LPSTR lpCmdLine, int)
|
|||
if (!bSysClkOK)
|
||||
{
|
||||
MessageBox(g_hFrameWindow, "DirectX failed to create SystemClock instance", TEXT("AppleWin Error"), MB_OK);
|
||||
PostMessage(g_hFrameWindow, WM_DESTROY, 0, 0); // Close everything down
|
||||
bShutdown = true;
|
||||
}
|
||||
|
||||
if (g_bCustomRomF8Failed)
|
||||
{
|
||||
MessageBox(g_hFrameWindow, "Failed to load custom F8 rom (not found or not exactly 2KB)", TEXT("AppleWin Error"), MB_OK);
|
||||
PostMessage(g_hFrameWindow, WM_DESTROY, 0, 0); // Close everything down
|
||||
bShutdown = true;
|
||||
}
|
||||
|
||||
tfe_init();
|
||||
|
@ -1042,16 +1043,24 @@ int APIENTRY WinMain(HINSTANCE passinstance, HINSTANCE, LPSTR lpCmdLine, int)
|
|||
Snapshot_Startup(); // Do this after everything has been init'ed
|
||||
LogFileOutput("Main: Snapshot_Startup()\n");
|
||||
|
||||
if (bSetFullScreen)
|
||||
if (bShutdown)
|
||||
{
|
||||
PostMessage(g_hFrameWindow, WM_USER_FULLSCREEN, 0, 0);
|
||||
bSetFullScreen = false;
|
||||
PostMessage(g_hFrameWindow, WM_DESTROY, 0, 0); // Close everything down
|
||||
// NB. If shutting down, then don't post any other messages (GH#286)
|
||||
}
|
||||
|
||||
if (bBoot)
|
||||
else
|
||||
{
|
||||
PostMessage(g_hFrameWindow, WM_USER_BOOT, 0, 0);
|
||||
bBoot = false;
|
||||
if (bSetFullScreen)
|
||||
{
|
||||
PostMessage(g_hFrameWindow, WM_USER_FULLSCREEN, 0, 0);
|
||||
bSetFullScreen = false;
|
||||
}
|
||||
|
||||
if (bBoot)
|
||||
{
|
||||
PostMessage(g_hFrameWindow, WM_USER_BOOT, 0, 0);
|
||||
bBoot = false;
|
||||
}
|
||||
}
|
||||
|
||||
// ENTER THE MAIN MESSAGE LOOP
|
||||
|
|
|
@ -63,7 +63,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
//
|
||||
// What about these:
|
||||
// . 65C02: STZ?, TRB?, TSB?
|
||||
// . Answer: TRB & TSB don't have affected adressing modes
|
||||
// . Answer: TRB & TSB don't have affected addressing modes
|
||||
// . STZ probably doesn't add a cycle since otherwise it would be slower than STA which doesn't make sense.
|
||||
//
|
||||
// NB. 'Zero-page indexed' opcodes wrap back to zero-page.
|
||||
|
|
|
@ -35,7 +35,6 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
|
|||
WORD val;
|
||||
AF_TO_EF
|
||||
ULONG uExecutedCycles = 0;
|
||||
BOOL bSlowerOnPagecross = 0; // Set if opcode writes to memory (eg. ASL, STA)
|
||||
WORD base;
|
||||
g_bDebugBreakpointHit = 0;
|
||||
|
||||
|
@ -50,269 +49,270 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
|
|||
}
|
||||
else
|
||||
{
|
||||
if (!Fetch(iOpcode, uExecutedCycles))
|
||||
break;
|
||||
if (!Fetch(iOpcode, uExecutedCycles))
|
||||
break;
|
||||
|
||||
#define $ INV // INV = Invalid -> Debugger Break
|
||||
switch (iOpcode)
|
||||
{
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: $ HLT CYC(2) break;
|
||||
case 0x03: $ idx ASO CYC(8) break;
|
||||
case 0x04: $ ZPG NOP CYC(3) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASLn CYC(5) break;
|
||||
case 0x07: $ ZPG ASO CYC(5) break; // invalid
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: $ IMM ANC CYC(2) break; // invald
|
||||
case 0x0C: $ abx NOP CYC(4) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASLn CYC(6) break;
|
||||
case 0x0F: $ ABS ASO CYC(6) break; // invalid
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: idy ORA CYC(5) break;
|
||||
case 0x12: $ HLT CYC(2) break;
|
||||
case 0x13: $ idy ASO CYC(8) break; // invalid
|
||||
case 0x14: $ zpx NOP CYC(4) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASLn CYC(6) break;
|
||||
case 0x17: $ zpx ASO CYC(6) break; // invalid
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: aby ORA CYC(4) break;
|
||||
case 0x1A: $ NOP CYC(2) break;
|
||||
case 0x1B: $ aby ASO CYC(7) break; // invalid
|
||||
case 0x1C: $ abx NOP CYC(4) break;
|
||||
case 0x1D: abx ORA CYC(4) break;
|
||||
case 0x1E: abx ASLn CYC(6) break;
|
||||
case 0x1F: $ abx ASO CYC(7) break; // invalid
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: $ HLT CYC(2) break;
|
||||
case 0x23: $ idx RLA CYC(8) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROLn CYC(5) break;
|
||||
case 0x27: $ ZPG RLA CYC(5) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: $ IMM ANC CYC(2) break; // invalid
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(2) break;
|
||||
case 0x2E: ABS ROLn CYC(6) break;
|
||||
case 0x2F: $ ABS RLA CYC(6) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: idy AND CYC(5) break;
|
||||
case 0x32: $ HLT CYC(2) break;
|
||||
case 0x33: $ idy RLA CYC(8) break; // invalid
|
||||
case 0x34: $ zpx NOP CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROLn CYC(6) break;
|
||||
case 0x37: $ zpx RLA CYC(6) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: aby AND CYC(4) break;
|
||||
case 0x3A: $ NOP CYC(2) break;
|
||||
case 0x3B: $ aby RLA CYC(7) break; // invalid
|
||||
case 0x3C: $ abx NOP CYC(4) break;
|
||||
case 0x3D: abx AND CYC(4) break;
|
||||
case 0x3E: abx ROLn CYC(6) break;
|
||||
case 0x3F: $ abx RLA CYC(7) break; // invalid
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: $ HLT CYC(2) break;
|
||||
case 0x43: $ idx LSE CYC(8) break; // invalid
|
||||
case 0x44: $ ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSRn CYC(5) break;
|
||||
case 0x47: $ ZPG LSE CYC(5) break; // invalid
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: $ IMM ALR CYC(2) break; // invalid
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSRn CYC(6) break;
|
||||
case 0x4F: $ ABS LSE CYC(6) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: idy EOR CYC(5) break;
|
||||
case 0x52: $ HLT CYC(2) break;
|
||||
case 0x53: $ idy LSE CYC(8) break;
|
||||
case 0x54: $ zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSRn CYC(6) break;
|
||||
case 0x57: $ zpx LSE CYC(6) break; // invalid
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: aby EOR CYC(4) break;
|
||||
case 0x5A: $ NOP CYC(2) break;
|
||||
case 0x5B: $ aby LSE CYC(7) break; // invalid
|
||||
case 0x5C: $ abx NOP CYC(4) break;
|
||||
case 0x5D: abx EOR CYC(4) break;
|
||||
case 0x5E: abx LSRn CYC(6) break;
|
||||
case 0x5F: $ abx LSE CYC(7) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADCn CYC(6) break;
|
||||
case 0x62: $ HLT CYC(2) break;
|
||||
case 0x63: $ idx RRA CYC(8) break; // invalid
|
||||
case 0x64: $ ZPG NOP CYC(3) break;
|
||||
case 0x65: ZPG ADCn CYC(3) break;
|
||||
case 0x66: ZPG RORn CYC(5) break;
|
||||
case 0x67: $ ZPG RRA CYC(5) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADCn CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: $ IMM ARR CYC(2) break; // invalid
|
||||
case 0x6C: IABSNMOS JMP CYC(6) break;
|
||||
case 0x6D: ABS ADCn CYC(4) break;
|
||||
case 0x6E: ABS RORn CYC(6) break;
|
||||
case 0x6F: $ ABS RRA CYC(6) break; // invalid
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: idy ADCn CYC(5) break;
|
||||
case 0x72: $ HLT CYC(2) break;
|
||||
case 0x73: $ idy RRA CYC(8) break; // invalid
|
||||
case 0x74: $ zpx NOP CYC(4) break;
|
||||
case 0x75: zpx ADCn CYC(4) break;
|
||||
case 0x76: zpx RORn CYC(6) break;
|
||||
case 0x77: $ zpx RRA CYC(6) break; // invalid
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: aby ADCn CYC(4) break;
|
||||
case 0x7A: $ NOP CYC(2) break;
|
||||
case 0x7B: $ aby RRA CYC(7) break; // invalid
|
||||
case 0x7C: $ abx NOP CYC(4) break;
|
||||
case 0x7D: abx ADCn CYC(4) break;
|
||||
case 0x7E: abx RORn CYC(6) break;
|
||||
case 0x7F: $ abx RRA CYC(7) break; // invalid
|
||||
case 0x80: $ IMM NOP CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: $ IMM NOP CYC(2) break;
|
||||
case 0x83: $ idx AXS CYC(6) break; // invalid
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: $ ZPG AXS CYC(3) break; // invalid
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: $ IMM NOP CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: $ IMM XAA CYC(2) break; // invalid
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: $ ABS AXS CYC(4) break; // invalid
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: idy STA CYC(6) break;
|
||||
case 0x92: $ HLT CYC(2) break;
|
||||
case 0x93: $ idy AXA CYC(6) break; // invalid
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: $ zpy AXS CYC(4) break; // invalid
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: aby STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: $ aby TAS CYC(5) break; // invalid
|
||||
case 0x9C: $ abx SAY CYC(5) break; // invalid
|
||||
case 0x9D: abx STA CYC(5) break;
|
||||
case 0x9E: $ aby XAS CYC(5) break;
|
||||
case 0x9F: $ aby AXA CYC(5) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: $ idx LAX CYC(6) break; // invalid
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: $ ZPG LAX CYC(3) break; // invalid
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: $ IMM OAL CYC(2) break; // invalid
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: $ ABS LAX CYC(4) break; // invalid
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: idy LDA CYC(5) break;
|
||||
case 0xB2: $ HLT CYC(2) break;
|
||||
case 0xB3: $ idy LAX CYC(5) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: $ zpy LAX CYC(4) break; // invalid
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: aby LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: $ aby LAS CYC(4) break; // invalid
|
||||
case 0xBC: abx LDY CYC(4) break;
|
||||
case 0xBD: abx LDA CYC(4) break;
|
||||
case 0xBE: aby LDX CYC(4) break;
|
||||
case 0xBF: $ aby LAX CYC(4) break; // invalid
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: $ IMM NOP CYC(2) break;
|
||||
case 0xC3: $ idx DCM CYC(8) break; // invalid
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DECn CYC(5) break;
|
||||
case 0xC7: $ ZPG DCM CYC(5) break; // invalid
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: $ IMM SAX CYC(2) break; // invalid
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DECn CYC(5) break;
|
||||
case 0xCF: $ ABS DCM CYC(6) break; // invalid
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: idy CMP CYC(5) break;
|
||||
case 0xD2: $ HLT CYC(2) break;
|
||||
case 0xD3: $ idy DCM CYC(8) break; // invalid
|
||||
case 0xD4: $ zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DECn CYC(6) break;
|
||||
case 0xD7: $ zpx DCM CYC(6) break; // invalid
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: aby CMP CYC(4) break;
|
||||
case 0xDA: $ NOP CYC(2) break;
|
||||
case 0xDB: $ aby DCM CYC(7) break; // invalid
|
||||
case 0xDC: $ abx NOP CYC(4) break;
|
||||
case 0xDD: abx CMP CYC(4) break;
|
||||
case 0xDE: abx DECn CYC(6) break;
|
||||
case 0xDF: $ abx DCM CYC(7) break; // invalid
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBCn CYC(6) break;
|
||||
case 0xE2: $ IMM NOP CYC(2) break;
|
||||
case 0xE3: $ idx INS CYC(8) break; // invalid
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBCn CYC(3) break;
|
||||
case 0xE6: ZPG INCn CYC(5) break;
|
||||
case 0xE7: $ ZPG INS CYC(5) break; // invalid
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBCn CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: $ IMM SBCn CYC(2) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBCn CYC(4) break;
|
||||
case 0xEE: ABS INCn CYC(6) break;
|
||||
case 0xEF: $ ABS INS CYC(6) break; // invalid
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: idy SBCn CYC(5) break;
|
||||
case 0xF2: $ HLT CYC(2) break;
|
||||
case 0xF3: $ idy INS CYC(8) break; // invalid
|
||||
case 0xF4: $ zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBCn CYC(4) break;
|
||||
case 0xF6: zpx INCn CYC(6) break;
|
||||
case 0xF7: $ zpx INS CYC(6) break; // invalid
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: aby SBCn CYC(4) break;
|
||||
case 0xFA: $ NOP CYC(2) break;
|
||||
case 0xFB: $ aby INS CYC(7) break;
|
||||
case 0xFC: $ abx NOP CYC(4) break;
|
||||
case 0xFD: abx SBCn CYC(4) break;
|
||||
case 0xFE: abx INCn CYC(6) break;
|
||||
case 0xFF: $ abx INS CYC(7) break;
|
||||
}
|
||||
switch (iOpcode)
|
||||
{
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: $ HLT CYC(2) break;
|
||||
case 0x03: $ idx ASO CYC(8) break;
|
||||
case 0x04: $ ZPG NOP CYC(3) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASLn CYC(5) break;
|
||||
case 0x07: $ ZPG ASO CYC(5) break;
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: $ IMM ANC CYC(2) break;
|
||||
case 0x0C: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASLn CYC(6) break;
|
||||
case 0x0F: $ ABS ASO CYC(6) break;
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: INDY_OPT ORA CYC(5) break;
|
||||
case 0x12: $ HLT CYC(2) break;
|
||||
case 0x13: $ INDY_CONST ASO CYC(8) break;
|
||||
case 0x14: $ zpx NOP CYC(4) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASLn CYC(6) break;
|
||||
case 0x17: $ zpx ASO CYC(6) break;
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: ABSY_OPT ORA CYC(4) break;
|
||||
case 0x1A: $ NOP CYC(2) break;
|
||||
case 0x1B: $ ABSY_CONST ASO CYC(7) break;
|
||||
case 0x1C: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0x1D: ABSX_OPT ORA CYC(4) break;
|
||||
case 0x1E: ABSX_CONST ASLn CYC(7) break;
|
||||
case 0x1F: $ ABSX_CONST ASO CYC(7) break;
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: $ HLT CYC(2) break;
|
||||
case 0x23: $ idx RLA CYC(8) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROLn CYC(5) break;
|
||||
case 0x27: $ ZPG RLA CYC(5) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: $ IMM ANC CYC(2) break;
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(4) break;
|
||||
case 0x2E: ABS ROLn CYC(6) break;
|
||||
case 0x2F: $ ABS RLA CYC(6) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: INDY_OPT AND CYC(5) break;
|
||||
case 0x32: $ HLT CYC(2) break;
|
||||
case 0x33: $ INDY_CONST RLA CYC(8) break;
|
||||
case 0x34: $ zpx NOP CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROLn CYC(6) break;
|
||||
case 0x37: $ zpx RLA CYC(6) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: ABSY_OPT AND CYC(4) break;
|
||||
case 0x3A: $ NOP CYC(2) break;
|
||||
case 0x3B: $ ABSY_CONST RLA CYC(7) break;
|
||||
case 0x3C: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0x3D: ABSX_OPT AND CYC(4) break;
|
||||
case 0x3E: ABSX_CONST ROLn CYC(6) break;
|
||||
case 0x3F: $ ABSX_CONST RLA CYC(7) break;
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: $ HLT CYC(2) break;
|
||||
case 0x43: $ idx LSE CYC(8) break;
|
||||
case 0x44: $ ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSRn CYC(5) break;
|
||||
case 0x47: $ ZPG LSE CYC(5) break;
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: $ IMM ALR CYC(2) break;
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSRn CYC(6) break;
|
||||
case 0x4F: $ ABS LSE CYC(6) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: INDY_OPT EOR CYC(5) break;
|
||||
case 0x52: $ HLT CYC(2) break;
|
||||
case 0x53: $ INDY_CONST LSE CYC(8) break;
|
||||
case 0x54: $ zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSRn CYC(6) break;
|
||||
case 0x57: $ zpx LSE CYC(6) break;
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: ABSY_OPT EOR CYC(4) break;
|
||||
case 0x5A: $ NOP CYC(2) break;
|
||||
case 0x5B: $ ABSY_CONST LSE CYC(7) break;
|
||||
case 0x5C: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0x5D: ABSX_OPT EOR CYC(4) break;
|
||||
case 0x5E: ABSX_CONST LSRn CYC(6) break;
|
||||
case 0x5F: $ ABSX_CONST LSE CYC(7) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADCn CYC(6) break;
|
||||
case 0x62: $ HLT CYC(2) break;
|
||||
case 0x63: $ idx RRA CYC(8) break;
|
||||
case 0x64: $ ZPG NOP CYC(3) break;
|
||||
case 0x65: ZPG ADCn CYC(3) break;
|
||||
case 0x66: ZPG RORn CYC(5) break;
|
||||
case 0x67: $ ZPG RRA CYC(5) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADCn CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: $ IMM ARR CYC(2) break;
|
||||
case 0x6C: IABS_NMOS JMP CYC(5) break; // GH#264
|
||||
case 0x6D: ABS ADCn CYC(4) break;
|
||||
case 0x6E: ABS RORn CYC(6) break;
|
||||
case 0x6F: $ ABS RRA CYC(6) break;
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: INDY_OPT ADCn CYC(5) break;
|
||||
case 0x72: $ HLT CYC(2) break;
|
||||
case 0x73: $ INDY_CONST RRA CYC(8) break;
|
||||
case 0x74: $ zpx NOP CYC(4) break;
|
||||
case 0x75: zpx ADCn CYC(4) break;
|
||||
case 0x76: zpx RORn CYC(6) break;
|
||||
case 0x77: $ zpx RRA CYC(6) break;
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: ABSY_OPT ADCn CYC(4) break;
|
||||
case 0x7A: $ NOP CYC(2) break;
|
||||
case 0x7B: $ ABSY_CONST RRA CYC(7) break;
|
||||
case 0x7C: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0x7D: ABSX_OPT ADCn CYC(4) break;
|
||||
case 0x7E: ABSX_CONST RORn CYC(6) break;
|
||||
case 0x7F: $ ABSX_CONST RRA CYC(7) break;
|
||||
case 0x80: $ IMM NOP CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: $ IMM NOP CYC(2) break;
|
||||
case 0x83: $ idx AXS CYC(6) break;
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: $ ZPG AXS CYC(3) break;
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: $ IMM NOP CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: $ IMM XAA CYC(2) break;
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: $ ABS AXS CYC(4) break;
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: INDY_CONST STA CYC(6) break;
|
||||
case 0x92: $ HLT CYC(2) break;
|
||||
case 0x93: $ INDY_CONST AXA CYC(6) break;
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: $ zpy AXS CYC(4) break;
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: ABSY_CONST STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: $ ABSY_CONST TAS CYC(5) break;
|
||||
case 0x9C: $ ABSX_CONST SAY CYC(5) break;
|
||||
case 0x9D: ABSX_CONST STA CYC(5) break;
|
||||
case 0x9E: $ ABSY_CONST XAS CYC(5) break;
|
||||
case 0x9F: $ ABSY_CONST AXA CYC(5) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: $ idx LAX CYC(6) break;
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: $ ZPG LAX CYC(3) break;
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: $ IMM OAL CYC(2) break;
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: $ ABS LAX CYC(4) break;
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: INDY_OPT LDA CYC(5) break;
|
||||
case 0xB2: $ HLT CYC(2) break;
|
||||
case 0xB3: $ INDY_OPT LAX CYC(5) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: $ zpy LAX CYC(4) break;
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: ABSY_OPT LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: $ ABSY_OPT LAS CYC(4) break;
|
||||
case 0xBC: ABSX_OPT LDY CYC(4) break;
|
||||
case 0xBD: ABSX_OPT LDA CYC(4) break;
|
||||
case 0xBE: ABSY_OPT LDX CYC(4) break;
|
||||
case 0xBF: $ ABSY_OPT LAX CYC(4) break;
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: $ IMM NOP CYC(2) break;
|
||||
case 0xC3: $ idx DCM CYC(8) break;
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DEC CYC(5) break;
|
||||
case 0xC7: $ ZPG DCM CYC(5) break;
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: $ IMM SAX CYC(2) break;
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DEC CYC(6) break;
|
||||
case 0xCF: $ ABS DCM CYC(6) break;
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: INDY_OPT CMP CYC(5) break;
|
||||
case 0xD2: $ HLT CYC(2) break;
|
||||
case 0xD3: $ INDY_CONST DCM CYC(8) break;
|
||||
case 0xD4: $ zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DEC CYC(6) break;
|
||||
case 0xD7: $ zpx DCM CYC(6) break;
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: ABSY_OPT CMP CYC(4) break;
|
||||
case 0xDA: $ NOP CYC(2) break;
|
||||
case 0xDB: $ ABSY_CONST DCM CYC(7) break;
|
||||
case 0xDC: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0xDD: ABSX_OPT CMP CYC(4) break;
|
||||
case 0xDE: ABSX_CONST DEC CYC(7) break;
|
||||
case 0xDF: $ ABSX_CONST DCM CYC(7) break;
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBCn CYC(6) break;
|
||||
case 0xE2: $ IMM NOP CYC(2) break;
|
||||
case 0xE3: $ idx INS CYC(8) break;
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBCn CYC(3) break;
|
||||
case 0xE6: ZPG INC CYC(5) break;
|
||||
case 0xE7: $ ZPG INS CYC(5) break;
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBCn CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: $ IMM SBCn CYC(2) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBCn CYC(4) break;
|
||||
case 0xEE: ABS INC CYC(6) break;
|
||||
case 0xEF: $ ABS INS CYC(6) break;
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: INDY_OPT SBCn CYC(5) break;
|
||||
case 0xF2: $ HLT CYC(2) break;
|
||||
case 0xF3: $ INDY_CONST INS CYC(8) break;
|
||||
case 0xF4: $ zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBCn CYC(4) break;
|
||||
case 0xF6: zpx INC CYC(6) break;
|
||||
case 0xF7: $ zpx INS CYC(6) break;
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: ABSY_OPT SBCn CYC(4) break;
|
||||
case 0xFA: $ NOP CYC(2) break;
|
||||
case 0xFB: $ ABSY_CONST INS CYC(7) break;
|
||||
case 0xFC: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0xFD: ABSX_OPT SBCn CYC(4) break;
|
||||
case 0xFE: ABSX_CONST INC CYC(7) break;
|
||||
case 0xFF: $ ABSX_CONST INS CYC(7) break;
|
||||
}
|
||||
#undef $
|
||||
}
|
||||
|
||||
CheckInterruptSources(uExecutedCycles);
|
||||
|
|
|
@ -38,7 +38,6 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
|
|||
WORD val;
|
||||
AF_TO_EF
|
||||
ULONG uExecutedCycles = 0;
|
||||
BOOL bSlowerOnPagecross = 0; // Set if opcode writes to memory (eg. ASL, STA)
|
||||
WORD base;
|
||||
g_bDebugBreakpointHit = 0;
|
||||
|
||||
|
@ -56,265 +55,265 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
|
|||
if (!Fetch(iOpcode, uExecutedCycles))
|
||||
break;
|
||||
|
||||
#define $ INV // INV = Invalid -> Debugger Break
|
||||
switch (iOpcode)
|
||||
{
|
||||
#define $ INV // INV = Invalid -> Debugger Break
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: $ IMM NOP CYC(2) break;
|
||||
case 0x03: $ NOP CYC(2) break;
|
||||
case 0x04: ZPG TSB CYC(5) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASLc CYC(5) break;
|
||||
case 0x07: $ NOP CYC(2) break;
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: $ NOP CYC(2) break;
|
||||
case 0x0C: ABS TSB CYC(6) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASLc CYC(6) break;
|
||||
case 0x0F: $ NOP CYC(2) break;
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: idy ORA CYC(5) break;
|
||||
case 0x12: izp ORA CYC(5) break;
|
||||
case 0x13: $ NOP CYC(2) break;
|
||||
case 0x14: ZPG TRB CYC(5) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASLc CYC(6) break;
|
||||
case 0x17: $ NOP CYC(2) break;
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: aby ORA CYC(4) break;
|
||||
case 0x1A: INA CYC(2) break;
|
||||
case 0x1B: $ NOP CYC(2) break;
|
||||
case 0x1C: ABS TRB CYC(6) break;
|
||||
case 0x1D: abx ORA CYC(4) break;
|
||||
case 0x1E: abx ASLc CYC(6) break;
|
||||
case 0x1F: $ NOP CYC(2) break;
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: $ IMM NOP CYC(2) break;
|
||||
case 0x23: $ NOP CYC(2) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROLc CYC(5) break;
|
||||
case 0x27: $ NOP CYC(2) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: $ NOP CYC(2) break;
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(2) break;
|
||||
case 0x2E: ABS ROLc CYC(6) break;
|
||||
case 0x2F: $ NOP CYC(2) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: idy AND CYC(5) break;
|
||||
case 0x32: izp AND CYC(5) break;
|
||||
case 0x33: $ NOP CYC(2) break;
|
||||
case 0x34: zpx BIT CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROLc CYC(6) break;
|
||||
case 0x37: $ NOP CYC(2) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: aby AND CYC(4) break;
|
||||
case 0x3A: DEA CYC(2) break;
|
||||
case 0x3B: $ NOP CYC(2) break;
|
||||
case 0x3C: abx BIT CYC(4) break;
|
||||
case 0x3D: abx AND CYC(4) break;
|
||||
case 0x3E: abx ROLc CYC(6) break;
|
||||
case 0x3F: $ NOP CYC(2) break;
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: $ IMM NOP CYC(2) break;
|
||||
case 0x43: $ NOP CYC(2) break;
|
||||
case 0x44: $ ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSRc CYC(5) break;
|
||||
case 0x47: $ NOP CYC(2) break;
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: $ NOP CYC(2) break;
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSRc CYC(6) break;
|
||||
case 0x4F: $ NOP CYC(2) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: idy EOR CYC(5) break;
|
||||
case 0x52: izp EOR CYC(5) break;
|
||||
case 0x53: $ NOP CYC(2) break;
|
||||
case 0x54: $ zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSRc CYC(6) break;
|
||||
case 0x57: $ NOP CYC(2) break;
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: aby EOR CYC(4) break;
|
||||
case 0x5A: PHY CYC(3) break;
|
||||
case 0x5B: $ NOP CYC(2) break;
|
||||
case 0x5C: $ abx NOP CYC(8) break;
|
||||
case 0x5D: abx EOR CYC(4) break;
|
||||
case 0x5E: abx LSRc CYC(6) break;
|
||||
case 0x5F: $ NOP CYC(2) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADCc CYC(6) break;
|
||||
case 0x62: $ IMM NOP CYC(2) break;
|
||||
case 0x63: $ NOP CYC(2) break;
|
||||
case 0x64: ZPG STZ CYC(3) break;
|
||||
case 0x65: ZPG ADCc CYC(3) break;
|
||||
case 0x66: ZPG RORc CYC(5) break;
|
||||
case 0x67: $ NOP CYC(2) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADCc CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: $ NOP CYC(2) break;
|
||||
case 0x6C: IABSCMOS JMP CYC(6) break;
|
||||
case 0x6D: ABS ADCc CYC(4) break;
|
||||
case 0x6E: ABS RORc CYC(6) break;
|
||||
case 0x6F: $ NOP CYC(2) break;
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: idy ADCc CYC(5) break;
|
||||
case 0x72: izp ADCc CYC(5) break;
|
||||
case 0x73: $ NOP CYC(2) break;
|
||||
case 0x74: zpx STZ CYC(4) break;
|
||||
case 0x75: zpx ADCc CYC(4) break;
|
||||
case 0x76: zpx RORc CYC(6) break;
|
||||
case 0x77: $ NOP CYC(2) break;
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: aby ADCc CYC(4) break;
|
||||
case 0x7A: PLY CYC(4) break;
|
||||
case 0x7B: $ NOP CYC(2) break;
|
||||
case 0x7C: IABSX JMP CYC(6) break; //
|
||||
case 0x7D: abx ADCc CYC(4) break;
|
||||
case 0x7E: abx RORc CYC(6) break;
|
||||
case 0x7F: $ NOP CYC(2) break;
|
||||
case 0x80: REL BRA CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: $ IMM NOP CYC(2) break;
|
||||
case 0x83: $ NOP CYC(2) break;
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: $ NOP CYC(2) break;
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: IMM BITI CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: $ NOP CYC(2) break;
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: $ NOP CYC(2) break;
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: idy STA CYC(6) break;
|
||||
case 0x92: izp STA CYC(5) break;
|
||||
case 0x93: $ NOP CYC(2) break;
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: $ NOP CYC(2) break;
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: aby STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: $ NOP CYC(2) break;
|
||||
case 0x9C: ABS STZ CYC(4) break;
|
||||
case 0x9D: abx STA CYC(5) break;
|
||||
case 0x9E: abx STZ CYC(5) break;
|
||||
case 0x9F: $ NOP CYC(2) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: $ NOP CYC(2) break;
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: $ NOP CYC(2) break;
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: $ NOP CYC(2) break;
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: $ NOP CYC(2) break;
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: idy LDA CYC(5) break;
|
||||
case 0xB2: izp LDA CYC(5) break;
|
||||
case 0xB3: $ NOP CYC(2) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: $ NOP CYC(2) break;
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: aby LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: $ NOP CYC(2) break;
|
||||
case 0xBC: abx LDY CYC(4) break;
|
||||
case 0xBD: abx LDA CYC(4) break;
|
||||
case 0xBE: aby LDX CYC(4) break;
|
||||
case 0xBF: $ NOP CYC(2) break;
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: $ IMM NOP CYC(2) break;
|
||||
case 0xC3: $ NOP CYC(2) break;
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DECc CYC(5) break;
|
||||
case 0xC7: $ NOP CYC(2) break;
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: $ NOP CYC(2) break;
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DECc CYC(5) break;
|
||||
case 0xCF: $ NOP CYC(2) break;
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: idy CMP CYC(5) break;
|
||||
case 0xD2: izp CMP CYC(5) break;
|
||||
case 0xD3: $ NOP CYC(2) break;
|
||||
case 0xD4: $ zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DECc CYC(6) break;
|
||||
case 0xD7: $ NOP CYC(2) break;
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: aby CMP CYC(4) break;
|
||||
case 0xDA: PHX CYC(3) break;
|
||||
case 0xDB: $ NOP CYC(2) break;
|
||||
case 0xDC: $ abx NOP CYC(4) break;
|
||||
case 0xDD: abx CMP CYC(4) break;
|
||||
case 0xDE: abx DECc CYC(6) break;
|
||||
case 0xDF: $ NOP CYC(2) break;
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBCc CYC(6) break;
|
||||
case 0xE2: $ IMM NOP CYC(2) break;
|
||||
case 0xE3: $ NOP CYC(2) break;
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBCc CYC(3) break;
|
||||
case 0xE6: ZPG INCc CYC(5) break;
|
||||
case 0xE7: $ NOP CYC(2) break;
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBCc CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: $ NOP CYC(2) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBCc CYC(4) break;
|
||||
case 0xEE: ABS INCc CYC(6) break;
|
||||
case 0xEF: $ NOP CYC(2) break;
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: idy SBCc CYC(5) break;
|
||||
case 0xF2: izp SBCc CYC(5) break;
|
||||
case 0xF3: $ NOP CYC(2) break;
|
||||
case 0xF4: $ zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBCc CYC(4) break;
|
||||
case 0xF6: zpx INCc CYC(6) break;
|
||||
case 0xF7: $ NOP CYC(2) break;
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: aby SBCc CYC(4) break;
|
||||
case 0xFA: PLX CYC(4) break;
|
||||
case 0xFB: $ NOP CYC(2) break;
|
||||
case 0xFC: $ abx NOP CYC(4) break;
|
||||
case 0xFD: abx SBCc CYC(4) break;
|
||||
case 0xFE: abx INCc CYC(6) break;
|
||||
case 0xFF: $ NOP CYC(2) break;
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: $ IMM NOP CYC(2) break;
|
||||
case 0x03: $ NOP CYC(1) break;
|
||||
case 0x04: ZPG TSB CYC(5) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASLc CYC(5) break;
|
||||
case 0x07: $ NOP CYC(1) break;
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: $ NOP CYC(1) break;
|
||||
case 0x0C: ABS TSB CYC(6) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASLc CYC(6) break;
|
||||
case 0x0F: $ NOP CYC(1) break;
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: INDY_OPT ORA CYC(5) break;
|
||||
case 0x12: izp ORA CYC(5) break;
|
||||
case 0x13: $ NOP CYC(1) break;
|
||||
case 0x14: ZPG TRB CYC(5) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASLc CYC(6) break;
|
||||
case 0x17: $ NOP CYC(1) break;
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: ABSY_OPT ORA CYC(4) break;
|
||||
case 0x1A: INA CYC(2) break;
|
||||
case 0x1B: $ NOP CYC(1) break;
|
||||
case 0x1C: ABS TRB CYC(6) break;
|
||||
case 0x1D: ABSX_OPT ORA CYC(4) break;
|
||||
case 0x1E: ABSX_OPT ASLc CYC(6) break;
|
||||
case 0x1F: $ NOP CYC(1) break;
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: $ IMM NOP CYC(2) break;
|
||||
case 0x23: $ NOP CYC(1) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROLc CYC(5) break;
|
||||
case 0x27: $ NOP CYC(1) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: $ NOP CYC(1) break;
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(4) break;
|
||||
case 0x2E: ABS ROLc CYC(6) break;
|
||||
case 0x2F: $ NOP CYC(1) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: INDY_OPT AND CYC(5) break;
|
||||
case 0x32: izp AND CYC(5) break;
|
||||
case 0x33: $ NOP CYC(1) break;
|
||||
case 0x34: zpx BIT CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROLc CYC(6) break;
|
||||
case 0x37: $ NOP CYC(1) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: ABSY_OPT AND CYC(4) break;
|
||||
case 0x3A: DEA CYC(2) break;
|
||||
case 0x3B: $ NOP CYC(1) break;
|
||||
case 0x3C: ABSX_OPT BIT CYC(4) break;
|
||||
case 0x3D: ABSX_OPT AND CYC(4) break;
|
||||
case 0x3E: ABSX_OPT ROLc CYC(6) break;
|
||||
case 0x3F: $ NOP CYC(1) break;
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: $ IMM NOP CYC(2) break;
|
||||
case 0x43: $ NOP CYC(1) break;
|
||||
case 0x44: $ ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSRc CYC(5) break;
|
||||
case 0x47: $ NOP CYC(1) break;
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: $ NOP CYC(1) break;
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSRc CYC(6) break;
|
||||
case 0x4F: $ NOP CYC(1) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: INDY_OPT EOR CYC(5) break;
|
||||
case 0x52: izp EOR CYC(5) break;
|
||||
case 0x53: $ NOP CYC(1) break;
|
||||
case 0x54: $ zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSRc CYC(6) break;
|
||||
case 0x57: $ NOP CYC(1) break;
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: ABSY_OPT EOR CYC(4) break;
|
||||
case 0x5A: PHY CYC(3) break;
|
||||
case 0x5B: $ NOP CYC(1) break;
|
||||
case 0x5C: $ ABS NOP CYC(8) break;
|
||||
case 0x5D: ABSX_OPT EOR CYC(4) break;
|
||||
case 0x5E: ABSX_OPT LSRc CYC(6) break;
|
||||
case 0x5F: $ NOP CYC(1) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADCc CYC(6) break;
|
||||
case 0x62: $ IMM NOP CYC(2) break;
|
||||
case 0x63: $ NOP CYC(1) break;
|
||||
case 0x64: ZPG STZ CYC(3) break;
|
||||
case 0x65: ZPG ADCc CYC(3) break;
|
||||
case 0x66: ZPG RORc CYC(5) break;
|
||||
case 0x67: $ NOP CYC(1) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADCc CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: $ NOP CYC(1) break;
|
||||
case 0x6C: IABS_CMOS JMP CYC(6) break;
|
||||
case 0x6D: ABS ADCc CYC(4) break;
|
||||
case 0x6E: ABS RORc CYC(6) break;
|
||||
case 0x6F: $ NOP CYC(1) break;
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: INDY_OPT ADCc CYC(5) break;
|
||||
case 0x72: izp ADCc CYC(5) break;
|
||||
case 0x73: $ NOP CYC(1) break;
|
||||
case 0x74: zpx STZ CYC(4) break;
|
||||
case 0x75: zpx ADCc CYC(4) break;
|
||||
case 0x76: zpx RORc CYC(6) break;
|
||||
case 0x77: $ NOP CYC(1) break;
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: ABSY_OPT ADCc CYC(4) break;
|
||||
case 0x7A: PLY CYC(4) break;
|
||||
case 0x7B: $ NOP CYC(1) break;
|
||||
case 0x7C: IABSX JMP CYC(6) break;
|
||||
case 0x7D: ABSX_OPT ADCc CYC(4) break;
|
||||
case 0x7E: ABSX_OPT RORc CYC(6) break;
|
||||
case 0x7F: $ NOP CYC(1) break;
|
||||
case 0x80: REL BRA CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: $ IMM NOP CYC(2) break;
|
||||
case 0x83: $ NOP CYC(1) break;
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: $ NOP CYC(1) break;
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: IMM BITI CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: $ NOP CYC(1) break;
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: $ NOP CYC(1) break;
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: INDY_CONST STA CYC(6) break;
|
||||
case 0x92: izp STA CYC(5) break;
|
||||
case 0x93: $ NOP CYC(1) break;
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: $ NOP CYC(1) break;
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: ABSY_CONST STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: $ NOP CYC(1) break;
|
||||
case 0x9C: ABS STZ CYC(4) break;
|
||||
case 0x9D: ABSX_CONST STA CYC(5) break;
|
||||
case 0x9E: ABSX_CONST STZ CYC(5) break;
|
||||
case 0x9F: $ NOP CYC(1) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: $ NOP CYC(1) break;
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: $ NOP CYC(1) break;
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: $ NOP CYC(1) break;
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: $ NOP CYC(1) break;
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: INDY_OPT LDA CYC(5) break;
|
||||
case 0xB2: izp LDA CYC(5) break;
|
||||
case 0xB3: $ NOP CYC(1) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: $ NOP CYC(1) break;
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: ABSY_OPT LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: $ NOP CYC(1) break;
|
||||
case 0xBC: ABSX_OPT LDY CYC(4) break;
|
||||
case 0xBD: ABSX_OPT LDA CYC(4) break;
|
||||
case 0xBE: ABSY_OPT LDX CYC(4) break;
|
||||
case 0xBF: $ NOP CYC(1) break;
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: $ IMM NOP CYC(2) break;
|
||||
case 0xC3: $ NOP CYC(1) break;
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DEC CYC(5) break;
|
||||
case 0xC7: $ NOP CYC(1) break;
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: $ NOP CYC(1) break;
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DEC CYC(6) break;
|
||||
case 0xCF: $ NOP CYC(1) break;
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: INDY_OPT CMP CYC(5) break;
|
||||
case 0xD2: izp CMP CYC(5) break;
|
||||
case 0xD3: $ NOP CYC(1) break;
|
||||
case 0xD4: $ zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DEC CYC(6) break;
|
||||
case 0xD7: $ NOP CYC(1) break;
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: ABSY_OPT CMP CYC(4) break;
|
||||
case 0xDA: PHX CYC(3) break;
|
||||
case 0xDB: $ NOP CYC(1) break;
|
||||
case 0xDC: $ ABS LDD CYC(4) break;
|
||||
case 0xDD: ABSX_OPT CMP CYC(4) break;
|
||||
case 0xDE: ABSX_CONST DEC CYC(7) break;
|
||||
case 0xDF: $ NOP CYC(1) break;
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBCc CYC(6) break;
|
||||
case 0xE2: $ IMM NOP CYC(2) break;
|
||||
case 0xE3: $ NOP CYC(1) break;
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBCc CYC(3) break;
|
||||
case 0xE6: ZPG INC CYC(5) break;
|
||||
case 0xE7: $ NOP CYC(1) break;
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBCc CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: $ NOP CYC(1) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBCc CYC(4) break;
|
||||
case 0xEE: ABS INC CYC(6) break;
|
||||
case 0xEF: $ NOP CYC(1) break;
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: INDY_OPT SBCc CYC(5) break;
|
||||
case 0xF2: izp SBCc CYC(5) break;
|
||||
case 0xF3: $ NOP CYC(1) break;
|
||||
case 0xF4: $ zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBCc CYC(4) break;
|
||||
case 0xF6: zpx INC CYC(6) break;
|
||||
case 0xF7: $ NOP CYC(1) break;
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: ABSY_OPT SBCc CYC(4) break;
|
||||
case 0xFA: PLX CYC(4) break;
|
||||
case 0xFB: $ NOP CYC(1) break;
|
||||
case 0xFC: $ ABS LDD CYC(4) break;
|
||||
case 0xFD: ABSX_OPT SBCc CYC(4) break;
|
||||
case 0xFE: ABSX_CONST INC CYC(7) break;
|
||||
case 0xFF: $ NOP CYC(1) break;
|
||||
}
|
||||
#undef $
|
||||
}
|
||||
|
|
|
@ -18,8 +18,8 @@ along with AppleWin; if not, write to the Free Software
|
|||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
typedef unsigned char u8;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned char u8; // TODO: change to <stdint.h> uint8_t
|
||||
typedef unsigned short u16; // TODO: change to <stdint.h> uint16_t
|
||||
|
||||
// return (x < 255) ? (x+1) : 255;
|
||||
inline u8 IncClamp8( u8 x )
|
||||
|
@ -37,43 +37,58 @@ inline u8 DecClamp8( u8 x )
|
|||
return r;
|
||||
}
|
||||
|
||||
// TODO: Verify: RGBA or BGRA (.bmp format)
|
||||
// 0 A n/a
|
||||
// 1 B Exec
|
||||
// 2 G Read
|
||||
// 3 R Write
|
||||
// RGBA r= write, g = read, b = pc
|
||||
int g_aMemoryAccess[ 65536 ];
|
||||
u8 *g_pRead = 0;
|
||||
u8 *g_pWrite = 0;
|
||||
u8 *g_pExeec = 0;
|
||||
//
|
||||
// 0xAARRGGBB
|
||||
// [0] B Exec
|
||||
// [1] G Load
|
||||
// [2] R Store
|
||||
// [3] A n/a
|
||||
// RGBA r = write, g = read, b = Program Counter
|
||||
const int HEATMAP_W_MASK = 0x00FF0000; // Red Store
|
||||
const int HEATMAP_R_MASK = 0x0000FF00; // Green Load
|
||||
const int HEATMAP_X_MASK = 0x000000FF; // Blue Exec
|
||||
|
||||
|
||||
// This is a memory heatmap
|
||||
// FF = accessed on this clock cycle
|
||||
// FE = accessed 1 clock cycles ago
|
||||
// FD = accessed 2 clock cycles ago
|
||||
// etc.
|
||||
// Displayed as 256x256 64K memory access
|
||||
int g_aMemoryHeatmap[ 65536 ]; // TODO: Change to <stdint.h> int32_t
|
||||
|
||||
#define HEATMAP_W(addr) g_aMemoryHeatmap[ addr ] |= HEATMAP_W_MASK
|
||||
#define HEATMAP_R(addr) g_aMemoryHeatmap[ addr ] |= HEATMAP_R_MASK
|
||||
#define HEATMAP_X(addr) g_aMemoryHeatmap[ addr ] |= HEATMAP_X_MASK
|
||||
|
||||
#undef READ
|
||||
#define READ ReadByte( addr, uExecutedCycles )
|
||||
|
||||
inline u8 ReadByte( u16 addr, int uExecutedCycles )
|
||||
{
|
||||
(u8*) g_pRead = ((u8*)g_aMemoryAccess) + (addr * 4) + 3;
|
||||
*g_pRead = IncClamp8( *g_pRead );
|
||||
// TODO: We should have a single g_bDebuggerActive so we can have a single implementation across ][+ //e
|
||||
HEATMAP_R(addr);
|
||||
|
||||
return
|
||||
( \
|
||||
((addr & 0xF000) == 0xC000) \
|
||||
? IORead[(addr>>4) & 0xFF](regs.pc,addr,0,0,uExecutedCycles) \
|
||||
: *(mem+addr) \
|
||||
);
|
||||
return ((addr & 0xF000) == 0xC000)
|
||||
? IORead[(addr>>4) & 0xFF](regs.pc,addr,0,0,uExecutedCycles)
|
||||
: *(mem+addr);
|
||||
}
|
||||
|
||||
#undef WRITE
|
||||
#define WRITE(a) \
|
||||
(u8*) g_pWrite = ((u8*)g_aMemoryAccess) + (addr * 4) + 0; \
|
||||
*g_pWrite = DecClamp8( *g_pWrite ); \
|
||||
{ \
|
||||
memdirty[addr >> 8] = 0xFF; \
|
||||
LPBYTE page = memwrite[addr >> 8]; \
|
||||
if (page) \
|
||||
*(page+(addr & 0xFF)) = (BYTE)(a); \
|
||||
else if ((addr & 0xF000) == 0xC000) \
|
||||
IOWrite[(addr>>4) & 0xFF](regs.pc,addr,1,(BYTE)(a),uExecutedCycles); \
|
||||
#undef WRITE
|
||||
#define WRITE(a) \
|
||||
HEATMAP_W(addr); \
|
||||
{ \
|
||||
memdirty[addr >> 8] = 0xFF; \
|
||||
LPBYTE page = memwrite[addr >> 8]; \
|
||||
if (page) \
|
||||
*(page+(addr & 0xFF)) = (BYTE)(a); \
|
||||
else if ((addr & 0xF000) == 0xC000) \
|
||||
IOWrite[(addr>>4) & 0xFF](regs.pc,addr,1,(BYTE)(a),uExecutedCycles); \
|
||||
}
|
||||
|
||||
#include "cpu/cpu_instructions.inl"
|
||||
|
@ -97,7 +112,6 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
|
|||
WORD val;
|
||||
AF_TO_EF
|
||||
ULONG uExecutedCycles = 0;
|
||||
BOOL bSlowerOnPagecross = 0; // Set if opcode writes to memory (eg. ASL, STA)
|
||||
WORD base;
|
||||
g_bDebugBreakpointHit = 0;
|
||||
|
||||
|
@ -112,6 +126,8 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
|
|||
}
|
||||
else
|
||||
|
||||
HEATMAP_X( regs.pc );
|
||||
|
||||
if (!Fetch(iOpcode, uExecutedCycles))
|
||||
break;
|
||||
|
||||
|
@ -126,525 +142,264 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
|
|||
{
|
||||
// TODO Optimization Note: ?? Move CYC(#) to array ??
|
||||
|
||||
// Version 1 opcode: INV AM Instruction // Form1: INV=DebugBreak AM=AddressingMode
|
||||
// INV Instruction // Form2:
|
||||
//! ! ! ! ! ! // Tab-Stops
|
||||
/*
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: INV IMM NOP CYC(2) break;
|
||||
case 0x03: INV NOP CYC(2) break;
|
||||
case 0x04: ZPG TSB CYC(5) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASL_CMOS CYC(5) break;
|
||||
case 0x07: INV NOP CYC(2) break;
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: INV NOP CYC(2) break;
|
||||
case 0x0C: ABS TSB CYC(6) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASL_CMOS CYC(6) break;
|
||||
case 0x0F: INV NOP CYC(2) break;
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: idy ORA CYC(5) break;
|
||||
case 0x12: izp ORA CYC(5) break;
|
||||
case 0x13: INV NOP CYC(2) break;
|
||||
case 0x14: ZPG TRB CYC(5) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASL_CMOS CYC(6) break;
|
||||
case 0x17: INV NOP CYC(2) break;
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: aby ORA CYC(4) break;
|
||||
case 0x1A: INA CYC(2) break;
|
||||
case 0x1B: INV NOP CYC(2) break;
|
||||
case 0x1C: ABS TRB CYC(6) break;
|
||||
case 0x1D: abx ORA CYC(4) break;
|
||||
case 0x1E: abx ASL_CMOS CYC(6) break;
|
||||
case 0x1F: INV NOP CYC(2) break;
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: INV IMM NOP CYC(2) break;
|
||||
case 0x23: INV NOP CYC(2) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROL_CMOS CYC(5) break;
|
||||
case 0x27: INV NOP CYC(2) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: INV NOP CYC(2) break;
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(2) break;
|
||||
case 0x2E: ABS ROL_CMOS CYC(6) break;
|
||||
case 0x2F: INV NOP CYC(2) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: idy AND CYC(5) break;
|
||||
case 0x32: izp AND CYC(5) break;
|
||||
case 0x33: INV NOP CYC(2) break;
|
||||
case 0x34: zpx BIT CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROL_CMOS CYC(6) break;
|
||||
case 0x37: INV NOP CYC(2) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: aby AND CYC(4) break;
|
||||
case 0x3A: DEA CYC(2) break;
|
||||
case 0x3B: INV NOP CYC(2) break;
|
||||
case 0x3C: abx BIT CYC(4) break;
|
||||
case 0x3D: abx AND CYC(4) break;
|
||||
case 0x3E: abx ROL_CMOS CYC(6) break;
|
||||
case 0x3F: INV NOP CYC(2) break;
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: INV IMM NOP CYC(2) break;
|
||||
case 0x43: INV NOP CYC(2) break;
|
||||
case 0x44: INV ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSR_CMOS CYC(5) break;
|
||||
case 0x47: INV NOP CYC(2) break;
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: INV NOP CYC(2) break;
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSR_CMOS CYC(6) break;
|
||||
case 0x4F: INV NOP CYC(2) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: idy EOR CYC(5) break;
|
||||
case 0x52: izp EOR CYC(5) break;
|
||||
case 0x53: INV NOP CYC(2) break;
|
||||
case 0x54: INV zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSR_CMOS CYC(6) break;
|
||||
case 0x57: INV NOP CYC(2) break;
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: aby EOR CYC(4) break;
|
||||
case 0x5A: PHY CYC(3) break;
|
||||
case 0x5B: INV NOP CYC(2) break;
|
||||
case 0x5C: INV abx NOP CYC(8) break;
|
||||
case 0x5D: abx EOR CYC(4) break;
|
||||
case 0x5E: abx LSR_CMOS CYC(6) break;
|
||||
case 0x5F: INV NOP CYC(2) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADC_CMOS CYC(6) break;
|
||||
case 0x62: INV IMM NOP CYC(2) break;
|
||||
case 0x63: INV NOP CYC(2) break;
|
||||
case 0x64: ZPG STZ CYC(3) break;
|
||||
case 0x65: ZPG ADC_CMOS CYC(3) break;
|
||||
case 0x66: ZPG ROR_CMOS CYC(5) break;
|
||||
case 0x67: INV NOP CYC(2) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADC_CMOS CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: INV NOP CYC(2) break;
|
||||
case 0x6C: IABSCMOS JMP CYC(6) break; // 0x6C // 65c02 IABSCMOS JMP // 6502 IABSNMOS JMP
|
||||
case 0x6D: ABS ADC_CMOS CYC(4) break;
|
||||
case 0x6E: ABS ROR_CMOS CYC(6) break;
|
||||
case 0x6F: INV NOP CYC(2) break;
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: idy ADC_CMOS CYC(5) break;
|
||||
case 0x72: izp ADC_CMOS CYC(5) break;
|
||||
case 0x73: INV NOP CYC(2) break;
|
||||
case 0x74: zpx STZ CYC(4) break;
|
||||
case 0x75: zpx ADC_CMOS CYC(4) break;
|
||||
case 0x76: zpx ROR_CMOS CYC(6) break;
|
||||
case 0x77: INV NOP CYC(2) break;
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: aby ADC_CMOS CYC(4) break;
|
||||
case 0x7A: PLY CYC(4) break;
|
||||
case 0x7B: INV NOP CYC(2) break;
|
||||
case 0x7C: IABSX JMP CYC(6) break; // 0x7C // 65c02 IABSX JMP // 6502 ABSX NOP
|
||||
case 0x7D: abx ADC_CMOS CYC(4) break;
|
||||
case 0x7E: abx ROR_CMOS CYC(6) break;
|
||||
case 0x7F: INV NOP CYC(2) break;
|
||||
case 0x80: REL BRA CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: INV IMM NOP CYC(2) break;
|
||||
case 0x83: INV NOP CYC(2) break;
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: INV NOP CYC(2) break;
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: IMM BITI CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: INV NOP CYC(2) break;
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: INV NOP CYC(2) break;
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: idy STA CYC(6) break;
|
||||
case 0x92: izp STA CYC(5) break;
|
||||
case 0x93: INV NOP CYC(2) break;
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: INV NOP CYC(2) break;
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: aby STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: INV NOP CYC(2) break;
|
||||
case 0x9C: ABS STZ CYC(4) break;
|
||||
case 0x9D: abx STA CYC(5) break;
|
||||
case 0x9E: abx STZ CYC(5) break;
|
||||
case 0x9F: INV NOP CYC(2) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: INV NOP CYC(2) break;
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: INV NOP CYC(2) break;
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: INV NOP CYC(2) break;
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: INV NOP CYC(2) break;
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: idy LDA CYC(5) break;
|
||||
case 0xB2: izp LDA CYC(5) break;
|
||||
case 0xB3: INV NOP CYC(2) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: INV NOP CYC(2) break;
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: aby LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: INV NOP CYC(2) break;
|
||||
case 0xBC: abx LDY CYC(4) break;
|
||||
case 0xBD: abx LDA CYC(4) break;
|
||||
case 0xBE: aby LDX CYC(4) break;
|
||||
case 0xBF: INV NOP CYC(2) break;
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: INV IMM NOP CYC(2) break;
|
||||
case 0xC3: INV NOP CYC(2) break;
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DEC_CMOS CYC(5) break;
|
||||
case 0xC7: INV NOP CYC(2) break;
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: INV NOP CYC(2) break;
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DEC_CMOS CYC(5) break;
|
||||
case 0xCF: INV NOP CYC(2) break;
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: idy CMP CYC(5) break;
|
||||
case 0xD2: izp CMP CYC(5) break;
|
||||
case 0xD3: INV NOP CYC(2) break;
|
||||
case 0xD4: INV zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DEC_CMOS CYC(6) break;
|
||||
case 0xD7: INV NOP CYC(2) break;
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: aby CMP CYC(4) break;
|
||||
case 0xDA: PHX CYC(3) break;
|
||||
case 0xDB: INV NOP CYC(2) break;
|
||||
case 0xDC: INV abx NOP CYC(4) break;
|
||||
case 0xDD: abx CMP CYC(4) break;
|
||||
case 0xDE: abx DEC_CMOS CYC(6) break;
|
||||
case 0xDF: INV NOP CYC(2) break;
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBC_CMOS CYC(6) break;
|
||||
case 0xE2: INV IMM NOP CYC(2) break;
|
||||
case 0xE3: INV NOP CYC(2) break;
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBC_CMOS CYC(3) break;
|
||||
case 0xE6: ZPG INC_CMOS CYC(5) break;
|
||||
case 0xE7: INV NOP CYC(2) break;
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBC_CMOS CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: INV NOP CYC(2) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBC_CMOS CYC(4) break;
|
||||
case 0xEE: ABS INC_CMOS CYC(6) break;
|
||||
case 0xEF: INV NOP CYC(2) break;
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: idy SBC_CMOS CYC(5) break;
|
||||
case 0xF2: izp SBC_CMOS CYC(5) break;
|
||||
case 0xF3: INV NOP CYC(2) break;
|
||||
case 0xF4: INV zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBC_CMOS CYC(4) break;
|
||||
case 0xF6: zpx INC_CMOS CYC(6) break;
|
||||
case 0xF7: INV NOP CYC(2) break;
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: aby SBC_CMOS CYC(4) break;
|
||||
case 0xFA: PLX CYC(4) break;
|
||||
case 0xFB: INV NOP CYC(2) break;
|
||||
case 0xFC: INV abx NOP CYC(4) break;
|
||||
case 0xFD: abx SBC_CMOS CYC(4) break;
|
||||
case 0xFE: abx INC_CMOS CYC(6) break;
|
||||
case 0xFF: INV NOP CYC(2) break;
|
||||
*/
|
||||
// Version 2 opcode: $ AM Instruction // $=DebugBreak AM=AddressingMode
|
||||
//! ! ! ! ! ! // Tab-Stops
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: $ IMM NOP CYC(2) break;
|
||||
case 0x03: $ NOP CYC(2) break;
|
||||
case 0x04: ZPG TSB CYC(5) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASLc CYC(5) break;
|
||||
case 0x07: $ NOP CYC(2) break;
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: $ NOP CYC(2) break;
|
||||
case 0x0C: ABS TSB CYC(6) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASLc CYC(6) break;
|
||||
case 0x0F: $ NOP CYC(2) break;
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: idy ORA CYC(5) break;
|
||||
case 0x12: izp ORA CYC(5) break;
|
||||
case 0x13: $ NOP CYC(2) break;
|
||||
case 0x14: ZPG TRB CYC(5) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASLc CYC(6) break;
|
||||
case 0x17: $ NOP CYC(2) break;
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: aby ORA CYC(4) break;
|
||||
case 0x1A: INA CYC(2) break;
|
||||
case 0x1B: $ NOP CYC(2) break;
|
||||
case 0x1C: ABS TRB CYC(6) break;
|
||||
case 0x1D: abx ORA CYC(4) break;
|
||||
case 0x1E: abx ASLc CYC(6) break;
|
||||
case 0x1F: $ NOP CYC(2) break;
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: $ IMM NOP CYC(2) break;
|
||||
case 0x23: $ NOP CYC(2) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROLc CYC(5) break;
|
||||
case 0x27: $ NOP CYC(2) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: $ NOP CYC(2) break;
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(2) break;
|
||||
case 0x2E: ABS ROLc CYC(6) break;
|
||||
case 0x2F: $ NOP CYC(2) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: idy AND CYC(5) break;
|
||||
case 0x32: izp AND CYC(5) break;
|
||||
case 0x33: $ NOP CYC(2) break;
|
||||
case 0x34: zpx BIT CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROLc CYC(6) break;
|
||||
case 0x37: $ NOP CYC(2) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: aby AND CYC(4) break;
|
||||
case 0x3A: DEA CYC(2) break;
|
||||
case 0x3B: $ NOP CYC(2) break;
|
||||
case 0x3C: abx BIT CYC(4) break;
|
||||
case 0x3D: abx AND CYC(4) break;
|
||||
case 0x3E: abx ROLc CYC(6) break;
|
||||
case 0x3F: $ NOP CYC(2) break;
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: $ IMM NOP CYC(2) break;
|
||||
case 0x43: $ NOP CYC(2) break;
|
||||
case 0x44: $ ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSRc CYC(5) break;
|
||||
case 0x47: $ NOP CYC(2) break;
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: $ NOP CYC(2) break;
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSRc CYC(6) break;
|
||||
case 0x4F: $ NOP CYC(2) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: idy EOR CYC(5) break;
|
||||
case 0x52: izp EOR CYC(5) break;
|
||||
case 0x53: $ NOP CYC(2) break;
|
||||
case 0x54: $ zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSRc CYC(6) break;
|
||||
case 0x57: $ NOP CYC(2) break;
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: aby EOR CYC(4) break;
|
||||
case 0x5A: PHY CYC(3) break;
|
||||
case 0x5B: $ NOP CYC(2) break;
|
||||
case 0x5C: $ abx NOP CYC(8) break;
|
||||
case 0x5D: abx EOR CYC(4) break;
|
||||
case 0x5E: abx LSRc CYC(6) break;
|
||||
case 0x5F: $ NOP CYC(2) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADCc CYC(6) break;
|
||||
case 0x62: $ IMM NOP CYC(2) break;
|
||||
case 0x63: $ NOP CYC(2) break;
|
||||
case 0x64: ZPG STZ CYC(3) break;
|
||||
case 0x65: ZPG ADCc CYC(3) break;
|
||||
case 0x66: ZPG RORc CYC(5) break;
|
||||
case 0x67: $ NOP CYC(2) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADCc CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: $ NOP CYC(2) break;
|
||||
case 0x6C: IABSCMOS JMP CYC(6) break; // 0x6C // 65c02 IABSCMOS JMP // 6502 IABSNMOS JMP
|
||||
case 0x6D: ABS ADCc CYC(4) break;
|
||||
case 0x6E: ABS RORc CYC(6) break;
|
||||
case 0x6F: $ NOP CYC(2) break;
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: idy ADCc CYC(5) break;
|
||||
case 0x72: izp ADCc CYC(5) break;
|
||||
case 0x73: $ NOP CYC(2) break;
|
||||
case 0x74: zpx STZ CYC(4) break;
|
||||
case 0x75: zpx ADCc CYC(4) break;
|
||||
case 0x76: zpx RORc CYC(6) break;
|
||||
case 0x77: $ NOP CYC(2) break;
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: aby ADCc CYC(4) break;
|
||||
case 0x7A: PLY CYC(4) break;
|
||||
case 0x7B: $ NOP CYC(2) break;
|
||||
case 0x7C: IABSX JMP CYC(6) break; // 0x7C // 65c02 IABSX JMP // 6502 ABSX NOP
|
||||
case 0x7D: abx ADCc CYC(4) break;
|
||||
case 0x7E: abx RORc CYC(6) break;
|
||||
case 0x7F: $ NOP CYC(2) break;
|
||||
case 0x80: REL BRA CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: $ IMM NOP CYC(2) break;
|
||||
case 0x83: $ NOP CYC(2) break;
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: $ NOP CYC(2) break;
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: IMM BITI CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: $ NOP CYC(2) break;
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: $ NOP CYC(2) break;
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: idy STA CYC(6) break;
|
||||
case 0x92: izp STA CYC(5) break;
|
||||
case 0x93: $ NOP CYC(2) break;
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: $ NOP CYC(2) break;
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: aby STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: $ NOP CYC(2) break;
|
||||
case 0x9C: ABS STZ CYC(4) break;
|
||||
case 0x9D: abx STA CYC(5) break;
|
||||
case 0x9E: abx STZ CYC(5) break;
|
||||
case 0x9F: $ NOP CYC(2) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: $ NOP CYC(2) break;
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: $ NOP CYC(2) break;
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: $ NOP CYC(2) break;
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: $ NOP CYC(2) break;
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: idy LDA CYC(5) break;
|
||||
case 0xB2: izp LDA CYC(5) break;
|
||||
case 0xB3: $ NOP CYC(2) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: $ NOP CYC(2) break;
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: aby LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: $ NOP CYC(2) break;
|
||||
case 0xBC: abx LDY CYC(4) break;
|
||||
case 0xBD: abx LDA CYC(4) break;
|
||||
case 0xBE: aby LDX CYC(4) break;
|
||||
case 0xBF: $ NOP CYC(2) break;
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: $ IMM NOP CYC(2) break;
|
||||
case 0xC3: $ NOP CYC(2) break;
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DECc CYC(5) break;
|
||||
case 0xC7: $ NOP CYC(2) break;
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: $ NOP CYC(2) break;
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DECc CYC(5) break;
|
||||
case 0xCF: $ NOP CYC(2) break;
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: idy CMP CYC(5) break;
|
||||
case 0xD2: izp CMP CYC(5) break;
|
||||
case 0xD3: $ NOP CYC(2) break;
|
||||
case 0xD4: $ zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DECc CYC(6) break;
|
||||
case 0xD7: $ NOP CYC(2) break;
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: aby CMP CYC(4) break;
|
||||
case 0xDA: PHX CYC(3) break;
|
||||
case 0xDB: $ NOP CYC(2) break;
|
||||
case 0xDC: $ abx NOP CYC(4) break;
|
||||
case 0xDD: abx CMP CYC(4) break;
|
||||
case 0xDE: abx DECc CYC(6) break;
|
||||
case 0xDF: $ NOP CYC(2) break;
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBCc CYC(6) break;
|
||||
case 0xE2: $ IMM NOP CYC(2) break;
|
||||
case 0xE3: $ NOP CYC(2) break;
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBCc CYC(3) break;
|
||||
case 0xE6: ZPG INCc CYC(5) break;
|
||||
case 0xE7: $ NOP CYC(2) break;
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBCc CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: $ NOP CYC(2) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBCc CYC(4) break;
|
||||
case 0xEE: ABS INCc CYC(6) break;
|
||||
case 0xEF: $ NOP CYC(2) break;
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: idy SBCc CYC(5) break;
|
||||
case 0xF2: izp SBCc CYC(5) break;
|
||||
case 0xF3: $ NOP CYC(2) break;
|
||||
case 0xF4: $ zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBCc CYC(4) break;
|
||||
case 0xF6: zpx INCc CYC(6) break;
|
||||
case 0xF7: $ NOP CYC(2) break;
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: aby SBCc CYC(4) break;
|
||||
case 0xFA: PLX CYC(4) break;
|
||||
case 0xFB: $ NOP CYC(2) break;
|
||||
case 0xFC: $ abx NOP CYC(4) break;
|
||||
case 0xFD: abx SBCc CYC(4) break;
|
||||
case 0xFE: abx INCc CYC(6) break;
|
||||
case 0xFF: $ NOP CYC(2) break;
|
||||
// Version 2 opcode: $ AM Instruction // $=DebugBreak AM=AddressingMode
|
||||
//! ! ! ! ! ! // Tab-Stops
|
||||
case 0x00: BRK CYC(7) break;
|
||||
case 0x01: idx ORA CYC(6) break;
|
||||
case 0x02: $ IMM NOP CYC(2) break;
|
||||
case 0x03: $ NOP CYC(2) break;
|
||||
case 0x04: ZPG TSB CYC(5) break;
|
||||
case 0x05: ZPG ORA CYC(3) break;
|
||||
case 0x06: ZPG ASLc CYC(5) break;
|
||||
case 0x07: $ NOP CYC(2) break;
|
||||
case 0x08: PHP CYC(3) break;
|
||||
case 0x09: IMM ORA CYC(2) break;
|
||||
case 0x0A: asl CYC(2) break;
|
||||
case 0x0B: $ NOP CYC(2) break;
|
||||
case 0x0C: ABS TSB CYC(6) break;
|
||||
case 0x0D: ABS ORA CYC(4) break;
|
||||
case 0x0E: ABS ASLc CYC(6) break;
|
||||
case 0x0F: $ NOP CYC(2) break;
|
||||
case 0x10: REL BPL CYC(2) break;
|
||||
case 0x11: INDY_OPT ORA CYC(5) break;
|
||||
case 0x12: izp ORA CYC(5) break;
|
||||
case 0x13: $ NOP CYC(2) break;
|
||||
case 0x14: ZPG TRB CYC(5) break;
|
||||
case 0x15: zpx ORA CYC(4) break;
|
||||
case 0x16: zpx ASLc CYC(6) break;
|
||||
case 0x17: $ NOP CYC(2) break;
|
||||
case 0x18: CLC CYC(2) break;
|
||||
case 0x19: ABSY_OPT ORA CYC(4) break;
|
||||
case 0x1A: INA CYC(2) break;
|
||||
case 0x1B: $ NOP CYC(2) break;
|
||||
case 0x1C: ABS TRB CYC(6) break;
|
||||
case 0x1D: ABSX_OPT ORA CYC(4) break;
|
||||
case 0x1E: ABSX_OPT ASLc CYC(6) break;
|
||||
case 0x1F: $ NOP CYC(2) break;
|
||||
case 0x20: ABS JSR CYC(6) break;
|
||||
case 0x21: idx AND CYC(6) break;
|
||||
case 0x22: $ IMM NOP CYC(2) break;
|
||||
case 0x23: $ NOP CYC(2) break;
|
||||
case 0x24: ZPG BIT CYC(3) break;
|
||||
case 0x25: ZPG AND CYC(3) break;
|
||||
case 0x26: ZPG ROLc CYC(5) break;
|
||||
case 0x27: $ NOP CYC(2) break;
|
||||
case 0x28: PLP CYC(4) break;
|
||||
case 0x29: IMM AND CYC(2) break;
|
||||
case 0x2A: rol CYC(2) break;
|
||||
case 0x2B: $ NOP CYC(2) break;
|
||||
case 0x2C: ABS BIT CYC(4) break;
|
||||
case 0x2D: ABS AND CYC(2) break;
|
||||
case 0x2E: ABS ROLc CYC(6) break;
|
||||
case 0x2F: $ NOP CYC(2) break;
|
||||
case 0x30: REL BMI CYC(2) break;
|
||||
case 0x31: INDY_OPT AND CYC(5) break;
|
||||
case 0x32: izp AND CYC(5) break;
|
||||
case 0x33: $ NOP CYC(2) break;
|
||||
case 0x34: zpx BIT CYC(4) break;
|
||||
case 0x35: zpx AND CYC(4) break;
|
||||
case 0x36: zpx ROLc CYC(6) break;
|
||||
case 0x37: $ NOP CYC(2) break;
|
||||
case 0x38: SEC CYC(2) break;
|
||||
case 0x39: ABSY_OPT AND CYC(4) break;
|
||||
case 0x3A: DEA CYC(2) break;
|
||||
case 0x3B: $ NOP CYC(2) break;
|
||||
case 0x3C: ABSX_OPT BIT CYC(4) break;
|
||||
case 0x3D: ABSX_OPT AND CYC(4) break;
|
||||
case 0x3E: ABSX_OPT ROLc CYC(6) break;
|
||||
case 0x3F: $ NOP CYC(2) break;
|
||||
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
|
||||
case 0x41: idx EOR CYC(6) break;
|
||||
case 0x42: $ IMM NOP CYC(2) break;
|
||||
case 0x43: $ NOP CYC(2) break;
|
||||
case 0x44: $ ZPG NOP CYC(3) break;
|
||||
case 0x45: ZPG EOR CYC(3) break;
|
||||
case 0x46: ZPG LSRc CYC(5) break;
|
||||
case 0x47: $ NOP CYC(2) break;
|
||||
case 0x48: PHA CYC(3) break;
|
||||
case 0x49: IMM EOR CYC(2) break;
|
||||
case 0x4A: lsr CYC(2) break;
|
||||
case 0x4B: $ NOP CYC(2) break;
|
||||
case 0x4C: ABS JMP CYC(3) break;
|
||||
case 0x4D: ABS EOR CYC(4) break;
|
||||
case 0x4E: ABS LSRc CYC(6) break;
|
||||
case 0x4F: $ NOP CYC(2) break;
|
||||
case 0x50: REL BVC CYC(2) break;
|
||||
case 0x51: INDY_OPT EOR CYC(5) break;
|
||||
case 0x52: izp EOR CYC(5) break;
|
||||
case 0x53: $ NOP CYC(2) break;
|
||||
case 0x54: $ zpx NOP CYC(4) break;
|
||||
case 0x55: zpx EOR CYC(4) break;
|
||||
case 0x56: zpx LSRc CYC(6) break;
|
||||
case 0x57: $ NOP CYC(2) break;
|
||||
case 0x58: CLI CYC(2) break;
|
||||
case 0x59: ABSY_OPT EOR CYC(4) break;
|
||||
case 0x5A: PHY CYC(3) break;
|
||||
case 0x5B: $ NOP CYC(2) break;
|
||||
case 0x5C: $ ABSX_OPT NOP CYC(8) break;
|
||||
case 0x5D: ABSX_OPT EOR CYC(4) break;
|
||||
case 0x5E: ABSX_OPT LSRc CYC(6) break;
|
||||
case 0x5F: $ NOP CYC(2) break;
|
||||
case 0x60: RTS CYC(6) break;
|
||||
case 0x61: idx ADCc CYC(6) break;
|
||||
case 0x62: $ IMM NOP CYC(2) break;
|
||||
case 0x63: $ NOP CYC(2) break;
|
||||
case 0x64: ZPG STZ CYC(3) break;
|
||||
case 0x65: ZPG ADCc CYC(3) break;
|
||||
case 0x66: ZPG RORc CYC(5) break;
|
||||
case 0x67: $ NOP CYC(2) break;
|
||||
case 0x68: PLA CYC(4) break;
|
||||
case 0x69: IMM ADCc CYC(2) break;
|
||||
case 0x6A: ror CYC(2) break;
|
||||
case 0x6B: $ NOP CYC(2) break;
|
||||
case 0x6C: IABS_CMOS JMP CYC(6) break;
|
||||
case 0x6D: ABS ADCc CYC(4) break;
|
||||
case 0x6E: ABS RORc CYC(6) break;
|
||||
case 0x6F: $ NOP CYC(2) break;
|
||||
case 0x70: REL BVS CYC(2) break;
|
||||
case 0x71: INDY_OPT ADCc CYC(5) break;
|
||||
case 0x72: izp ADCc CYC(5) break;
|
||||
case 0x73: $ NOP CYC(2) break;
|
||||
case 0x74: zpx STZ CYC(4) break;
|
||||
case 0x75: zpx ADCc CYC(4) break;
|
||||
case 0x76: zpx RORc CYC(6) break;
|
||||
case 0x77: $ NOP CYC(2) break;
|
||||
case 0x78: SEI CYC(2) break;
|
||||
case 0x79: ABSY_OPT ADCc CYC(4) break;
|
||||
case 0x7A: PLY CYC(4) break;
|
||||
case 0x7B: $ NOP CYC(2) break;
|
||||
case 0x7C: IABSX JMP CYC(6) break;
|
||||
case 0x7D: ABSX_OPT ADCc CYC(4) break;
|
||||
case 0x7E: ABSX_OPT RORc CYC(6) break;
|
||||
case 0x7F: $ NOP CYC(2) break;
|
||||
case 0x80: REL BRA CYC(2) break;
|
||||
case 0x81: idx STA CYC(6) break;
|
||||
case 0x82: $ IMM NOP CYC(2) break;
|
||||
case 0x83: $ NOP CYC(2) break;
|
||||
case 0x84: ZPG STY CYC(3) break;
|
||||
case 0x85: ZPG STA CYC(3) break;
|
||||
case 0x86: ZPG STX CYC(3) break;
|
||||
case 0x87: $ NOP CYC(2) break;
|
||||
case 0x88: DEY CYC(2) break;
|
||||
case 0x89: IMM BITI CYC(2) break;
|
||||
case 0x8A: TXA CYC(2) break;
|
||||
case 0x8B: $ NOP CYC(2) break;
|
||||
case 0x8C: ABS STY CYC(4) break;
|
||||
case 0x8D: ABS STA CYC(4) break;
|
||||
case 0x8E: ABS STX CYC(4) break;
|
||||
case 0x8F: $ NOP CYC(2) break;
|
||||
case 0x90: REL BCC CYC(2) break;
|
||||
case 0x91: INDY_CONST STA CYC(6) break;
|
||||
case 0x92: izp STA CYC(5) break;
|
||||
case 0x93: $ NOP CYC(2) break;
|
||||
case 0x94: zpx STY CYC(4) break;
|
||||
case 0x95: zpx STA CYC(4) break;
|
||||
case 0x96: zpy STX CYC(4) break;
|
||||
case 0x97: $ NOP CYC(2) break;
|
||||
case 0x98: TYA CYC(2) break;
|
||||
case 0x99: ABSY_CONST STA CYC(5) break;
|
||||
case 0x9A: TXS CYC(2) break;
|
||||
case 0x9B: $ NOP CYC(2) break;
|
||||
case 0x9C: ABS STZ CYC(4) break;
|
||||
case 0x9D: ABSX_CONST STA CYC(5) break;
|
||||
case 0x9E: ABSX_CONST STZ CYC(5) break;
|
||||
case 0x9F: $ NOP CYC(2) break;
|
||||
case 0xA0: IMM LDY CYC(2) break;
|
||||
case 0xA1: idx LDA CYC(6) break;
|
||||
case 0xA2: IMM LDX CYC(2) break;
|
||||
case 0xA3: $ NOP CYC(2) break;
|
||||
case 0xA4: ZPG LDY CYC(3) break;
|
||||
case 0xA5: ZPG LDA CYC(3) break;
|
||||
case 0xA6: ZPG LDX CYC(3) break;
|
||||
case 0xA7: $ NOP CYC(2) break;
|
||||
case 0xA8: TAY CYC(2) break;
|
||||
case 0xA9: IMM LDA CYC(2) break;
|
||||
case 0xAA: TAX CYC(2) break;
|
||||
case 0xAB: $ NOP CYC(2) break;
|
||||
case 0xAC: ABS LDY CYC(4) break;
|
||||
case 0xAD: ABS LDA CYC(4) break;
|
||||
case 0xAE: ABS LDX CYC(4) break;
|
||||
case 0xAF: $ NOP CYC(2) break;
|
||||
case 0xB0: REL BCS CYC(2) break;
|
||||
case 0xB1: INDY_OPT LDA CYC(5) break;
|
||||
case 0xB2: izp LDA CYC(5) break;
|
||||
case 0xB3: $ NOP CYC(2) break;
|
||||
case 0xB4: zpx LDY CYC(4) break;
|
||||
case 0xB5: zpx LDA CYC(4) break;
|
||||
case 0xB6: zpy LDX CYC(4) break;
|
||||
case 0xB7: $ NOP CYC(2) break;
|
||||
case 0xB8: CLV CYC(2) break;
|
||||
case 0xB9: ABSY_OPT LDA CYC(4) break;
|
||||
case 0xBA: TSX CYC(2) break;
|
||||
case 0xBB: $ NOP CYC(2) break;
|
||||
case 0xBC: ABSX_OPT LDY CYC(4) break;
|
||||
case 0xBD: ABSX_OPT LDA CYC(4) break;
|
||||
case 0xBE: ABSY_OPT LDX CYC(4) break;
|
||||
case 0xBF: $ NOP CYC(2) break;
|
||||
case 0xC0: IMM CPY CYC(2) break;
|
||||
case 0xC1: idx CMP CYC(6) break;
|
||||
case 0xC2: $ IMM NOP CYC(2) break;
|
||||
case 0xC3: $ NOP CYC(2) break;
|
||||
case 0xC4: ZPG CPY CYC(3) break;
|
||||
case 0xC5: ZPG CMP CYC(3) break;
|
||||
case 0xC6: ZPG DEC CYC(5) break;
|
||||
case 0xC7: $ NOP CYC(2) break;
|
||||
case 0xC8: INY CYC(2) break;
|
||||
case 0xC9: IMM CMP CYC(2) break;
|
||||
case 0xCA: DEX CYC(2) break;
|
||||
case 0xCB: $ NOP CYC(2) break;
|
||||
case 0xCC: ABS CPY CYC(4) break;
|
||||
case 0xCD: ABS CMP CYC(4) break;
|
||||
case 0xCE: ABS DEC CYC(6) break;
|
||||
case 0xCF: $ NOP CYC(2) break;
|
||||
case 0xD0: REL BNE CYC(2) break;
|
||||
case 0xD1: INDY_OPT CMP CYC(5) break;
|
||||
case 0xD2: izp CMP CYC(5) break;
|
||||
case 0xD3: $ NOP CYC(2) break;
|
||||
case 0xD4: $ zpx NOP CYC(4) break;
|
||||
case 0xD5: zpx CMP CYC(4) break;
|
||||
case 0xD6: zpx DEC CYC(6) break;
|
||||
case 0xD7: $ NOP CYC(2) break;
|
||||
case 0xD8: CLD CYC(2) break;
|
||||
case 0xD9: ABSY_OPT CMP CYC(4) break;
|
||||
case 0xDA: PHX CYC(3) break;
|
||||
case 0xDB: $ NOP CYC(2) break;
|
||||
case 0xDC: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0xDD: ABSX_OPT CMP CYC(4) break;
|
||||
case 0xDE: ABSX_CONST DEC CYC(7) break;
|
||||
case 0xDF: $ NOP CYC(2) break;
|
||||
case 0xE0: IMM CPX CYC(2) break;
|
||||
case 0xE1: idx SBCc CYC(6) break;
|
||||
case 0xE2: $ IMM NOP CYC(2) break;
|
||||
case 0xE3: $ NOP CYC(2) break;
|
||||
case 0xE4: ZPG CPX CYC(3) break;
|
||||
case 0xE5: ZPG SBCc CYC(3) break;
|
||||
case 0xE6: ZPG INC CYC(5) break;
|
||||
case 0xE7: $ NOP CYC(2) break;
|
||||
case 0xE8: INX CYC(2) break;
|
||||
case 0xE9: IMM SBCc CYC(2) break;
|
||||
case 0xEA: NOP CYC(2) break;
|
||||
case 0xEB: $ NOP CYC(2) break;
|
||||
case 0xEC: ABS CPX CYC(4) break;
|
||||
case 0xED: ABS SBCc CYC(4) break;
|
||||
case 0xEE: ABS INC CYC(6) break;
|
||||
case 0xEF: $ NOP CYC(2) break;
|
||||
case 0xF0: REL BEQ CYC(2) break;
|
||||
case 0xF1: INDY_OPT SBCc CYC(5) break;
|
||||
case 0xF2: izp SBCc CYC(5) break;
|
||||
case 0xF3: $ NOP CYC(2) break;
|
||||
case 0xF4: $ zpx NOP CYC(4) break;
|
||||
case 0xF5: zpx SBCc CYC(4) break;
|
||||
case 0xF6: zpx INC CYC(6) break;
|
||||
case 0xF7: $ NOP CYC(2) break;
|
||||
case 0xF8: SED CYC(2) break;
|
||||
case 0xF9: ABSY_OPT SBCc CYC(4) break;
|
||||
case 0xFA: PLX CYC(4) break;
|
||||
case 0xFB: $ NOP CYC(2) break;
|
||||
case 0xFC: $ ABSX_OPT NOP CYC(4) break;
|
||||
case 0xFD: ABSX_OPT SBCc CYC(4) break;
|
||||
case 0xFE: ABSX_CONST INC CYC(7) break;
|
||||
case 0xFF: $ NOP CYC(2) break;
|
||||
}
|
||||
#undef $
|
||||
|
||||
|
|
|
@ -73,6 +73,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
IOWrite[(addr>>4) & 0xFF](regs.pc,addr,1,(BYTE)(a),uExecutedCycles); \
|
||||
}
|
||||
|
||||
#define ON_PAGECROSS_REPLACE_HI_ADDR if ((base ^ addr) >> 8) {addr = (val<<8) | (addr&0xff);} /* GH#282 */
|
||||
|
||||
//
|
||||
|
||||
// ExtraCycles:
|
||||
|
@ -89,10 +91,9 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
//
|
||||
|
||||
#define CHECK_PAGE_CHANGE if (bSlowerOnPagecross) { \
|
||||
if ((base ^ addr) & 0xFF00) \
|
||||
uExtraCycles=1; \
|
||||
}
|
||||
// TODO Optimization Note: uExtraCycles = ((base ^ addr) >> 8) & 1;
|
||||
#define CHECK_PAGE_CHANGE if ((base ^ addr) & 0xFF00) \
|
||||
uExtraCycles=1;
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
|
@ -102,53 +103,71 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
#define ABS addr = *(LPWORD)(mem+regs.pc); regs.pc += 2;
|
||||
#define IABSX addr = *(LPWORD)(mem+(*(LPWORD)(mem+regs.pc))+(WORD)regs.x); regs.pc += 2;
|
||||
#define ABSX base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
|
||||
#define ABSY base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
|
||||
// TODO Optimization Note: uExtraCycles = ((base & 0xFF) + 1) >> 8;
|
||||
#define IABSCMOS base = *(LPWORD)(mem+regs.pc); \
|
||||
|
||||
// Optimised for page-cross
|
||||
#define ABSX_OPT base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
|
||||
// Not optimised for page-cross
|
||||
#define ABSX_CONST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2;
|
||||
|
||||
// Optimised for page-cross
|
||||
#define ABSY_OPT base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
|
||||
// Not optimised for page-cross
|
||||
#define ABSY_CONST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2;
|
||||
|
||||
// TODO Optimization Note (just for IABSCMOS): uExtraCycles = ((base & 0xFF) + 1) >> 8;
|
||||
#define IABS_CMOS base = *(LPWORD)(mem+regs.pc); \
|
||||
addr = *(LPWORD)(mem+base); \
|
||||
if ((base & 0xFF) == 0xFF) uExtraCycles=1; \
|
||||
regs.pc += 2;
|
||||
#define IABSNMOS base = *(LPWORD)(mem+regs.pc); \
|
||||
#define IABS_NMOS base = *(LPWORD)(mem+regs.pc); \
|
||||
if ((base & 0xFF) == 0xFF) \
|
||||
addr = *(mem+base)+((WORD)*(mem+(base&0xFF00))<<8);\
|
||||
else \
|
||||
else \
|
||||
addr = *(LPWORD)(mem+base); \
|
||||
regs.pc += 2;
|
||||
|
||||
#define IMM addr = regs.pc++;
|
||||
|
||||
#define INDX base = ((*(mem+regs.pc++))+regs.x) & 0xFF; \
|
||||
if (base == 0xFF) \
|
||||
addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
|
||||
else \
|
||||
addr = *(LPWORD)(mem+base);
|
||||
#define INDY if (*(mem+regs.pc) == 0xFF) \
|
||||
|
||||
// Optimised for page-cross
|
||||
#define INDY_OPT if (*(mem+regs.pc) == 0xFF) /*incurs an extra cycle for page-crossing*/ \
|
||||
base = *(mem+0xFF)+(((WORD)*mem)<<8); \
|
||||
else \
|
||||
base = *(LPWORD)(mem+*(mem+regs.pc)); \
|
||||
regs.pc++; \
|
||||
addr = base+(WORD)regs.y; \
|
||||
CHECK_PAGE_CHANGE;
|
||||
// Not optimised for page-cross
|
||||
#define INDY_CONST if (*(mem+regs.pc) == 0xFF) /*no extra cycle for page-crossing*/ \
|
||||
base = *(mem+0xFF)+(((WORD)*mem)<<8); \
|
||||
else \
|
||||
base = *(LPWORD)(mem+*(mem+regs.pc)); \
|
||||
regs.pc++; \
|
||||
addr = base+(WORD)regs.y;
|
||||
|
||||
#define IZPG base = *(mem+regs.pc++); \
|
||||
if (base == 0xFF) \
|
||||
addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
|
||||
else \
|
||||
addr = *(LPWORD)(mem+base);
|
||||
|
||||
#define REL addr = (signed char)*(mem+regs.pc++);
|
||||
|
||||
// TODO Optimization Note:
|
||||
// . Opcodes that generate zero-page addresses can't be accessing $C000..$CFFF
|
||||
// so they could be paired with special READZP/WRITEZP macros (instead of READ/WRITE)
|
||||
#define ZPG addr = *(mem+regs.pc++);
|
||||
#define ZPG addr = *(mem+regs.pc++);
|
||||
#define ZPGX addr = ((*(mem+regs.pc++))+regs.x) & 0xFF;
|
||||
#define ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
|
||||
|
||||
// Tidy 3 char addressing modes to keep the opcode table visually aligned, clean, and readable.
|
||||
#undef abx
|
||||
#undef abx
|
||||
#undef aby
|
||||
#undef asl
|
||||
#undef idx
|
||||
#undef idy
|
||||
#undef imm
|
||||
#undef izp
|
||||
#undef lsr
|
||||
|
@ -158,11 +177,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#undef zpx
|
||||
#undef zpy
|
||||
|
||||
#define abx ABSX
|
||||
#define aby ABSY
|
||||
#define asl ASLA // Arithmetic Shift Left
|
||||
#define idx INDX
|
||||
#define idy INDY
|
||||
#define imm IMM
|
||||
#define izp IZPG
|
||||
#define lsr LSRA // Logical Shift Right
|
||||
|
@ -171,6 +187,3 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#define ror RORA // Rotate Right
|
||||
#define zpx ZPGX
|
||||
#define zpy ZPGY
|
||||
// 0x6C // 65c02 IABSCMOS JMP // 6502 IABSNMOS JMP
|
||||
// 0x7C IABSX
|
||||
|
||||
|
|
|
@ -68,15 +68,13 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#undef CPY
|
||||
#undef DCM
|
||||
#undef DEA
|
||||
#undef DEC_NMOS
|
||||
#undef DEC_CMOS
|
||||
#undef DEC
|
||||
#undef DEX
|
||||
#undef DEY
|
||||
#undef EOR
|
||||
#undef HLT
|
||||
#undef INA
|
||||
#undef INC_NMOS
|
||||
#undef INC_CMOS
|
||||
#undef INC
|
||||
#undef INS
|
||||
#undef INX
|
||||
#undef INY
|
||||
|
@ -139,8 +137,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
#undef ADCn
|
||||
#undef ASLn
|
||||
#undef DECn
|
||||
#undef INCn
|
||||
#undef LSRn
|
||||
#undef ROLn
|
||||
#undef RORn
|
||||
|
@ -148,8 +144,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
#define ADCn ADC_NMOS
|
||||
#define ASLn ASL_NMOS
|
||||
#define DECn DEC_NMOS
|
||||
#define INCn INC_NMOS
|
||||
#define LSRn LSR_NMOS
|
||||
#define ROLn ROL_NMOS
|
||||
#define RORn ROR_NMOS
|
||||
|
@ -159,8 +153,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
#undef ADCc
|
||||
#undef ASLc
|
||||
#undef DECc
|
||||
#undef INCc
|
||||
#undef LSRc
|
||||
#undef ROLc
|
||||
#undef RORc
|
||||
|
@ -168,8 +160,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
#define ADCc ADC_CMOS
|
||||
#define ASLc ASL_CMOS
|
||||
#define DECc DEC_CMOS
|
||||
#define INCc INC_CMOS
|
||||
#define LSRc LSR_CMOS
|
||||
#define ROLc ROL_CMOS
|
||||
#define RORc ROR_CMOS
|
||||
|
@ -177,7 +167,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
// ==========
|
||||
|
||||
#define ADC_NMOS bSlowerOnPagecross = 1; \
|
||||
#define ADC_NMOS /*bSlowerOnPagecross = 1;*/ \
|
||||
temp = READ; \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
val = (regs.a & 0x0F) + (temp & 0x0F) + flagc; \
|
||||
|
@ -203,7 +193,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a); \
|
||||
}
|
||||
#define ADC_CMOS bSlowerOnPagecross = 1; \
|
||||
#define ADC_CMOS /*bSlowerOnPagecross = 1*/; \
|
||||
temp = READ; \
|
||||
flagv = !((regs.a ^ temp) & 0x80); \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
|
@ -242,7 +232,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagn = 0; \
|
||||
regs.a >>= 1; \
|
||||
SETZ(regs.a)
|
||||
#define AND bSlowerOnPagecross = 1; \
|
||||
#define AND /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.a &= READ; \
|
||||
SETNZ(regs.a)
|
||||
#define ANC regs.a &= READ; \
|
||||
|
@ -274,12 +264,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagv = ((val & 0x40) ^ ((val & 0x20) << 1)); \
|
||||
regs.a = (val & 0xFF); \
|
||||
}
|
||||
#define ASL_NMOS bSlowerOnPagecross = 0; \
|
||||
#define ASL_NMOS /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ << 1; \
|
||||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define ASL_CMOS bSlowerOnPagecross = 1; \
|
||||
#define ASL_CMOS /*bSlowerOnPagecross = 1*/; \
|
||||
val = READ << 1; \
|
||||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
|
@ -288,21 +278,22 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
regs.a = (BYTE)val;
|
||||
#define ASO bSlowerOnPagecross = 0; \
|
||||
#define ASO /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ << 1; \
|
||||
flagc = (val > 0xFF); \
|
||||
WRITE(val) \
|
||||
regs.a |= val; \
|
||||
SETNZ(regs.a)
|
||||
#define AXA bSlowerOnPagecross = 0;/*FIXME: $93 case is still unclear*/ \
|
||||
#define AXA /*bSlowerOnPagecross = 0;*/ \
|
||||
val = regs.a & regs.x & (((base >> 8) + 1) & 0xFF); \
|
||||
ON_PAGECROSS_REPLACE_HI_ADDR \
|
||||
WRITE(val)
|
||||
#define AXS bSlowerOnPagecross = 0; \
|
||||
#define AXS /*bSlowerOnPagecross = 0;*/ \
|
||||
WRITE(regs.a & regs.x)
|
||||
#define BCC if (!flagc) BRANCH_TAKEN;
|
||||
#define BCS if ( flagc) BRANCH_TAKEN;
|
||||
#define BEQ if ( flagz) BRANCH_TAKEN;
|
||||
#define BIT bSlowerOnPagecross = 1; \
|
||||
#define BIT /*bSlowerOnPagecross = 1;*/ \
|
||||
val = READ; \
|
||||
flagz = !(regs.a & val); \
|
||||
flagn = val & 0x80; \
|
||||
|
@ -325,7 +316,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#define CLD regs.ps &= ~AF_DECIMAL;
|
||||
#define CLI regs.ps &= ~AF_INTERRUPT;
|
||||
#define CLV flagv = 0;
|
||||
#define CMP bSlowerOnPagecross = 1; \
|
||||
#define CMP /*bSlowerOnPagecross = 1;*/ \
|
||||
val = READ; \
|
||||
flagc = (regs.a >= val); \
|
||||
val = regs.a-val; \
|
||||
|
@ -338,7 +329,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagc = (regs.y >= val); \
|
||||
val = regs.y-val; \
|
||||
SETNZ(val)
|
||||
#define DCM bSlowerOnPagecross = 0; \
|
||||
#define DCM /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ-1; \
|
||||
WRITE(val) \
|
||||
flagc = (regs.a >= val); \
|
||||
|
@ -346,11 +337,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
SETNZ(val)
|
||||
#define DEA --regs.a; \
|
||||
SETNZ(regs.a)
|
||||
#define DEC_NMOS bSlowerOnPagecross = 0; \
|
||||
val = READ-1; \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define DEC_CMOS bSlowerOnPagecross = 1; \
|
||||
#define DEC /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ-1; \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
|
@ -358,22 +345,18 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
SETNZ(regs.x)
|
||||
#define DEY --regs.y; \
|
||||
SETNZ(regs.y)
|
||||
#define EOR bSlowerOnPagecross = 1; \
|
||||
#define EOR /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.a ^= READ; \
|
||||
SETNZ(regs.a)
|
||||
#define HLT regs.bJammed = 1; \
|
||||
--regs.pc;
|
||||
#define INA ++regs.a; \
|
||||
SETNZ(regs.a)
|
||||
#define INC_NMOS bSlowerOnPagecross = 0; \
|
||||
#define INC /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ+1; \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define INC_CMOS bSlowerOnPagecross = 1; \
|
||||
val = READ+1; \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define INS bSlowerOnPagecross = 0; \
|
||||
#define INS /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ+1; \
|
||||
WRITE(val) \
|
||||
temp = val; \
|
||||
|
@ -408,38 +391,40 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
PUSH(regs.pc >> 8) \
|
||||
PUSH(regs.pc & 0xFF) \
|
||||
regs.pc = addr;
|
||||
#define LAS bSlowerOnPagecross = 1; \
|
||||
#define LAS /*bSlowerOnPagecross = 1*/; \
|
||||
val = (BYTE)(READ & regs.sp); \
|
||||
regs.a = regs.x = (BYTE) val; \
|
||||
regs.sp = val | 0x100; \
|
||||
SETNZ(val)
|
||||
#define LAX bSlowerOnPagecross = 1; \
|
||||
#define LAX /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.a = regs.x = READ; \
|
||||
SETNZ(regs.a)
|
||||
#define LDA bSlowerOnPagecross = 1; \
|
||||
#define LDA /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.a = READ; \
|
||||
SETNZ(regs.a)
|
||||
#define LDX bSlowerOnPagecross = 1; \
|
||||
#define LDD /*Undocumented 65C02: LoaD and Discard*/ \
|
||||
READ;
|
||||
#define LDX /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.x = READ; \
|
||||
SETNZ(regs.x)
|
||||
#define LDY bSlowerOnPagecross = 1; \
|
||||
#define LDY /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.y = READ; \
|
||||
SETNZ(regs.y)
|
||||
#define LSE bSlowerOnPagecross = 0; \
|
||||
#define LSE /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ; \
|
||||
flagc = (val & 1); \
|
||||
val >>= 1; \
|
||||
WRITE(val) \
|
||||
regs.a ^= val; \
|
||||
SETNZ(regs.a)
|
||||
#define LSR_NMOS bSlowerOnPagecross = 0; \
|
||||
#define LSR_NMOS /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ; \
|
||||
flagc = (val & 1); \
|
||||
flagn = 0; \
|
||||
val >>= 1; \
|
||||
SETZ(val) \
|
||||
WRITE(val)
|
||||
#define LSR_CMOS bSlowerOnPagecross = 1; \
|
||||
#define LSR_CMOS /*bSlowerOnPagecross = 1;*/ \
|
||||
val = READ; \
|
||||
flagc = (val & 1); \
|
||||
flagn = 0; \
|
||||
|
@ -450,12 +435,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagn = 0; \
|
||||
regs.a >>= 1; \
|
||||
SETZ(regs.a)
|
||||
#define NOP bSlowerOnPagecross = 1;
|
||||
#define NOP /*bSlowerOnPagecross = 1;*/
|
||||
#define OAL regs.a |= 0xEE; \
|
||||
regs.a &= READ; \
|
||||
regs.x = regs.a; \
|
||||
SETNZ(regs.a)
|
||||
#define ORA bSlowerOnPagecross = 1; \
|
||||
#define ORA /*bSlowerOnPagecross = 1;*/ \
|
||||
regs.a |= READ; \
|
||||
SETNZ(regs.a)
|
||||
#define PHA PUSH(regs.a)
|
||||
|
@ -471,18 +456,18 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
SETNZ(regs.x)
|
||||
#define PLY regs.y = POP; \
|
||||
SETNZ(regs.y)
|
||||
#define RLA bSlowerOnPagecross = 0; \
|
||||
#define RLA /*bSlowerOnPagecross = 0;*/ \
|
||||
val = (READ << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
WRITE(val) \
|
||||
regs.a &= val; \
|
||||
SETNZ(regs.a)
|
||||
#define ROL_NMOS bSlowerOnPagecross = 0; \
|
||||
#define ROL_NMOS /*bSlowerOnPagecross = 0;*/ \
|
||||
val = (READ << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define ROL_CMOS bSlowerOnPagecross = 1; \
|
||||
#define ROL_CMOS /*bSlowerOnPagecross = 1;*/ \
|
||||
val = (READ << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
|
@ -491,13 +476,13 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagc = (val > 0xFF); \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a);
|
||||
#define ROR_NMOS bSlowerOnPagecross = 0; \
|
||||
#define ROR_NMOS /*bSlowerOnPagecross = 0;*/ \
|
||||
temp = READ; \
|
||||
val = (temp >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (temp & 1); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define ROR_CMOS bSlowerOnPagecross = 1; \
|
||||
#define ROR_CMOS /*bSlowerOnPagecross = 1;*/ \
|
||||
temp = READ; \
|
||||
val = (temp >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (temp & 1); \
|
||||
|
@ -507,7 +492,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagc = (regs.a & 1); \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a)
|
||||
#define RRA bSlowerOnPagecross = 0; \
|
||||
#define RRA /*bSlowerOnPagecross = 0;*/ \
|
||||
temp = READ; \
|
||||
val = (temp >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (temp & 1); \
|
||||
|
@ -549,10 +534,11 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
flagc = (temp >= val); \
|
||||
regs.x = temp-val; \
|
||||
SETNZ(regs.x)
|
||||
#define SAY bSlowerOnPagecross = 0; \
|
||||
#define SAY /*bSlowerOnPagecross = 0;*/ \
|
||||
val = regs.y & (((base >> 8) + 1) & 0xFF); \
|
||||
ON_PAGECROSS_REPLACE_HI_ADDR \
|
||||
WRITE(val)
|
||||
#define SBC_NMOS bSlowerOnPagecross = 1; \
|
||||
#define SBC_NMOS /*bSlowerOnPagecross = 1;*/ \
|
||||
temp = READ; \
|
||||
temp2 = regs.a - temp - !flagc; \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
|
@ -576,7 +562,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a); \
|
||||
}
|
||||
#define SBC_CMOS bSlowerOnPagecross = 1; \
|
||||
#define SBC_CMOS /*bSlowerOnPagecross = 1;*/ \
|
||||
temp = READ; \
|
||||
flagv = ((regs.a ^ temp) & 0x80); \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
|
@ -622,29 +608,30 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#define SEC flagc = 1;
|
||||
#define SED regs.ps |= AF_DECIMAL;
|
||||
#define SEI regs.ps |= AF_INTERRUPT;
|
||||
#define STA bSlowerOnPagecross = 0; \
|
||||
#define STA /*bSlowerOnPagecross = 0;*/ \
|
||||
WRITE(regs.a)
|
||||
#define STX bSlowerOnPagecross = 0; \
|
||||
#define STX /*bSlowerOnPagecross = 0;*/ \
|
||||
WRITE(regs.x)
|
||||
#define STY bSlowerOnPagecross = 0; \
|
||||
#define STY /*bSlowerOnPagecross = 0;*/ \
|
||||
WRITE(regs.y)
|
||||
#define STZ bSlowerOnPagecross = 0; \
|
||||
#define STZ /*bSlowerOnPagecross = 0;*/ \
|
||||
WRITE(0)
|
||||
#define TAS bSlowerOnPagecross = 0; \
|
||||
#define TAS /*bSlowerOnPagecross = 0;*/ \
|
||||
val = regs.a & regs.x; \
|
||||
regs.sp = 0x100 | val; \
|
||||
val &= (((base >> 8) + 1) & 0xFF); \
|
||||
ON_PAGECROSS_REPLACE_HI_ADDR \
|
||||
WRITE(val)
|
||||
#define TAX regs.x = regs.a; \
|
||||
SETNZ(regs.x)
|
||||
#define TAY regs.y = regs.a; \
|
||||
SETNZ(regs.y)
|
||||
#define TRB bSlowerOnPagecross = 0; \
|
||||
#define TRB /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ; \
|
||||
flagz = !(regs.a & val); \
|
||||
val &= ~regs.a; \
|
||||
WRITE(val)
|
||||
#define TSB bSlowerOnPagecross = 0; \
|
||||
#define TSB /*bSlowerOnPagecross = 0;*/ \
|
||||
val = READ; \
|
||||
flagz = !(regs.a & val); \
|
||||
val |= regs.a; \
|
||||
|
@ -659,7 +646,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#define XAA regs.a = regs.x; \
|
||||
regs.a &= READ; \
|
||||
SETNZ(regs.a)
|
||||
#define XAS bSlowerOnPagecross = 0; \
|
||||
#define XAS /*bSlowerOnPagecross = 0;*/ \
|
||||
val = regs.x & (((base >> 8) + 1) & 0xFF); \
|
||||
ON_PAGECROSS_REPLACE_HI_ADDR \
|
||||
WRITE(val)
|
||||
|
||||
|
|
|
@ -93,6 +93,10 @@ BOOL CPageSound::DlgProcInternal(HWND hWnd, UINT message, WPARAM wparam, LPARAM
|
|||
if (NewSoundcardConfigured(hWnd, wparam, CT_Phasor))
|
||||
InitOptions(hWnd); // re-init
|
||||
break;
|
||||
case IDC_SAM_ENABLE:
|
||||
if (NewSoundcardConfigured(hWnd, wparam, CT_SAM))
|
||||
InitOptions(hWnd); // re-init
|
||||
break;
|
||||
case IDC_SOUNDCARD_DISABLE:
|
||||
if (NewSoundcardConfigured(hWnd, wparam, CT_Empty))
|
||||
InitOptions(hWnd); // re-init
|
||||
|
@ -114,7 +118,11 @@ BOOL CPageSound::DlgProcInternal(HWND hWnd, UINT message, WPARAM wparam, LPARAM
|
|||
SendDlgItemMessage(hWnd,IDC_MB_VOLUME,TBM_SETTICFREQ,10,0);
|
||||
SendDlgItemMessage(hWnd,IDC_MB_VOLUME,TBM_SETPOS,1,MB_GetVolume());
|
||||
|
||||
m_NewCardType = MB_GetSoundcardType(); // Reinit 1st time page is activated (fires before PSN_SETACTIVE)
|
||||
if (g_Slot5 == CT_SAM)
|
||||
m_NewCardType = CT_SAM;
|
||||
else
|
||||
m_NewCardType = MB_GetSoundcardType(); // Reinit 1st time page is activated (fires before PSN_SETACTIVE)
|
||||
|
||||
InitOptions(hWnd);
|
||||
|
||||
break;
|
||||
|
@ -153,6 +161,8 @@ void CPageSound::InitOptions(HWND hWnd)
|
|||
m_nCurrentIDCheckButton = IDC_MB_ENABLE;
|
||||
else if(m_NewCardType == CT_Phasor)
|
||||
m_nCurrentIDCheckButton = IDC_PHASOR_ENABLE;
|
||||
else if(m_NewCardType == CT_SAM)
|
||||
m_nCurrentIDCheckButton = IDC_SAM_ENABLE;
|
||||
else
|
||||
m_nCurrentIDCheckButton = IDC_SOUNDCARD_DISABLE;
|
||||
|
||||
|
@ -168,16 +178,23 @@ void CPageSound::InitOptions(HWND hWnd)
|
|||
|
||||
// Phasor button
|
||||
{
|
||||
const BOOL bEnable = bIsSlot4Empty || Slot4 == CT_MockingboardC;
|
||||
const BOOL bEnable = bIsSlot4Empty || Slot4 == CT_MockingboardC || Slot4 == CT_Phasor;
|
||||
EnableWindow(GetDlgItem(hWnd, IDC_PHASOR_ENABLE), bEnable); // Disable Phasor (slot 4)
|
||||
}
|
||||
|
||||
// Mockingboard button
|
||||
{
|
||||
const BOOL bEnable = (bIsSlot4Empty || Slot4 == CT_Phasor) && bIsSlot5Empty;
|
||||
const BOOL bEnable = (bIsSlot4Empty || Slot4 == CT_Phasor || Slot4 == CT_MockingboardC) &&
|
||||
(bIsSlot5Empty || Slot5 == CT_SAM || Slot5 == CT_MockingboardC);
|
||||
EnableWindow(GetDlgItem(hWnd, IDC_MB_ENABLE), bEnable); // Disable Mockingboard (slot 4 & 5)
|
||||
}
|
||||
|
||||
// SAM button
|
||||
{
|
||||
const BOOL bEnable = bIsSlot5Empty || Slot5 == CT_MockingboardC || Slot5 == CT_SAM;
|
||||
EnableWindow(GetDlgItem(hWnd, IDC_SAM_ENABLE), bEnable); // Disable SAM (slot 5)
|
||||
}
|
||||
|
||||
EnableWindow(GetDlgItem(hWnd, IDC_MB_VOLUME), (m_nCurrentIDCheckButton != IDC_SOUNDCARD_DISABLE) ? TRUE : FALSE);
|
||||
}
|
||||
|
||||
|
@ -191,6 +208,7 @@ bool CPageSound::NewSoundcardConfigured(HWND hWnd, WPARAM wparam, SS_CARDTYPE Ne
|
|||
|
||||
m_NewCardType = NewCardType;
|
||||
|
||||
const SS_CARDTYPE Slot4 = m_PropertySheetHelper.GetConfigNew().m_Slot[4];
|
||||
const SS_CARDTYPE Slot5 = m_PropertySheetHelper.GetConfigNew().m_Slot[5];
|
||||
|
||||
if (NewCardType == CT_MockingboardC)
|
||||
|
@ -201,13 +219,20 @@ bool CPageSound::NewSoundcardConfigured(HWND hWnd, WPARAM wparam, SS_CARDTYPE Ne
|
|||
else if (NewCardType == CT_Phasor)
|
||||
{
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[4] = CT_Phasor;
|
||||
if (Slot5 == CT_MockingboardC)
|
||||
if ((Slot5 == CT_MockingboardC) || (Slot5 == CT_SAM))
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[5] = CT_Empty;
|
||||
}
|
||||
else if (NewCardType == CT_SAM)
|
||||
{
|
||||
if ((Slot4 == CT_MockingboardC) || (Slot4 == CT_Phasor))
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[4] = CT_Empty;
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[5] = CT_SAM;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[4] = CT_Empty;
|
||||
if (Slot5 == CT_MockingboardC)
|
||||
if ((Slot4 == CT_MockingboardC) || (Slot4 == CT_Phasor))
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[4] = CT_Empty;
|
||||
if ((Slot5 == CT_MockingboardC) || (Slot5 == CT_SAM))
|
||||
m_PropertySheetHelper.GetConfigNew().m_Slot[5] = CT_Empty;
|
||||
}
|
||||
|
||||
|
|
|
@ -44,7 +44,7 @@ Input
|
|||
. Mouse WM_USER_RESTART
|
||||
. CP/M WM_USER_RESTART
|
||||
Sound
|
||||
. MB/Phasor/None WM_USER_RESTART
|
||||
. MB/Phasor/SAM/None WM_USER_RESTART
|
||||
Disk
|
||||
. Enhanced disk speed WM_USER_RESTART Why? (used to patch Disk][ f/w - but not anymore)
|
||||
. HDD enable WM_USER_RESTART
|
||||
|
|
|
@ -47,7 +47,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#define ALLOW_INPUT_LOWERCASE 1
|
||||
|
||||
// See /docs/Debugger_Changelog.txt for full details
|
||||
const int DEBUGGER_VERSION = MAKE_VERSION(2,8,0,8);
|
||||
const int DEBUGGER_VERSION = MAKE_VERSION(2,8,0,12);
|
||||
|
||||
|
||||
// Public _________________________________________________________________________________________
|
||||
|
@ -555,8 +555,6 @@ Update_t CmdBookmarkClear (int nArgs)
|
|||
{
|
||||
int iBookmark = 0;
|
||||
|
||||
bool bClearAll = false;
|
||||
|
||||
int iArg;
|
||||
for (iArg = 1; iArg <= nArgs; iArg++ )
|
||||
{
|
||||
|
@ -730,7 +728,7 @@ Update_t CmdProfile (int nArgs)
|
|||
{
|
||||
if (! nArgs)
|
||||
{
|
||||
sprintf( g_aArgs[ 1 ].sArg, g_aParameters[ PARAM_RESET ].m_sName );
|
||||
sprintf( g_aArgs[ 1 ].sArg, "%s", g_aParameters[ PARAM_RESET ].m_sName );
|
||||
nArgs = 1;
|
||||
}
|
||||
|
||||
|
@ -938,8 +936,6 @@ Update_t CmdBreakOpcode (int nArgs) // Breakpoint IFF Full-speed!
|
|||
// Show what the current break opcode is
|
||||
wsprintf( sText, TEXT("%s full speed Break on Opcode: None")
|
||||
, sAction
|
||||
, g_iDebugBreakOnOpcode
|
||||
, g_aOpcodes65C02[ g_iDebugBreakOnOpcode ].sMnemonic
|
||||
);
|
||||
else
|
||||
// Show what the current break opcode is
|
||||
|
@ -1180,8 +1176,6 @@ Update_t CmdBreakpointAddSmart (int nArgs)
|
|||
CmdBreakpointAddMem( nArgs );
|
||||
return UPDATE_BREAKPOINTS;
|
||||
}
|
||||
|
||||
return UPDATE_CONSOLE_DISPLAY;
|
||||
}
|
||||
|
||||
|
||||
|
@ -1195,7 +1189,6 @@ Update_t CmdBreakpointAddReg (int nArgs)
|
|||
|
||||
BreakpointSource_t iSrc = BP_SRC_REG_PC;
|
||||
BreakpointOperator_t iCmp = BP_OP_EQUAL ;
|
||||
int nLen = 1;
|
||||
|
||||
bool bHaveSrc = false;
|
||||
bool bHaveCmp = false;
|
||||
|
@ -1204,7 +1197,6 @@ Update_t CmdBreakpointAddReg (int nArgs)
|
|||
int iParamCmp;
|
||||
|
||||
int nFound;
|
||||
bool bAdded = false;
|
||||
|
||||
int iArg = 0;
|
||||
while (iArg++ < nArgs)
|
||||
|
@ -1352,14 +1344,12 @@ Update_t CmdBreakpointAddPC (int nArgs)
|
|||
g_aArgs[1].nValue = g_nDisasmCurAddress;
|
||||
}
|
||||
|
||||
bool bHaveSrc = false;
|
||||
bool bHaveCmp = false;
|
||||
|
||||
// int iParamSrc;
|
||||
int iParamCmp;
|
||||
|
||||
int nFound = 0;
|
||||
bool bAdded = false;
|
||||
|
||||
int iArg = 0;
|
||||
while (iArg++ < nArgs)
|
||||
|
@ -1413,14 +1403,10 @@ Update_t CmdBreakpointAddMem (int nArgs)
|
|||
BreakpointSource_t iSrc = BP_SRC_MEM_1;
|
||||
BreakpointOperator_t iCmp = BP_OP_EQUAL ;
|
||||
|
||||
bool bAdded = false;
|
||||
|
||||
int iArg = 0;
|
||||
|
||||
while (iArg++ < nArgs)
|
||||
{
|
||||
char *sArg = g_aArgs[iArg].sArg;
|
||||
|
||||
if (g_aArgs[iArg].bType & TYPE_OPERATOR)
|
||||
{
|
||||
return Help_Arg_1( CMD_BREAKPOINT_ADD_MEM );
|
||||
|
@ -1941,7 +1927,7 @@ Update_t CmdTraceFile (int nArgs)
|
|||
fclose( g_hTraceFile );
|
||||
g_hTraceFile = NULL;
|
||||
|
||||
sprintf( sText, "Trace stopped." );
|
||||
_snprintf( sText, sizeof(sText), "Trace stopped." );
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1961,16 +1947,17 @@ Update_t CmdTraceFile (int nArgs)
|
|||
|
||||
if (g_hTraceFile)
|
||||
{
|
||||
sprintf( sText, "Trace started: %s", sFilePath );
|
||||
_snprintf( sText, sizeof(sText), "Trace started: %s", sFilePath );
|
||||
|
||||
g_bTraceHeader = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
sprintf( sText, "Trace ERROR: %s", sFilePath );
|
||||
_snprintf( sText, sizeof(sText), "Trace ERROR: %s", sFilePath );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
sText[sizeof(sText)-1] = 0; // _snprintf needs null if string was longer than buffer
|
||||
ConsoleBufferPush( sText );
|
||||
ConsoleBufferToDisplay();
|
||||
|
||||
|
@ -2299,7 +2286,7 @@ void ConfigSave_PrepareHeader ( const Parameters_e eCategory, const Commands_e e
|
|||
sprintf( sText, "%s %s = %s\n"
|
||||
, g_aTokens[ TOKEN_COMMENT_EOL ].sToken
|
||||
, g_aParameters[ PARAM_CATEGORY ].m_sName
|
||||
, g_aParameters[ eCategory ]
|
||||
, g_aParameters[ eCategory ].m_sName
|
||||
);
|
||||
g_ConfigState.PushLine( sText );
|
||||
|
||||
|
@ -3621,7 +3608,8 @@ Update_t CmdDisk ( int nArgs)
|
|||
|
||||
// check for info command
|
||||
int iParam = 0;
|
||||
int nInfoFound = FindParam( g_aArgs[ 1 ].sArg, MATCH_EXACT, iParam, _PARAM_DISK_BEGIN, _PARAM_DISK_END );
|
||||
FindParam( g_aArgs[ 1 ].sArg, MATCH_EXACT, iParam, _PARAM_DISK_BEGIN, _PARAM_DISK_END );
|
||||
|
||||
if (iParam == PARAM_DISK_INFO)
|
||||
{
|
||||
if (nArgs > 2)
|
||||
|
@ -3777,7 +3765,6 @@ Update_t CmdMemoryCompare (int nArgs )
|
|||
return Help_Arg_1( CMD_MEMORY_COMPARE );
|
||||
|
||||
WORD nSrcAddr = g_aArgs[1].nValue;
|
||||
WORD nLenByte = 0;
|
||||
WORD nDstAddr = g_aArgs[3].nValue;
|
||||
|
||||
WORD nSrcSymAddr;
|
||||
|
@ -4216,20 +4203,71 @@ Update_t CmdMemoryLoad (int nArgs)
|
|||
bBankSpecified = false;
|
||||
}
|
||||
|
||||
if (g_aArgs[ iArgComma1 ].eToken != TOKEN_COMMA)
|
||||
return Help_Arg_1( CMD_MEMORY_LOAD );
|
||||
struct KnownFileType_t
|
||||
{
|
||||
char *pExtension;
|
||||
int nAddress;
|
||||
int nLength;
|
||||
};
|
||||
|
||||
const KnownFileType_t aFileTypes[] =
|
||||
{
|
||||
{ "" , 0, 0 } // n/a
|
||||
,{ ".hgr" , 0x2000, 0x2000 }
|
||||
,{ ".hgr2", 0x4000, 0x2000 }
|
||||
// TODO: extension ".dhgr", ".dhgr2"
|
||||
};
|
||||
const int nFileTypes = sizeof( aFileTypes ) / sizeof( KnownFileType_t );
|
||||
const KnownFileType_t *pFileType = NULL;
|
||||
|
||||
char *pFileName = g_aArgs[ 1 ].sArg;
|
||||
int nLen = strlen( pFileName );
|
||||
char *pEnd = pFileName + + nLen - 1;
|
||||
while( pEnd > pFileName )
|
||||
{
|
||||
if( *pEnd == '.' )
|
||||
{
|
||||
for( int i = 1; i < nFileTypes; i++ )
|
||||
{
|
||||
if( strcmp( pEnd, aFileTypes[i].pExtension ) == 0 )
|
||||
{
|
||||
pFileType = &aFileTypes[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if( pFileType )
|
||||
break;
|
||||
|
||||
pEnd--;
|
||||
}
|
||||
|
||||
if( !pFileType )
|
||||
if (g_aArgs[ iArgComma1 ].eToken != TOKEN_COMMA)
|
||||
return Help_Arg_1( CMD_MEMORY_LOAD );
|
||||
|
||||
TCHAR sLoadSaveFilePath[ MAX_PATH ];
|
||||
_tcscpy( sLoadSaveFilePath, g_sCurrentDir ); // TODO: g_sDebugDir
|
||||
|
||||
WORD nAddressStart;
|
||||
WORD nAddress2 = 0;
|
||||
WORD nAddressEnd = 0;
|
||||
int nAddressLen = 0;
|
||||
WORD nAddressStart = 0;
|
||||
WORD nAddress2 = 0;
|
||||
WORD nAddressEnd = 0;
|
||||
int nAddressLen = 0;
|
||||
|
||||
RangeType_t eRange;
|
||||
eRange = Range_Get( nAddressStart, nAddress2, iArgAddress );
|
||||
if (nArgs > iArgComma2)
|
||||
if( pFileType )
|
||||
{
|
||||
nAddressStart = pFileType->nAddress;
|
||||
nAddressLen = pFileType->nLength;
|
||||
nAddressEnd = pFileType->nLength + nAddressLen;
|
||||
}
|
||||
|
||||
RangeType_t eRange = RANGE_MISSING_ARG_2;
|
||||
|
||||
if (g_aArgs[ iArgComma1 ].eToken == TOKEN_COMMA)
|
||||
eRange = Range_Get( nAddressStart, nAddress2, iArgAddress );
|
||||
|
||||
if( nArgs > iArgComma2 )
|
||||
{
|
||||
if (eRange == RANGE_MISSING_ARG_2)
|
||||
{
|
||||
|
@ -4245,7 +4283,7 @@ Update_t CmdMemoryLoad (int nArgs)
|
|||
|
||||
if (bHaveFileName)
|
||||
{
|
||||
_tcscpy( g_sMemoryLoadSaveFileName, g_aArgs[ 1 ].sArg );
|
||||
_tcscpy( g_sMemoryLoadSaveFileName, pFileName );
|
||||
}
|
||||
_tcscat( sLoadSaveFilePath, g_sMemoryLoadSaveFileName );
|
||||
|
||||
|
@ -4275,7 +4313,9 @@ Update_t CmdMemoryLoad (int nArgs)
|
|||
size_t nRead = fread( pMemBankBase+nAddressStart, nAddressLen, 1, hFile );
|
||||
if (nRead == 1)
|
||||
{
|
||||
ConsoleBufferPush( TEXT( "Loaded." ) );
|
||||
char text[ 128 ];
|
||||
sprintf( text, "Loaded @ A$%04X,L$%04X", nAddressStart, nAddressLen );
|
||||
ConsoleBufferPush( text );
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -5537,6 +5577,7 @@ Update_t CmdOutputPrintf (int nArgs)
|
|||
{
|
||||
case '\\':
|
||||
eThis = PS_ESCAPE;
|
||||
break;
|
||||
case '%':
|
||||
eThis = PS_TYPE;
|
||||
break;
|
||||
|
@ -6585,7 +6626,6 @@ Update_t CmdWindowViewCode (int nArgs)
|
|||
Update_t CmdWindowViewConsole (int nArgs)
|
||||
{
|
||||
return _CmdWindowViewFull( WINDOW_CONSOLE );
|
||||
return UPDATE_ALL;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
@ -6607,14 +6647,12 @@ Update_t CmdWindowViewOutput (int nArgs)
|
|||
Update_t CmdWindowViewSource (int nArgs)
|
||||
{
|
||||
return _CmdWindowViewFull( WINDOW_CONSOLE );
|
||||
return UPDATE_ALL;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
Update_t CmdWindowViewSymbols (int nArgs)
|
||||
{
|
||||
return _CmdWindowViewFull( WINDOW_CONSOLE );
|
||||
return UPDATE_ALL;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
@ -7329,7 +7367,7 @@ void OutputTraceLine ()
|
|||
(unsigned)regs.sp,
|
||||
(char*) sFlags
|
||||
, sDisassembly
|
||||
, sTarget
|
||||
//, sTarget // TODO: Show target?
|
||||
);
|
||||
}
|
||||
}
|
||||
|
@ -8876,7 +8914,7 @@ void DebuggerMouseClick( int x, int y )
|
|||
DebugDisplay( UPDATE_DISASM );
|
||||
}
|
||||
else // AD 00 00
|
||||
if ((cx > 4) & (cx <= 13))
|
||||
if ((cx > 4) && (cx <= 13))
|
||||
{
|
||||
g_bConfigDisasmOpcodesView ^= true;
|
||||
DebugDisplay( UPDATE_DISASM );
|
||||
|
|
|
@ -565,7 +565,6 @@ bool _6502_GetStackReturnAddress ( WORD & nAddress_ )
|
|||
|
||||
if (nStack <= (_6502_STACK_END - 1))
|
||||
{
|
||||
nAddress_ = 0;
|
||||
nAddress_ = (unsigned)*(LPBYTE)(mem + nStack);
|
||||
nStack++;
|
||||
|
||||
|
|
|
@ -279,8 +279,9 @@ bool ConsoleBufferPush ( const char * pText )
|
|||
const char *pSrc = pText;
|
||||
conchar_t *pDst = & g_aConsoleBuffer[ g_nConsoleBuffer ][ 0 ];
|
||||
|
||||
while ((x < CONSOLE_WIDTH) && (c = *pSrc))
|
||||
while ((x < CONSOLE_WIDTH) && *pSrc)
|
||||
{
|
||||
c = *pSrc;
|
||||
if ((c == '\n') || (x == (CONSOLE_WIDTH - 1)))
|
||||
{
|
||||
*pDst = 0;
|
||||
|
|
|
@ -1223,7 +1223,7 @@ void DrawBreakpoints ( int line )
|
|||
//===========================================================================
|
||||
int GetConsoleLineHeightPixels()
|
||||
{
|
||||
int nHeight = nHeight = g_aFontConfig[ FONT_CONSOLE ]._nFontHeight; // _nLineHeight; // _nFontHeight;
|
||||
int nHeight = g_aFontConfig[ FONT_CONSOLE ]._nFontHeight; // _nLineHeight; // _nFontHeight;
|
||||
/*
|
||||
if (g_iFontSpacing == FONT_SPACING_CLASSIC)
|
||||
{
|
||||
|
|
|
@ -126,7 +126,7 @@ Update_t Help_Arg_1( int iCommandHelp )
|
|||
{
|
||||
_Arg_1( iCommandHelp );
|
||||
|
||||
wsprintf( g_aArgs[ 1 ].sArg, g_aCommands[ iCommandHelp ].m_sName ); // .3 Fixed: Help_Arg_1() now copies command name into arg.name
|
||||
wsprintf( g_aArgs[ 1 ].sArg, "%s", g_aCommands[ iCommandHelp ].m_sName ); // .3 Fixed: Help_Arg_1() now copies command name into arg.name
|
||||
|
||||
return CmdHelpSpecific( 1 );
|
||||
}
|
||||
|
@ -669,49 +669,49 @@ Update_t CmdHelpSpecific (int nArgs)
|
|||
|
||||
// HACK: Major kludge to display category!!!
|
||||
if (iCmd <= CMD_UNASSEMBLE)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_CPU ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_CPU ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_BOOKMARK_SAVE)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_BOOKMARKS ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_BOOKMARKS ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_BREAKPOINT_SAVE)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_BREAKPOINTS ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_BREAKPOINTS ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_CONFIG_SAVE)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_CONFIG ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_CONFIG ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_CURSOR_PAGE_DOWN_4K)
|
||||
wsprintf( sCategory, "Scrolling" );
|
||||
else
|
||||
if (iCmd <= CMD_FLAG_SET_N)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_FLAGS ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_FLAGS ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_MOTD)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_HELP ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_HELP ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_MEMORY_FILL)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_MEMORY ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_MEMORY ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_OUTPUT_RUN)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_OUTPUT ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_OUTPUT ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_SYNC)
|
||||
wsprintf( sCategory, "Source" );
|
||||
else
|
||||
if (iCmd <= CMD_SYMBOLS_LIST)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_SYMBOLS ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_SYMBOLS ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_VIEW_DHGR2)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_VIEW ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_VIEW ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_WATCH_SAVE)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_WATCHES ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_WATCHES ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_WINDOW_OUTPUT)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_WINDOW ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_WINDOW ].m_sName );
|
||||
else
|
||||
if (iCmd <= CMD_ZEROPAGE_POINTER_SAVE)
|
||||
wsprintf( sCategory, g_aParameters[ PARAM_CAT_ZEROPAGE ].m_sName );
|
||||
wsprintf( sCategory, "%s", g_aParameters[ PARAM_CAT_ZEROPAGE ].m_sName );
|
||||
else
|
||||
wsprintf( sCategory, "Unknown!" );
|
||||
|
||||
|
|
248
source/Disk.cpp
248
source/Disk.cpp
|
@ -4,7 +4,7 @@ AppleWin : An Apple //e emulator for Windows
|
|||
Copyright (C) 1994-1996, Michael O'Brien
|
||||
Copyright (C) 1999-2001, Oliver Schmidt
|
||||
Copyright (C) 2002-2005, Tom Charlesworth
|
||||
Copyright (C) 2006-2014, Tom Charlesworth, Michael Pohoreski
|
||||
Copyright (C) 2006-2015, Tom Charlesworth, Michael Pohoreski, Nick Westgate
|
||||
|
||||
AppleWin is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
|
@ -24,6 +24,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
/* Description: Disk
|
||||
*
|
||||
* Author: Various
|
||||
*
|
||||
* In comments, UTA2E is an abbreviation for a reference to "Understanding the Apple //e" by James Sather
|
||||
*/
|
||||
|
||||
#include "StdAfx.h"
|
||||
|
@ -34,6 +36,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#include "Disk.h"
|
||||
#include "DiskImage.h"
|
||||
#include "Frame.h"
|
||||
#include "Log.h"
|
||||
#include "Memory.h"
|
||||
#include "Registry.h"
|
||||
#include "Video.h"
|
||||
|
@ -41,6 +44,10 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#include "..\resource\resource.h"
|
||||
|
||||
#define LOG_DISK_ENABLED 0
|
||||
#define LOG_DISK_TRACKS 1
|
||||
#define LOG_DISK_MOTOR 0
|
||||
#define LOG_DISK_PHASES 0
|
||||
#define LOG_DISK_NIBBLES 0
|
||||
|
||||
// __VA_ARGS__ not supported on MSVC++ .NET 7.x
|
||||
#if (LOG_DISK_ENABLED)
|
||||
|
@ -106,6 +113,7 @@ static BOOL diskaccessed = 0;
|
|||
static Disk_t g_aFloppyDisk[NUM_DRIVES];
|
||||
static BYTE floppylatch = 0;
|
||||
static BOOL floppymotoron = 0;
|
||||
static BOOL floppyloadmode = 0; // for efficiency this is not used; it's extremely unlikely to affect emulation (nickw)
|
||||
static BOOL floppywritemode = 0;
|
||||
static WORD phases = 0; // state bits for stepper magnet phases 0 - 3
|
||||
static bool g_bSaveDiskImage = true; // Save the DiskImage name to Registry
|
||||
|
@ -147,13 +155,21 @@ char* DiskGetCurrentState(void)
|
|||
else if (floppywritemode)
|
||||
{
|
||||
if (g_aFloppyDisk[currdrive].bWriteProtected)
|
||||
return "Writing";
|
||||
else
|
||||
return "Writing (write protected)";
|
||||
else
|
||||
return "Writing";
|
||||
}
|
||||
else
|
||||
{
|
||||
return "Reading";
|
||||
/*if (floppyloadmode)
|
||||
{
|
||||
if (g_aFloppyDisk[currdrive].bWriteProtected)
|
||||
return "Reading write protect state (write protected)";
|
||||
else
|
||||
return "Reading write protect state (not write protected)";
|
||||
}
|
||||
else*/
|
||||
return "Reading";
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -283,8 +299,9 @@ static void ReadTrack(const int iDrive)
|
|||
|
||||
if (pFloppy->trackimage && pFloppy->imagehandle)
|
||||
{
|
||||
LOG_DISK("read track %2X%s\r", pFloppy->track, (pFloppy->phase & 1) ? ".5" : "");
|
||||
|
||||
#if LOG_DISK_TRACKS
|
||||
LOG_DISK("track $%02X%s read\r\n", pFloppy->track, (pFloppy->phase & 1) ? ".5" : " ");
|
||||
#endif
|
||||
ImageReadTrack(
|
||||
pFloppy->imagehandle,
|
||||
pFloppy->track,
|
||||
|
@ -340,12 +357,17 @@ static void WriteTrack(const int iDrive)
|
|||
return;
|
||||
|
||||
if (pFloppy->trackimage && pFloppy->imagehandle)
|
||||
{
|
||||
#if LOG_DISK_TRACKS
|
||||
LOG_DISK("track $%02X%s write\r\n", pFloppy->track, (pFloppy->phase & 0) ? ".5" : " "); // TODO: hard-coded to whole tracks - see below (nickw)
|
||||
#endif
|
||||
ImageWriteTrack(
|
||||
pFloppy->imagehandle,
|
||||
pFloppy->track,
|
||||
pFloppy->phase,
|
||||
pFloppy->phase, // TODO: this should never be used; it's the current phase (half-track), not that of the track to be written (nickw)
|
||||
pFloppy->trackimage,
|
||||
pFloppy->nibbles );
|
||||
pFloppy->nibbles);
|
||||
}
|
||||
|
||||
pFloppy->trackimagedirty = 0;
|
||||
}
|
||||
|
@ -366,34 +388,34 @@ void DiskBoot(void)
|
|||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskControlMotor(WORD, WORD address, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
static void __stdcall DiskControlMotor(WORD, WORD address, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
{
|
||||
floppymotoron = address & 1;
|
||||
#if LOG_DISK_MOTOR
|
||||
LOG_DISK("motor %s\r\n", (floppymotoron) ? "on" : "off");
|
||||
#endif
|
||||
CheckSpinning();
|
||||
return MemReadFloatingBus(1, uExecutedCycles); // TC-TODO: Check b7 always set
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskControlStepper(WORD, WORD address, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
static void __stdcall DiskControlStepper(WORD, WORD address, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
{
|
||||
Disk_t * fptr = &g_aFloppyDisk[currdrive];
|
||||
#if 1
|
||||
int phase = (address >> 1) & 3;
|
||||
int phase = (address >> 1) & 3;
|
||||
int phase_bit = (1 << phase);
|
||||
|
||||
#if 1
|
||||
// update the magnet states
|
||||
if (address & 1)
|
||||
{
|
||||
// phase on
|
||||
phases |= phase_bit;
|
||||
LOG_DISK("track %02X phases %X phase %d on address $C0E%X\r", fptr->phase, phases, phase, address & 0xF);
|
||||
}
|
||||
else
|
||||
{
|
||||
// phase off
|
||||
phases &= ~phase_bit;
|
||||
LOG_DISK("track %02X phases %X phase %d off address $C0E%X\r", fptr->phase, phases, phase, address & 0xF);
|
||||
}
|
||||
|
||||
// check for any stepping effect from a magnet
|
||||
|
@ -414,7 +436,6 @@ static BYTE __stdcall DiskControlStepper(WORD, WORD address, BYTE, BYTE, ULONG u
|
|||
const int nNumTracksInImage = ImageGetNumTracks(fptr->imagehandle);
|
||||
const int newtrack = (nNumTracksInImage == 0) ? 0
|
||||
: MIN(nNumTracksInImage-1, fptr->phase >> 1); // (round half tracks down)
|
||||
LOG_DISK("newtrack %2X%s\r", newtrack, (fptr->phase & 1) ? ".5" : "");
|
||||
if (newtrack != fptr->track)
|
||||
{
|
||||
if (fptr->trackimage && fptr->trackimagedirty)
|
||||
|
@ -429,31 +450,21 @@ static BYTE __stdcall DiskControlStepper(WORD, WORD address, BYTE, BYTE, ULONG u
|
|||
// https://github.com/AppleWin/AppleWin/issues/201
|
||||
FrameDrawDiskStatus( (HDC)0 );
|
||||
}
|
||||
#else // Old 1.13.1 code for Chessmaster 2000 to work! (see bug#18109)
|
||||
const int nNumTracksInImage = ImageGetNumTracks(fptr->imagehandle);
|
||||
if (address & 1) {
|
||||
int phase = (address >> 1) & 3;
|
||||
int direction = 0;
|
||||
if (phase == ((fptr->phase+1) & 3))
|
||||
direction = 1;
|
||||
if (phase == ((fptr->phase+3) & 3))
|
||||
direction = -1;
|
||||
if (direction) {
|
||||
fptr->phase = MAX(0,MIN(79,fptr->phase+direction));
|
||||
if (!(fptr->phase & 1)) {
|
||||
int newtrack = MIN(nNumTracksInImage-1,fptr->phase >> 1);
|
||||
if (newtrack != fptr->track) {
|
||||
if (fptr->trackimage && fptr->trackimagedirty)
|
||||
WriteTrack(currdrive);
|
||||
fptr->track = newtrack;
|
||||
fptr->trackimagedata = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
// substitute alternate stepping code here to test
|
||||
#endif
|
||||
#if LOG_DISK_PHASES
|
||||
LOG_DISK("track $%02X%s phases %d%d%d%d phase %d %s address $%4X\r\n",
|
||||
fptr->phase >> 1,
|
||||
(fptr->phase & 1) ? ".5" : " ",
|
||||
(phases >> 3) & 1,
|
||||
(phases >> 2) & 1,
|
||||
(phases >> 1) & 1,
|
||||
(phases >> 0) & 1,
|
||||
phase,
|
||||
(address & 1) ? "on " : "off",
|
||||
address);
|
||||
#endif
|
||||
return ((address & 0xF) == 0) ? 0xFF // TC-TODO: Check why $C0E0 only returns 0xFF
|
||||
: MemReadFloatingBus(1, uExecutedCycles); // TC-TODO: Check b7 always set
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
@ -471,13 +482,12 @@ void DiskDestroy(void)
|
|||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskEnable(WORD, WORD address, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
static void __stdcall DiskEnable(WORD, WORD address, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
{
|
||||
currdrive = address & 1;
|
||||
g_aFloppyDisk[!currdrive].spinning = 0;
|
||||
g_aFloppyDisk[!currdrive].writelight = 0;
|
||||
CheckSpinning();
|
||||
return MemReadFloatingBus(uExecutedCycles);
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
@ -762,8 +772,9 @@ bool Disk_IsDriveEmpty(const int iDrive)
|
|||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskReadWrite (WORD programcounter, WORD, BYTE, BYTE, ULONG)
|
||||
static void __stdcall DiskReadWrite(WORD pc, WORD addr, BYTE bWrite, BYTE d, ULONG nCyclesLeft)
|
||||
{
|
||||
/* floppyloadmode = 0; */
|
||||
Disk_t * fptr = &g_aFloppyDisk[currdrive];
|
||||
|
||||
diskaccessed = 1;
|
||||
|
@ -772,32 +783,23 @@ static BYTE __stdcall DiskReadWrite (WORD programcounter, WORD, BYTE, BYTE, ULON
|
|||
ReadTrack(currdrive);
|
||||
|
||||
if (!fptr->trackimagedata)
|
||||
return 0xFF;
|
||||
|
||||
BYTE result = 0;
|
||||
|
||||
if (!floppywritemode || !fptr->bWriteProtected)
|
||||
{
|
||||
if (floppywritemode)
|
||||
{
|
||||
if (floppylatch & 0x80)
|
||||
{
|
||||
*(fptr->trackimage+fptr->byte) = floppylatch;
|
||||
fptr->trackimagedirty = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
result = *(fptr->trackimage+fptr->byte);
|
||||
}
|
||||
floppylatch = 0xFF;
|
||||
return;
|
||||
}
|
||||
|
||||
if (0)
|
||||
{ LOG_DISK("nib %4X = %2X\r", fptr->byte, result); }
|
||||
if (!floppywritemode)
|
||||
{
|
||||
floppylatch = *(fptr->trackimage + fptr->byte);
|
||||
#if LOG_DISK_NIBBLES
|
||||
LOG_DISK("read %4X = %2X\r\n", fptr->byte, floppylatch);
|
||||
#endif
|
||||
}
|
||||
else if ((floppylatch & 0x80) && !fptr->bWriteProtected) // && floppywritemode
|
||||
{
|
||||
*(fptr->trackimage + fptr->byte) = floppylatch;
|
||||
fptr->trackimagedirty = 1;
|
||||
}
|
||||
|
||||
if (++fptr->byte >= fptr->nibbles)
|
||||
fptr->byte = 0;
|
||||
|
@ -807,8 +809,6 @@ static BYTE __stdcall DiskReadWrite (WORD programcounter, WORD, BYTE, BYTE, ULON
|
|||
// NB. Prevent flooding of forcing UI to redraw!!!
|
||||
if( ((fptr->byte) & 0xFF) == 0 )
|
||||
FrameDrawDiskStatus( (HDC)0 );
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
@ -879,24 +879,31 @@ void DiskSelect(const int iDrive)
|
|||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskSetLatchValue(WORD, WORD, BYTE write, BYTE value, ULONG)
|
||||
{
|
||||
if (write)
|
||||
floppylatch = value;
|
||||
return floppylatch;
|
||||
static void __stdcall DiskLoadWriteProtect(WORD, WORD, BYTE write, BYTE value, ULONG) {
|
||||
/* floppyloadmode = 1; */
|
||||
if (!write)
|
||||
{
|
||||
if (floppymotoron && !floppywritemode)
|
||||
{
|
||||
// phase 1 on also forces write protect in the Disk II drive (UTA2E page 9-7) but we don't implement that
|
||||
if (g_aFloppyDisk[currdrive].bWriteProtected)
|
||||
floppylatch |= 0x80;
|
||||
else
|
||||
floppylatch &= 0x7F;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskSetReadMode(WORD, WORD, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
static void __stdcall DiskSetReadMode(WORD, WORD, BYTE, BYTE, ULONG)
|
||||
{
|
||||
floppywritemode = 0;
|
||||
return MemReadFloatingBus(g_aFloppyDisk[currdrive].bWriteProtected, uExecutedCycles);
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
||||
static BYTE __stdcall DiskSetWriteMode(WORD, WORD, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
static void __stdcall DiskSetWriteMode(WORD, WORD, BYTE, BYTE, ULONG uExecutedCycles)
|
||||
{
|
||||
floppywritemode = 1;
|
||||
BOOL modechange = !g_aFloppyDisk[currdrive].writelight;
|
||||
|
@ -906,8 +913,6 @@ static BYTE __stdcall DiskSetWriteMode(WORD, WORD, BYTE, BYTE, ULONG uExecutedCy
|
|||
//FrameRefreshStatus(DRAW_LEDS);
|
||||
FrameDrawDiskLEDS( (HDC)0 );
|
||||
}
|
||||
|
||||
return MemReadFloatingBus(1, uExecutedCycles); // TC-TODO: Check b7 always set
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
|
@ -1002,12 +1007,12 @@ void DiskLoadRom(LPBYTE pCxRomPeripheral, UINT uSlot)
|
|||
|
||||
memcpy(pCxRomPeripheral + uSlot*APPLE_SLOT_SIZE, pData, DISK2_FW_SIZE);
|
||||
|
||||
// NB. We used to disable the track stepping delay in the Disk II controller firmware by
|
||||
// Note: We used to disable the track stepping delay in the Disk II controller firmware by
|
||||
// patching $C64C with $A9,$00,$EA. Now not doing this since:
|
||||
// . Authentic Speed should be authentic
|
||||
// . Enhanced Speed runs emulation unthrottled, so removing the delay has negligible effect
|
||||
// . Patching the firmware breaks the ADC checksum used by "The CIA Files" (Tricky Dick)
|
||||
// . In this case we can patch to compensate for an ADC or EOR checksum but not both
|
||||
// . In this case we can patch to compensate for an ADC or EOR checksum but not both (nickw)
|
||||
|
||||
RegisterIoHandler(uSlot, Disk_IORead, Disk_IOWrite, NULL, NULL, NULL, NULL);
|
||||
|
||||
|
@ -1018,55 +1023,60 @@ void DiskLoadRom(LPBYTE pCxRomPeripheral, UINT uSlot)
|
|||
|
||||
static BYTE __stdcall Disk_IORead(WORD pc, WORD addr, BYTE bWrite, BYTE d, ULONG nCyclesLeft)
|
||||
{
|
||||
addr &= 0xFF;
|
||||
|
||||
switch (addr & 0xf)
|
||||
switch (addr & 0xF)
|
||||
{
|
||||
case 0x0: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x1: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x2: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x3: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x4: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x5: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x6: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x7: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x8: return DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x9: return DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xA: return DiskEnable(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xB: return DiskEnable(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xC: return DiskReadWrite(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xD: return DiskSetLatchValue(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xE: return DiskSetReadMode(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xF: return DiskSetWriteMode(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x0: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x1: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x2: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x3: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x4: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x5: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x6: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x7: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x8: DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x9: DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xA: DiskEnable(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xB: DiskEnable(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xC: DiskReadWrite(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xD: DiskLoadWriteProtect(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xE: DiskSetReadMode(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xF: DiskSetWriteMode(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
// only even addresses return the latch (UTA2E Table 9.1)
|
||||
if (!(addr & 1))
|
||||
return floppylatch;
|
||||
else
|
||||
return MemReadFloatingBus(nCyclesLeft);
|
||||
}
|
||||
|
||||
static BYTE __stdcall Disk_IOWrite(WORD pc, WORD addr, BYTE bWrite, BYTE d, ULONG nCyclesLeft)
|
||||
{
|
||||
addr &= 0xFF;
|
||||
|
||||
switch (addr & 0xf)
|
||||
switch (addr & 0xF)
|
||||
{
|
||||
case 0x0: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x1: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x2: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x3: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x4: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x5: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x6: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x7: return DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x8: return DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x9: return DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xA: return DiskEnable(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xB: return DiskEnable(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xC: return DiskReadWrite(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xD: return DiskSetLatchValue(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xE: return DiskSetReadMode(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xF: return DiskSetWriteMode(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x0: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x1: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x2: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x3: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x4: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x5: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x6: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x7: DiskControlStepper(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x8: DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0x9: DiskControlMotor(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xA: DiskEnable(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xB: DiskEnable(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xC: DiskReadWrite(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xD: DiskLoadWriteProtect(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xE: DiskSetReadMode(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
case 0xF: DiskSetWriteMode(pc, addr, bWrite, d, nCyclesLeft); break;
|
||||
}
|
||||
|
||||
// any address writes the latch via sequencer LD command (74LS323 datasheet)
|
||||
if (floppywritemode /* && floppyloadmode */)
|
||||
{
|
||||
floppylatch = d;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -435,7 +435,7 @@ void CImageBase::DenibblizeTrack(LPBYTE trackimage, SectorOrder_e SectorOrder, i
|
|||
offset = 0;
|
||||
}
|
||||
|
||||
if ((bytenum == 3) && (byteval[1] = 0xAA))
|
||||
if ((bytenum == 3) && (byteval[1] == 0xAA))
|
||||
{
|
||||
int loop = 0;
|
||||
int tempoffset = offset;
|
||||
|
|
|
@ -1317,7 +1317,7 @@ LRESULT CALLBACK FrameWndProc (
|
|||
{
|
||||
RevealCursor();
|
||||
}
|
||||
else if (g_nAppMode == MODE_RUNNING)
|
||||
else if (g_nAppMode == MODE_RUNNING || g_nAppMode == MODE_STEPPING)
|
||||
{
|
||||
if (!sg_Mouse.IsEnabled())
|
||||
{
|
||||
|
@ -1394,7 +1394,7 @@ LRESULT CALLBACK FrameWndProc (
|
|||
DrawCrosshairs(x,y);
|
||||
JoySetPosition(x-viewportx-2, g_nViewportCX-4, y-viewporty-2, g_nViewportCY-4);
|
||||
}
|
||||
else if (sg_Mouse.IsActiveAndEnabled() && (g_nAppMode == MODE_RUNNING))
|
||||
else if (sg_Mouse.IsActiveAndEnabled() && (g_nAppMode == MODE_RUNNING || g_nAppMode == MODE_STEPPING))
|
||||
{
|
||||
if (g_bLastCursorInAppleViewport)
|
||||
break;
|
||||
|
@ -1425,7 +1425,7 @@ LRESULT CALLBACK FrameWndProc (
|
|||
if (wparam == IDEVENT_TIMER_MOUSE)
|
||||
{
|
||||
// NB. Need to check /g_bAppActive/ since WM_TIMER events still occur after AppleWin app has lost focus
|
||||
if (g_bAppActive && sg_Mouse.IsActiveAndEnabled() && (g_nAppMode == MODE_RUNNING))
|
||||
if (g_bAppActive && sg_Mouse.IsActiveAndEnabled() && (g_nAppMode == MODE_RUNNING || g_nAppMode == MODE_STEPPING))
|
||||
{
|
||||
if (!g_bLastCursorInAppleViewport)
|
||||
break;
|
||||
|
@ -2480,7 +2480,6 @@ void FrameSetCursorPosByMousePos()
|
|||
int iY, iMinY, iMaxY;
|
||||
sg_Mouse.GetXY(iX, iMinX, iMaxX, iY, iMinY, iMaxY);
|
||||
|
||||
_ASSERT(iMinX == 0 && iMinY == 0);
|
||||
float fScaleX = (float)(iX-iMinX) / ((float)(iMaxX-iMinX));
|
||||
float fScaleY = (float)(iY-iMinY) / ((float)(iMaxY-iMinY));
|
||||
|
||||
|
@ -2516,7 +2515,6 @@ static void FrameSetCursorPosByMousePos(int x, int y, int dx, int dy, bool bLeav
|
|||
int iX, iMinX, iMaxX;
|
||||
int iY, iMinY, iMaxY;
|
||||
sg_Mouse.GetXY(iX, iMinX, iMaxX, iY, iMinY, iMaxY);
|
||||
_ASSERT(iMinX == 0 && iMinY == 0);
|
||||
|
||||
if (bLeavingAppleScreen)
|
||||
{
|
||||
|
|
|
@ -33,13 +33,13 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
void LogOutput(LPCTSTR format, ...)
|
||||
{
|
||||
TCHAR output[256];
|
||||
TCHAR output[256];
|
||||
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
|
||||
_vsntprintf(output, sizeof(output) - 1, format, args);
|
||||
OutputDebugString(output);
|
||||
_vsntprintf(output, sizeof(output) - 1, format, args);
|
||||
OutputDebugString(output);
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
|
@ -51,11 +51,11 @@ void LogFileOutput(LPCTSTR format, ...)
|
|||
if (!g_fh)
|
||||
return;
|
||||
|
||||
TCHAR output[256];
|
||||
TCHAR output[256];
|
||||
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
|
||||
_vsntprintf(output, sizeof(output) - 1, format, args);
|
||||
fprintf(g_fh, output);
|
||||
_vsntprintf(output, sizeof(output) - 1, format, args);
|
||||
fprintf(g_fh, "%s", output);
|
||||
}
|
||||
|
|
|
@ -24,6 +24,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
/* Description: Memory emulation
|
||||
*
|
||||
* Author: Various
|
||||
*
|
||||
* In comments, UTA2E is an abbreviation for a reference to "Understanding the Apple //e" by James Sather
|
||||
*/
|
||||
|
||||
#include "StdAfx.h"
|
||||
|
@ -41,6 +43,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#include "NoSlotClock.h"
|
||||
#include "ParallelPrinter.h"
|
||||
#include "Registry.h"
|
||||
#include "SAM.h"
|
||||
#include "SerialComms.h"
|
||||
#include "Speaker.h"
|
||||
#include "Tape.h"
|
||||
|
@ -342,7 +345,7 @@ static BYTE __stdcall IORead_C06x(WORD pc, WORD addr, BYTE bWrite, BYTE d, ULONG
|
|||
{
|
||||
static byte CurrentKestroke = 0;
|
||||
CurrentKestroke = KeybGetKeycode();
|
||||
switch (addr & 0xf)
|
||||
switch (addr & 0x7) // address bit 4 is ignored (UTA2E page 7-5)
|
||||
{
|
||||
//In Pravets8A/C if SETMODE (8bit character encoding) is enabled, bit6 in $C060 is 0; Else it is 1
|
||||
//If (CAPS lOCK of Pravets8A/C is on or Shift is pressed) and (MODE is enabled), bit7 in $C000 is 1; Else it is 0
|
||||
|
@ -356,14 +359,6 @@ static BYTE __stdcall IORead_C06x(WORD pc, WORD addr, BYTE bWrite, BYTE d, ULONG
|
|||
case 0x5: return JoyReadPosition(pc, addr, bWrite, d, nCyclesLeft); //$C065 Analog input 1
|
||||
case 0x6: return JoyReadPosition(pc, addr, bWrite, d, nCyclesLeft); //$C066 Analog input 2
|
||||
case 0x7: return JoyReadPosition(pc, addr, bWrite, d, nCyclesLeft); //$C067 Analog input 3
|
||||
case 0x8: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0x9: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xA: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xB: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xC: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xD: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xE: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
case 0xF: return IO_Null(pc, addr, bWrite, d, nCyclesLeft);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -1324,6 +1319,9 @@ void MemInitializeIO(void)
|
|||
{
|
||||
ConfigureSoftcard(pCxRomPeripheral, 5); // $C500 : Z80 card
|
||||
}
|
||||
else
|
||||
if (g_Slot5 == CT_SAM)
|
||||
ConfigureSAM(pCxRomPeripheral, 5); // $C500 : Z80 card
|
||||
|
||||
DiskLoadRom(pCxRomPeripheral, 6); // $C600 : Disk][ f/w
|
||||
HD_Load_Rom(pCxRomPeripheral, 7); // $C700 : HDD f/w
|
||||
|
@ -1429,14 +1427,14 @@ void MemReset()
|
|||
break;
|
||||
|
||||
case MIP_RANDOM:
|
||||
unsigned char random[ 256 + 4 ];
|
||||
unsigned char random[ 256 ];
|
||||
for( iByte = 0x0000; iByte < 0xC000; iByte += 256 )
|
||||
{
|
||||
for( int i = 0; i < 256; i++ )
|
||||
{
|
||||
clock = getRandomTime();
|
||||
random[ i+0 ] ^= (clock >> 0) & 0xFF;
|
||||
random[ i+1 ] ^= (clock >> 11) & 0xFF;
|
||||
random[ (i+0) & 0xFF ] ^= (clock >> 0) & 0xFF;
|
||||
random[ (i+1) & 0xFF ] ^= (clock >> 11) & 0xFF;
|
||||
}
|
||||
|
||||
memcpy( &memmain[ iByte ], random, 256 );
|
||||
|
|
|
@ -829,7 +829,7 @@ static void MB_Update()
|
|||
double fTicksSecs = (double)GetTickCount() / 1000.0;
|
||||
sprintf(szDbg, "%010.3f: [MBUpdt] PC=%08X, WC=%08X, Diff=%08X, Off=%08X, NS=%08X xxx\n", fTicksSecs, dwCurrentPlayCursor, dwCurrentWriteCursor, dwCurrentWriteCursor-dwCurrentPlayCursor, dwByteOffset, nNumSamples);
|
||||
OutputDebugString(szDbg);
|
||||
if (g_fh) fprintf(g_fh, szDbg);
|
||||
if (g_fh) fprintf(g_fh, "%s", szDbg);
|
||||
|
||||
dwByteOffset = dwCurrentWriteCursor;
|
||||
}
|
||||
|
@ -842,7 +842,7 @@ static void MB_Update()
|
|||
double fTicksSecs = (double)GetTickCount() / 1000.0;
|
||||
sprintf(szDbg, "%010.3f: [MBUpdt] PC=%08X, WC=%08X, Diff=%08X, Off=%08X, NS=%08X XXX\n", fTicksSecs, dwCurrentPlayCursor, dwCurrentWriteCursor, dwCurrentWriteCursor-dwCurrentPlayCursor, dwByteOffset, nNumSamples);
|
||||
OutputDebugString(szDbg);
|
||||
if (g_fh) fprintf(g_fh, szDbg);
|
||||
if (g_fh) fprintf(g_fh, "%s", szDbg);
|
||||
|
||||
dwByteOffset = dwCurrentWriteCursor;
|
||||
}
|
||||
|
|
93
source/SAM.cpp
Normal file
93
source/SAM.cpp
Normal file
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
AppleWin : An Apple //e emulator for Windows
|
||||
|
||||
Copyright (C) 1994-1996, Michael O'Brien
|
||||
Copyright (C) 1999-2001, Oliver Schmidt
|
||||
Copyright (C) 2002-2005, Tom Charlesworth
|
||||
Copyright (C) 2006-2007, Tom Charlesworth, Michael Pohoreski
|
||||
|
||||
AppleWin is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
AppleWin is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with AppleWin; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
/*
|
||||
SAM.CPP
|
||||
|
||||
Emulate an 8 bit DAC (eg: SAM card) which writes unsigned byte
|
||||
data written to its IO area to the audio buffer (as used by the speaker).
|
||||
This merges the data with the speaker stream, reducing the volume
|
||||
of the Apple speaker when active.
|
||||
|
||||
Riccardo Macri Mar 2015
|
||||
*/
|
||||
#include "StdAfx.h"
|
||||
|
||||
#include "AppleWin.h"
|
||||
#include "Memory.h"
|
||||
#include "SAM.h"
|
||||
#include "Speaker.h"
|
||||
|
||||
//
|
||||
// Write 8 bit data to speaker. Emulates a "SAM" speech card DAC
|
||||
//
|
||||
|
||||
|
||||
static BYTE __stdcall IOWrite_SAM(WORD pc, WORD addr, BYTE bWrite, BYTE d, ULONG nCyclesLeft)
|
||||
{
|
||||
// Emulate audio from a SAM / 8 bit DAC card
|
||||
// Only supportable if AppleWin is using WAVE output
|
||||
//
|
||||
// This works by using the existing speaker handling but then
|
||||
// replacing the speaker audio with the 8 bit samples from the DAC
|
||||
// before they get sent out to the soundcard buffer, whilst
|
||||
// audio samples are being written to the SAM.
|
||||
//
|
||||
// Whilst very unusual, it is possible to intermingle use of SAM and the apple
|
||||
// speaker. This is crudely supported with g_bQuieterSpeaker making the Apple
|
||||
// speaker produce quieter clicks which will be crudely intermingled
|
||||
// with the SAM data. The mute gets reset after the speaker code detects
|
||||
// silence.
|
||||
|
||||
if (soundtype != SOUND_WAVE)
|
||||
return MemReadFloatingBus(nCyclesLeft);
|
||||
|
||||
// use existing speaker code to bring timing up to date
|
||||
BYTE res = SpkrToggle(pc, addr, bWrite, d, nCyclesLeft);
|
||||
|
||||
// The DAC in the SAM uses unsigned 8 bit samples
|
||||
// The WAV data that g_nSpeakerData is loaded into is a signed short
|
||||
//
|
||||
// We convert unsigned 8 bit to signed by toggling the most significant bit
|
||||
//
|
||||
// SAM card WAV driver SAM WAV
|
||||
// 0xFF 255 0x7f 127 _ FF 7F
|
||||
// 0x81 129 0x01 1 / \
|
||||
// 0x80 128 0x00 0 / \ /80 00
|
||||
// 0x7f 127 0xFF -1 \_/
|
||||
// 0x00 0 0x80 -128 00 80
|
||||
//
|
||||
// SAM is 8 bit, PC WAV is 16 so shift audio to the MSB (<< 8)
|
||||
|
||||
g_nSpeakerData = (d ^ 0x80) << 8;
|
||||
|
||||
// make speaker quieter so eg: a metronome click through the
|
||||
// Apple speaker is softer vs. the analogue SAM output.
|
||||
g_bQuieterSpeaker = true;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
void ConfigureSAM(LPBYTE pCxRomPeripheral, UINT uSlot)
|
||||
{
|
||||
RegisterIoHandler(uSlot, IO_Null, IOWrite_SAM, IO_Null, IO_Null, NULL, NULL);
|
||||
}
|
3
source/SAM.h
Normal file
3
source/SAM.h
Normal file
|
@ -0,0 +1,3 @@
|
|||
#pragma once
|
||||
|
||||
void ConfigureSAM(LPBYTE pCxRomPeripheral, UINT uSlot);
|
|
@ -1048,7 +1048,7 @@ DWORD WINAPI CSuperSerialCard::CommThread(LPVOID lpParameter)
|
|||
sprintf(szDbg, "CommThread: Err=Other (0x%08X): InQueue=0x%08X, OutQueue=0x%08X\n", dwErrors, Stat.cbInQue, Stat.cbOutQue);
|
||||
OutputDebugString(szDbg);
|
||||
if (g_fh)
|
||||
fprintf(g_fh, szDbg);
|
||||
fprintf(g_fh, "%s", szDbg);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
|
|
@ -51,11 +51,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
// their buffers are running low.
|
||||
//
|
||||
|
||||
#define SOUND_NONE 0
|
||||
#define SOUND_DIRECT 1
|
||||
#define SOUND_SMART 2
|
||||
#define SOUND_WAVE 3
|
||||
|
||||
static const unsigned short g_nSPKR_NumChannels = 1;
|
||||
static const DWORD g_dwDSSpkrBufferSize = MAX_SAMPLES * sizeof(short) * g_nSPKR_NumChannels;
|
||||
|
||||
|
@ -66,18 +61,20 @@ static short* g_pSpeakerBuffer = NULL;
|
|||
// Globals (SOUND_WAVE)
|
||||
const short SPKR_DATA_INIT = (short)0x8000;
|
||||
|
||||
static short g_nSpeakerData = SPKR_DATA_INIT;
|
||||
short g_nSpeakerData = SPKR_DATA_INIT;
|
||||
static UINT g_nBufferIdx = 0;
|
||||
|
||||
static short* g_pRemainderBuffer = NULL;
|
||||
static UINT g_nRemainderBufferSize; // Setup in SpkrInitialize()
|
||||
static UINT g_nRemainderBufferIdx; // Setup in SpkrInitialize()
|
||||
|
||||
|
||||
// Application-wide globals:
|
||||
DWORD soundtype = SOUND_WAVE;
|
||||
double g_fClksPerSpkrSample; // Setup in SetClksPerSpkrSample()
|
||||
|
||||
// Allow temporary quietening of speaker (8 bit DAC)
|
||||
bool g_bQuieterSpeaker = false;
|
||||
|
||||
// Globals
|
||||
static DWORD lastcyclenum = 0;
|
||||
static DWORD toggles = 0;
|
||||
|
@ -226,7 +223,7 @@ void SpkrDestroy ()
|
|||
g_pSpeakerBuffer = NULL;
|
||||
g_pRemainderBuffer = NULL;
|
||||
}
|
||||
else
|
||||
else if (soundtype == SOUND_DIRECT || soundtype == SOUND_SMART)
|
||||
{
|
||||
InternalBeep(0,0);
|
||||
}
|
||||
|
@ -328,8 +325,8 @@ void SpkrReset()
|
|||
|
||||
BOOL SpkrSetEmulationType (HWND window, DWORD newtype)
|
||||
{
|
||||
if (soundtype != SOUND_NONE)
|
||||
SpkrDestroy();
|
||||
SpkrDestroy(); // GH#295: Destroy for all types (even SOUND_NONE)
|
||||
|
||||
soundtype = newtype;
|
||||
if (soundtype != SOUND_NONE)
|
||||
SpkrInitialize();
|
||||
|
@ -447,7 +444,21 @@ BYTE __stdcall SpkrToggle (WORD, WORD, BYTE, BYTE, ULONG nCyclesLeft)
|
|||
|
||||
UpdateSpkr();
|
||||
|
||||
g_nSpeakerData = ~g_nSpeakerData;
|
||||
if (g_bQuieterSpeaker)
|
||||
{
|
||||
// quieten the speaker if 8 bit DAC in use
|
||||
if (g_nSpeakerData == (SPKR_DATA_INIT >> 2))
|
||||
g_nSpeakerData = ~g_nSpeakerData;
|
||||
else
|
||||
g_nSpeakerData = SPKR_DATA_INIT>>2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (g_nSpeakerData == SPKR_DATA_INIT)
|
||||
g_nSpeakerData = ~g_nSpeakerData;
|
||||
else
|
||||
g_nSpeakerData = SPKR_DATA_INIT;
|
||||
}
|
||||
}
|
||||
else if (soundtype != SOUND_NONE)
|
||||
{
|
||||
|
@ -875,7 +886,7 @@ static ULONG Spkr_SubmitWaveBuffer(short* pSpeakerBuffer, ULONG nNumSamples)
|
|||
double fTicksSecs = (double)GetTickCount() / 1000.0;
|
||||
sprintf(szDbg, "%010.3f: [Submit] PC=%08X, WC=%08X, Diff=%08X, Off=%08X, NS=%08X XXX\n", fTicksSecs, dwCurrentPlayCursor, dwCurrentWriteCursor, dwCurrentWriteCursor-dwCurrentPlayCursor, dwByteOffset, nNumSamples);
|
||||
OutputDebugString(szDbg);
|
||||
if (g_fh) fprintf(g_fh, szDbg);
|
||||
if (g_fh) fprintf(g_fh, "%s", szDbg);
|
||||
|
||||
dwByteOffset = dwCurrentWriteCursor;
|
||||
nNumSamplesError = 0;
|
||||
|
@ -993,6 +1004,7 @@ static void Spkr_SetActive(bool bActive)
|
|||
// Called by SpkrUpdate() after 0.2s of speaker inactivity
|
||||
g_bSpkrRecentlyActive = false;
|
||||
SpeakerVoice.bRecentlyActive = false;
|
||||
g_bQuieterSpeaker = 0; // undo any muting (for 8 bit DAC)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -1,7 +1,14 @@
|
|||
#pragma once
|
||||
|
||||
#define SOUND_NONE 0
|
||||
#define SOUND_DIRECT 1
|
||||
#define SOUND_SMART 2
|
||||
#define SOUND_WAVE 3
|
||||
|
||||
extern DWORD soundtype;
|
||||
extern double g_fClksPerSpkrSample;
|
||||
extern bool g_bQuieterSpeaker;
|
||||
extern short g_nSpeakerData;
|
||||
|
||||
void SpkrDestroy ();
|
||||
void SpkrInitialize ();
|
||||
|
|
|
@ -24,6 +24,10 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <time.h>
|
||||
#if _MSC_VER >= 1600 // <stdint.h> supported from VS2010 (cl.exe v16.00)
|
||||
#include <stdint.h> // cleanup WORD DWORD -> uint16_t uint32_t
|
||||
#else
|
||||
#endif
|
||||
|
||||
#include <windows.h>
|
||||
#include <winuser.h> // WM_MOUSEWHEEL
|
||||
|
|
|
@ -24,8 +24,9 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
/* Description: This module is created for emulation of the 8bit character mode (mode 1) switch,
|
||||
* which is located in $c060, and so far does not intend to emulate a tape device.
|
||||
*
|
||||
*
|
||||
* Author: Various
|
||||
*
|
||||
* In comments, UTA2E is an abbreviation for a reference to "Understanding the Apple //e" by James Sather
|
||||
*/
|
||||
|
||||
#include "StdAfx.h"
|
||||
|
@ -77,7 +78,7 @@ BYTE __stdcall TapeRead(WORD, WORD address, BYTE, BYTE, ULONG nCyclesLeft)
|
|||
return C060;
|
||||
}
|
||||
|
||||
return (1<<7) | (MemReadFloatingBus(nCyclesLeft) & 0x7F); // Keep high-bit fixed (since TAPEIN isn't supported)
|
||||
return MemReadFloatingBus(1, nCyclesLeft); // TAPEIN has high bit 1 when input is low or not connected (UTA2E page 7-5, 7-6)
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
1116
test/TestCPU6502/TestCPU6502.cpp
Normal file
1116
test/TestCPU6502/TestCPU6502.cpp
Normal file
File diff suppressed because it is too large
Load Diff
205
test/TestCPU6502/TestCPU6502.vcproj
Normal file
205
test/TestCPU6502/TestCPU6502.vcproj
Normal file
|
@ -0,0 +1,205 @@
|
|||
<?xml version="1.0" encoding="Windows-1252"?>
|
||||
<VisualStudioProject
|
||||
ProjectType="Visual C++"
|
||||
Version="9.00"
|
||||
Name="TestCPU6502"
|
||||
ProjectGUID="{2CC8CA9F-E37E-41A4-BFAD-77E54EB783A2}"
|
||||
RootNamespace="TestCPU6502"
|
||||
Keyword="Win32Proj"
|
||||
TargetFrameworkVersion="196613"
|
||||
>
|
||||
<Platforms>
|
||||
<Platform
|
||||
Name="Win32"
|
||||
/>
|
||||
</Platforms>
|
||||
<ToolFiles>
|
||||
</ToolFiles>
|
||||
<Configurations>
|
||||
<Configuration
|
||||
Name="Debug|Win32"
|
||||
OutputDirectory="$(SolutionDir)$(ConfigurationName)"
|
||||
IntermediateDirectory="$(ConfigurationName)"
|
||||
ConfigurationType="1"
|
||||
CharacterSet="1"
|
||||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXMLDataGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCWebServiceProxyGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCMIDLTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
Optimization="0"
|
||||
PreprocessorDefinitions="WIN32;_DEBUG;_CONSOLE"
|
||||
MinimalRebuild="true"
|
||||
BasicRuntimeChecks="3"
|
||||
RuntimeLibrary="3"
|
||||
UsePrecompiledHeader="2"
|
||||
WarningLevel="3"
|
||||
DebugInformationFormat="4"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManagedResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPreLinkEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCLinkerTool"
|
||||
LinkIncremental="2"
|
||||
GenerateDebugInformation="true"
|
||||
SubSystem="1"
|
||||
TargetMachine="1"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCALinkTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManifestTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXDCMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCBscMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCFxCopTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCAppVerifierTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPostBuildEventTool"
|
||||
/>
|
||||
</Configuration>
|
||||
<Configuration
|
||||
Name="Release|Win32"
|
||||
OutputDirectory="$(SolutionDir)$(ConfigurationName)"
|
||||
IntermediateDirectory="$(ConfigurationName)"
|
||||
ConfigurationType="1"
|
||||
CharacterSet="1"
|
||||
WholeProgramOptimization="1"
|
||||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXMLDataGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCWebServiceProxyGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCMIDLTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
Optimization="2"
|
||||
EnableIntrinsicFunctions="true"
|
||||
PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE"
|
||||
RuntimeLibrary="2"
|
||||
EnableFunctionLevelLinking="true"
|
||||
UsePrecompiledHeader="2"
|
||||
WarningLevel="3"
|
||||
DebugInformationFormat="3"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManagedResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPreLinkEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCLinkerTool"
|
||||
LinkIncremental="1"
|
||||
GenerateDebugInformation="true"
|
||||
SubSystem="1"
|
||||
OptimizeReferences="2"
|
||||
EnableCOMDATFolding="2"
|
||||
TargetMachine="1"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCALinkTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManifestTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXDCMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCBscMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCFxCopTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCAppVerifierTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPostBuildEventTool"
|
||||
/>
|
||||
</Configuration>
|
||||
</Configurations>
|
||||
<References>
|
||||
</References>
|
||||
<Files>
|
||||
<Filter
|
||||
Name="Source Files"
|
||||
Filter="cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx"
|
||||
UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"
|
||||
>
|
||||
<File
|
||||
RelativePath=".\stdafx.cpp"
|
||||
>
|
||||
<FileConfiguration
|
||||
Name="Debug|Win32"
|
||||
>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
UsePrecompiledHeader="1"
|
||||
/>
|
||||
</FileConfiguration>
|
||||
<FileConfiguration
|
||||
Name="Release|Win32"
|
||||
>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
UsePrecompiledHeader="1"
|
||||
/>
|
||||
</FileConfiguration>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\stdafx.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\TestCPU6502.cpp"
|
||||
>
|
||||
</File>
|
||||
</Filter>
|
||||
</Files>
|
||||
<Globals>
|
||||
</Globals>
|
||||
</VisualStudioProject>
|
8
test/TestCPU6502/stdafx.cpp
Normal file
8
test/TestCPU6502/stdafx.cpp
Normal file
|
@ -0,0 +1,8 @@
|
|||
// stdafx.cpp : source file that includes just the standard includes
|
||||
// TestCPU6502.pch will be the pre-compiled header
|
||||
// stdafx.obj will contain the pre-compiled type information
|
||||
|
||||
#include "stdafx.h"
|
||||
|
||||
// TODO: reference any additional headers you need in STDAFX.H
|
||||
// and not in this file
|
11
test/TestCPU6502/stdafx.h
Normal file
11
test/TestCPU6502/stdafx.h
Normal file
|
@ -0,0 +1,11 @@
|
|||
// stdafx.h : include file for standard system include files,
|
||||
// or project specific include files that are used frequently, but
|
||||
// are changed infrequently
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdio.h>
|
||||
#include <tchar.h>
|
||||
|
||||
#include <windows.h>
|
Loading…
Reference in New Issue
Block a user