mirror of https://github.com/trudnai/Steve2.git
- Improved memory management
- speed bumped up a little bit
This commit is contained in:
Tamas Rudnai
parent
115313a40f
commit
c907317419
295
A2Mac/6502.c
295
A2Mac/6502.c
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@ -29,14 +29,24 @@ m6502_s m6502 = {0};
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static inline int m6502_step() {
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// switch ( fetch16() ) {
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// case 0xFCD0: // D0 FC BNE
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// BNE( 0xFC ); return 2;
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//
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// case 0x01E9: // E9 01 SBC
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// SBC( 0x01 ) ; return 6;
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//
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// default:
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// m6502.pc -= 2;
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//
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switch ( fetch() ) {
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case 0x00: BRK(); return 2; // BRK
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case 0x01: ORA( memread( addr_X_ind() ) ); return 6; // ORA X,ind
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// case 0x02: // t jams
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// case 0x03: // SLO* (undocumented)
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// case 0x04: // NOP* (undocumented)
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case 0x05: ORA( memread( fetch() ) ); return 3; // ORA zpg
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case 0x05: ORA( memread_zp( fetch() ) ); return 3; // ORA zpg
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case 0x06: ASL( & RAM[ fetch() ] ); return 5; // ASL zpg
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// case 0x07: // SLO* (undocumented)
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case 0x08: PHP(); return 3; // PHP
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@ -52,7 +62,7 @@ static inline int m6502_step() {
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// case 0x12: // t jams
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// case 0x13: // SLO* (undocumented)
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// case 0x14: // NOP* (undocumented)
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case 0x15: ORA( memread( fetch() + m6502.X ) ); return 4; // ORA zpg,X
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case 0x15: ORA( memread_zp( fetch() + m6502.X ) ); return 4; // ORA zpg,X
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case 0x16: ASL( & RAM[ fetch() + m6502.X ] ); return 6; // ASL zpg,X
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// case 0x17: // SLO* (undocumented)
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case 0x18: CLC(); return 2; // CLC
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@ -67,231 +77,232 @@ static inline int m6502_step() {
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case 0x21: AND( memread( addr_X_ind() ) ); return 6; // AND X,ind
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// case 0x22:
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// case 0x23:
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case 0x24: BIT( memread( fetch() ) ); return 3; // BIT zpg
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case 0x25: AND( memread( fetch() ) ); return 3; // AND zpg
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case 0x24: BIT( memread_zp( fetch() ) ); return 3; // BIT zpg
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case 0x25: AND( memread_zp( fetch() ) ); return 3; // AND zpg
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case 0x26: ROL( & RAM[ fetch() ] ); return 5; // ROL zpg
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// case 0x27:
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case 0x28: PLP(); return 4; // PLP
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case 0x29: AND( fetch() ); return 2; // AND imm
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case 0x2A: ROL( & m6502.A ); return 2; // ROL A
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case 0x28: PLP(); return 4; // PLP
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case 0x29: AND( fetch() ); return 2; // AND imm
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case 0x2A: ROL( & m6502.A ); return 2; // ROL A
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// case 0x2B:
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case 0x2C: BIT( memread( fetch16() ) ); return 4; // BIT abs
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case 0x2D: AND( fetch16() ); return 4; // AND abs
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case 0x2E: ROL( & RAM[ fetch16() ] ); return 6; // ROL abs
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case 0x2C: BIT( memread( fetch16() ) ); return 4; // BIT abs
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case 0x2D: AND( fetch16() ); return 4; // AND abs
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case 0x2E: ROL( & RAM[ fetch16() ] ); return 6; // ROL abs
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// case 0x2F:
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case 0x30: BMI( (int8_t)fetch() ); return 2; // BMI rel
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case 0x31: AND( memread( addr_ind_Y() ) ); return 5; // AND ind,Y
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case 0x30: BMI( (int8_t)fetch() ); return 2; // BMI rel
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case 0x31: AND( memread( addr_ind_Y() ) ); return 5; // AND ind,Y
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// case 0x32:
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// case 0x33:
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// case 0x34:
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case 0x35: AND( memread( addr_zpg_X() ) ); return 4; // AND zpg,X
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case 0x36: ROL( & RAM[ addr_zpg_X() ] ); return 6; // ROL zpg,X
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case 0x35: AND( memread_zp( addr_zp_X() ) ); return 4; // AND zpg,X
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case 0x36: ROL( & RAM[ addr_zp_X() ] ); return 6; // ROL zpg,X
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// case 0x37:
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case 0x38: SEC(); return 2; // SEC
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case 0x39: AND( memread( addr_abs_Y() ) ); return 4; // AND abs,Y
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case 0x38: SEC(); return 2; // SEC
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case 0x39: AND( memread( addr_abs_Y() ) ); return 4; // AND abs,Y
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// case 0x3A:
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// case 0x3B:
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// case 0x3C:
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case 0x3D: AND( memread( addr_abs_X() ) ); return 4; // AND abs,X
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case 0x3E: ROL( & RAM[ addr_abs_X() ] ); return 7; // ROL abs,X
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case 0x3D: AND( memread( addr_abs_X() ) ); return 4; // AND abs,X
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case 0x3E: ROL( & RAM[ addr_abs_X() ] ); return 7; // ROL abs,X
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// case 0x3F:
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case 0x40: RTI(); return 6; // RTI
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case 0x41: EOR( memread( addr_X_ind() ) ); return 6; // EOR X,ind
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case 0x40: RTI(); return 6; // RTI
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case 0x41: EOR( memread( addr_X_ind() ) ); return 6; // EOR X,ind
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// case 0x42:
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// case 0x43:
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// case 0x44:
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case 0x45: EOR( memread( fetch() ) ); return 3; // EOR zpg
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case 0x46: LSR( & RAM[ fetch() ] ); return 5; // LSR zpg
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case 0x45: EOR( memread_zp( fetch() ) ); return 3; // EOR zpg
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case 0x46: LSR( & RAM[ fetch() ] ); return 5; // LSR zpg
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// case 0x47:
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case 0x48: PHA(); return 3; // PHA
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case 0x49: EOR( fetch() ); return 2; // EOR imm
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case 0x4A: LSR( & m6502.A ); return 2; // LSR A
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case 0x48: PHA(); return 3; // PHA
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case 0x49: EOR( fetch() ); return 2; // EOR imm
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case 0x4A: LSR( & m6502.A ); return 2; // LSR A
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// case 0x4B:
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case 0x4C: JMP( fetch16() ); return 3; // JMP abs
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case 0x4D: EOR( fetch16() ); return 4; // EOR abs
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case 0x4E: LSR( & RAM[ fetch16() ] ); return 6; // LSR abs
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case 0x4C: JMP( fetch16() ); return 3; // JMP abs
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case 0x4D: EOR( fetch16() ); return 4; // EOR abs
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case 0x4E: LSR( & RAM[ fetch16() ] ); return 6; // LSR abs
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// case 0x4F:
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case 0x50: BVC( (int8_t)fetch() ); return 2; // BVC rel
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case 0x51: EOR( memread( addr_ind_Y() ) ); return 5; // EOR ind,Y
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case 0x50: BVC( (int8_t)fetch() ); return 2; // BVC rel
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case 0x51: EOR( memread( addr_ind_Y() ) ); return 5; // EOR ind,Y
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// case 0x52:
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// case 0x53:
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// case 0x54:
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case 0x55: EOR( memread( addr_zpg_X() ) ); return 4; // AND zpg,X
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case 0x56: LSR( & RAM[ addr_zpg_X() ] ); return 6; // LSR zpg,X
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case 0x55: EOR( memread_zp( addr_zp_X() ) ); return 4; // AND zpg,X
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case 0x56: LSR( & RAM[ addr_zp_X() ] ); return 6; // LSR zpg,X
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// case 0x57:
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case 0x58: CLI(); return 2; // CLI
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case 0x59: EOR( memread( addr_abs_Y() ) ); return 4; // EOR abs,Y
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case 0x58: CLI(); return 2; // CLI
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case 0x59: EOR( memread( addr_abs_Y() ) ); return 4; // EOR abs,Y
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// case 0x5A:
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// case 0x5B:
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// case 0x5C:
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case 0x5D: EOR( memread( addr_abs_X() ) ); return 4; // EOR abs,X
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case 0x5E: LSR( & RAM[ addr_abs_X() ] ); return 7; // LSR abs,X
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case 0x5D: EOR( memread( addr_abs_X() ) ); return 4; // EOR abs,X
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case 0x5E: LSR( & RAM[ addr_abs_X() ] ); return 7; // LSR abs,X
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// case 0x5F:
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case 0x60: RTS(); return 6; // RTS
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case 0x61: ADC( memread( addr_X_ind() ) ); return 6; // ADC X,ind
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case 0x60: RTS(); return 6; // RTS
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case 0x61: ADC( memread( addr_X_ind() ) ); return 6; // ADC X,ind
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// case 0x62:
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// case 0x63:
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// case 0x64:
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case 0x65: ADC( memread( fetch() ) ); return 3; // ADC zpg
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case 0x66: ROR( & RAM[ fetch() ] ); return 5; // ROR zpg
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case 0x65: ADC( memread_zp( fetch() ) ); return 3; // ADC zpg
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case 0x66: ROR( & RAM[ fetch() ] ); return 5; // ROR zpg
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// case 0x67:
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case 0x68: PLA(); break; // PLA
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case 0x69: ADC( fetch() ); return 2; // ADC imm
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case 0x6A: ROR( & m6502.A ); return 2; // ROR A
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case 0x68: PLA(); break; // PLA
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case 0x69: ADC( fetch() ); return 2; // ADC imm
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case 0x6A: ROR( & m6502.A ); return 2; // ROR A
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// case 0x6B:
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case 0x6C: JMP( memread16( fetch16() ) ); return 5; // JMP ind
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case 0x6D: ADC( memread( fetch16() ) ); return 4; // ADC abs
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case 0x6E: ROR( & RAM[ fetch16() ] ); return 6; // ROR abs
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case 0x6C: JMP( memread16( fetch16() ) ); return 5; // JMP ind
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case 0x6D: ADC( memread( fetch16() ) ); return 4; // ADC abs
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case 0x6E: ROR( & RAM[ fetch16() ] ); return 6; // ROR abs
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// case 0x6F:
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case 0x70: BVS( (int8_t)fetch() ); break; // BVS rel
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case 0x71: ADC( memread( addr_ind_Y() ) ); return 5; // ADC ind,Y
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case 0x70: BVS( (int8_t)fetch() ); break; // BVS rel
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case 0x71: ADC( memread( addr_ind_Y() ) ); return 5; // ADC ind,Y
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// case 0x72:
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// case 0x73:
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// case 0x74:
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case 0x75: ADC( memread( addr_zpg_X() ) ); return 4; // ADC zpg,X
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case 0x76: ROR( & RAM[ addr_zpg_X() ] ); return 6; // ROR zpg,X
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case 0x75: ADC( memread_zp( addr_zp_X() ) ); return 4; // ADC zpg,X
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case 0x76: ROR( & RAM[ addr_zp_X() ] ); return 6; // ROR zpg,X
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// case 0x77:
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case 0x78: SEI(); break; // SEI
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case 0x79: ADC( memread( addr_abs_Y() ) ); return 4; // ADC abs,Y
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case 0x78: SEI(); break; // SEI
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case 0x79: ADC( memread( addr_abs_Y() ) ); return 4; // ADC abs,Y
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// case 0x7A:
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// case 0x7B:
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// case 0x7C:
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case 0x7D: ADC( memread( addr_abs_X() ) ); return 4; // ADC abs,X
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case 0x7E: ROR( & RAM[ addr_abs_X() ] ); return 7; // ROR abs,X
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case 0x7D: ADC( memread( addr_abs_X() ) ); return 4; // ADC abs,X
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case 0x7E: ROR( & RAM[ addr_abs_X() ] ); return 7; // ROR abs,X
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// case 0x7F:
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// case 0x80:
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case 0x81: STA( & RAM[ addr_X_ind() ] ) ; return 6; // STA X,ind
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case 0x81: STA( & RAM[ addr_X_ind() ] ) ; return 6; // STA X,ind
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// case 0x82:
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// case 0x83:
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case 0x84: STY( & RAM[ fetch() ] ); return 3; // STY zpg
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case 0x85: STA( & RAM[ fetch() ] ); return 3; // STA zpg
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case 0x86: STX( & RAM[ fetch() ] ); return 3; // STX zpg
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case 0x84: STY( & RAM[ fetch() ] ); return 3; // STY zpg
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case 0x85: STA( & RAM[ fetch() ] ); return 3; // STA zpg
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case 0x86: STX( & RAM[ fetch() ] ); return 3; // STX zpg
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// case 0x87:
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case 0x88: DEY(); return 2; // DEY
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case 0x88: DEY(); return 2; // DEY
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// case 0x89:
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case 0x8A: TXA(); return 2; // TXA
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case 0x8A: TXA(); return 2; // TXA
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// case 0x8B:
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case 0x8C: STY( & RAM[ fetch16() ] ); return 4; // STY abs
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case 0x8D: STA( & RAM[ fetch16() ] ); return 4; // STA abs
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case 0x8E: STX( & RAM[ fetch16() ] ); return 4; // STX abs
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case 0x8C: STY( & RAM[ fetch16() ] ); return 4; // STY abs
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case 0x8D: STA( & RAM[ fetch16() ] ); return 4; // STA abs
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case 0x8E: STX( & RAM[ fetch16() ] ); return 4; // STX abs
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// case 0x8F:
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case 0x90: BCC( (int8_t)fetch() ); return 2; // BCC rel
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case 0x91: STA( & RAM[ addr_ind_Y() ] ); return 6; // STA ind,Y
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case 0x90: BCC( (int8_t)fetch() ); return 2; // BCC rel
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case 0x91: STA( & RAM[ addr_ind_Y() ] ); return 6; // STA ind,Y
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// case 0x92:
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// case 0x93:
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case 0x94: STY( & RAM[ addr_zpg_X() ] ); return 4; // STY zpg,X
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case 0x95: STA( & RAM[ addr_zpg_X() ] ); return 4; // STA zpg,X
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case 0x96: STX( & RAM[ addr_zpg_Y() ] ); return 4; // STX zpg,Y
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case 0x94: STY( & RAM[ addr_zp_X() ] ); return 4; // STY zpg,X
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case 0x95: STA( & RAM[ addr_zp_X() ] ); return 4; // STA zpg,X
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case 0x96: STX( & RAM[ addr_zp_Y() ] ); return 4; // STX zpg,Y
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// case 0x97:
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case 0x98: TYA(); return 2; // TYA
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case 0x99: STA( & RAM[ addr_abs_Y() ] ); return 5; // STA abs,Y
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case 0x9A: TXS(); return 2; // TXS
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case 0x98: TYA(); return 2; // TYA
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case 0x99: STA( & RAM[ addr_abs_Y() ] ); return 5; // STA abs,Y
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case 0x9A: TXS(); return 2; // TXS
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// case 0x9B:
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// case 0x9C:
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case 0x9D: STA( & RAM[ addr_abs_X() ] ); return 5; // STA abs,X
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case 0x9D: STA( & RAM[ addr_abs_X() ] ); return 5; // STA abs,X
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// case 0x9E:
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// case 0x9F:
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case 0xA0: LDY( fetch() ); return 2; // LDY imm
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case 0xA1: LDA( memread( addr_X_ind() ) ) ; return 6; // LDA X,ind
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case 0xA2: LDX( fetch() ); return 2; // LDX imm
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case 0xA0: LDY( fetch() ); return 2; // LDY imm
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case 0xA1: LDA( memread( addr_X_ind() ) ) ; return 6; // LDA X,ind
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case 0xA2: LDX( fetch() ); return 2; // LDX imm
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// case 0xA3:
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case 0xA4: LDY( memread( fetch() ) ); return 3; // LDY zpg
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case 0xA5: LDA( memread( fetch() ) ); return 3; // LDA zpg
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case 0xA6: LDX( memread( fetch() ) ); return 3; // LDX zpg
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case 0xA4: LDY( memread_zp( fetch() ) ); return 3; // LDY zpg
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case 0xA5: LDA( memread_zp( fetch() ) ); return 3; // LDA zpg
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case 0xA6: LDX( memread_zp( fetch() ) ); return 3; // LDX zpg
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// case 0xA7:
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case 0xA8: TAY(); return 2; // TAY
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case 0xA9: LDA( fetch() ); return 2; // LDA imm
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case 0xAA: TAX(); return 2; // TAX
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case 0xA8: TAY(); return 2; // TAY
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case 0xA9: LDA( fetch() ); return 2; // LDA imm
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case 0xAA: TAX(); return 2; // TAX
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// case 0xAB:
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case 0xAC: LDY( memread( fetch16() ) ); return 4; // LDY abs
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case 0xAD: LDA( memread( fetch16() ) ); return 4; // LDA abs
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case 0xAE: LDX( memread( fetch16() ) ); return 4; // LDX abs
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case 0xAC: LDY( memread( fetch16() ) ); return 4; // LDY abs
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case 0xAD: LDA( memread( fetch16() ) ); return 4; // LDA abs
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case 0xAE: LDX( memread( fetch16() ) ); return 4; // LDX abs
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// case 0xAF:
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case 0xB0: BCS( (int8_t)fetch() ); return 2; // BCS rel
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case 0xB1: LDA( memread( addr_ind_Y() ) ); return 5; // LDA ind,Y
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case 0xB0: BCS( (int8_t)fetch() ); return 2; // BCS rel
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case 0xB1: LDA( memread( addr_ind_Y() ) ); return 5; // LDA ind,Y
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// case 0xB2:
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// case 0xB3:
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case 0xB4: LDY( memread( addr_zpg_X() ) ); return 4; // LDY zpg,X
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case 0xB5: LDA( memread( addr_zpg_X() ) ); return 4; // LDA zpg,X
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case 0xB6: LDX( memread( addr_zpg_Y() ) ); return 4; // LDX zpg,Y
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case 0xB4: LDY( memread_zp( addr_zp_X() ) ); return 4; // LDY zpg,X
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case 0xB5: LDA( memread_zp( addr_zp_X() ) ); return 4; // LDA zpg,X
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case 0xB6: LDX( memread_zp( addr_zp_Y() ) ); return 4; // LDX zpg,Y
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// case 0xB7:
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case 0xB8: CLV(); return 2; // CLV
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case 0xB9: LDA( memread( addr_abs_Y() ) ); return 4; // LDA abs,Y
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case 0xBA: TSX(); return 2; // TSX
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case 0xB8: CLV(); return 2; // CLV
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case 0xB9: LDA( memread( addr_abs_Y() ) ); return 4; // LDA abs,Y
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case 0xBA: TSX(); return 2; // TSX
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// case 0xBB:
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case 0xBC: LDY( memread( addr_abs_X() ) ); return 4; // LDY abs,X
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case 0xBD: LDA( memread( addr_abs_X() ) ); return 4; // LDA abs,X
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case 0xBE: LDX( memread( addr_abs_X() ) ); return 4; // LDX abs,Y
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case 0xBC: LDY( memread( addr_abs_X() ) ); return 4; // LDY abs,X
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case 0xBD: LDA( memread( addr_abs_X() ) ); return 4; // LDA abs,X
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case 0xBE: LDX( memread( addr_abs_X() ) ); return 4; // LDX abs,Y
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// case 0xBF:
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case 0xC0: CPY( fetch() ); break; // CPY imm
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case 0xC1: CMP( memread( addr_X_ind() ) ) ; break; // LDA X,ind
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case 0xC0: CPY( fetch() ); break; // CPY imm
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case 0xC1: CMP( memread( addr_X_ind() ) ) ; break; // LDA X,ind
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// case 0xC2:
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// case 0xC3:
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case 0xC4: CPY( memread( fetch() ) ); return 3; // CPY zpg
|
||||
case 0xC5: CMP( memread( fetch() ) ); return 3; // CMP zpg
|
||||
case 0xC6: DEC( & RAM[ fetch() ] ); return 5; // DEC zpg
|
||||
case 0xC4: CPY( memread_zp( fetch() ) ); return 3; // CPY zpg
|
||||
case 0xC5: CMP( memread_zp( fetch() ) ); return 3; // CMP zpg
|
||||
case 0xC6: DEC( & RAM[ fetch() ] ); return 5; // DEC zpg
|
||||
// case 0xC7:
|
||||
case 0xC8: INY(); return 2; // INY
|
||||
case 0xC9: CMP( fetch() ); return 2; // CMP imm
|
||||
case 0xCA: DEX(); return 2; // DEX
|
||||
case 0xC8: INY(); return 2; // INY
|
||||
case 0xC9: CMP( fetch() ); return 2; // CMP imm
|
||||
case 0xCA: DEX(); return 2; // DEX
|
||||
// case 0xCB:
|
||||
case 0xCC: CPY( memread( fetch16() ) ); return 4; // CPY abs
|
||||
case 0xCD: CMP( fetch16() ); return 4; // CMP abs
|
||||
case 0xCE: DEC( & RAM[ fetch16() ] ); return 4; // DEC abs
|
||||
case 0xCC: CPY( memread( fetch16() ) ); return 4; // CPY abs
|
||||
case 0xCD: CMP( fetch16() ); return 4; // CMP abs
|
||||
case 0xCE: DEC( & RAM[ fetch16() ] ); return 4; // DEC abs
|
||||
// case 0xCF:
|
||||
case 0xD0: BNE( (int8_t)fetch() ); return 2; // BNE rel
|
||||
case 0xD1: CMP( memread( addr_ind_Y() ) ); return 5; // CMP ind,Y
|
||||
case 0xD0: BNE( (int8_t)fetch() ); return 2; // BNE rel
|
||||
case 0xD1: CMP( memread( addr_ind_Y() ) ); return 5; // CMP ind,Y
|
||||
// case 0xD2:
|
||||
// case 0xD3:
|
||||
// case 0xD4:
|
||||
case 0xD5: CMP( memread( addr_zpg_X() ) ); return 4; // CMP zpg,X
|
||||
case 0xD6: DEC( & RAM[ addr_zpg_X() ] ); return 6; // DEC zpg,X
|
||||
case 0xD5: CMP( memread_zp( addr_zp_X() ) ); return 4; // CMP zpg,X
|
||||
case 0xD6: DEC( & RAM[ addr_zp_X() ] ); return 6; // DEC zpg,X
|
||||
// case 0xD7:
|
||||
case 0xD8: CLD(); return 2; // CLD
|
||||
case 0xD9: CMP( memread( addr_abs_Y() ) ); return 4; // CMP abs,Y
|
||||
case 0xD8: CLD(); return 2; // CLD
|
||||
case 0xD9: CMP( memread( addr_abs_Y() ) ); return 4; // CMP abs,Y
|
||||
// case 0xDA:
|
||||
// case 0xDB:
|
||||
// case 0xDC:
|
||||
case 0xDD: CMP( memread( addr_abs_X() ) ); return 4; // CMP abs,X
|
||||
case 0xDE: DEC( & RAM[ addr_abs_X() ] ); return 7; // DEC abs,X
|
||||
case 0xDD: CMP( memread( addr_abs_X() ) ); return 4; // CMP abs,X
|
||||
case 0xDE: DEC( & RAM[ addr_abs_X() ] ); return 7; // DEC abs,X
|
||||
// case 0xDF:
|
||||
case 0xE0: CPX( fetch() ); return 2; // CPX imm
|
||||
case 0xE1: SBC( memread( addr_X_ind() ) ) ; return 6; // SBC (ind,X)
|
||||
case 0xE0: CPX( fetch() ); return 2; // CPX imm
|
||||
case 0xE1: SBC( memread( addr_X_ind() ) ) ; return 6; // SBC (ind,X)
|
||||
// case 0xE2:
|
||||
// case 0xE3:
|
||||
case 0xE4: CPX( memread( fetch() ) ); return 3; // CPX zpg
|
||||
case 0xE5: SBC( memread( fetch() ) ); return 3; // SBC zpg
|
||||
case 0xE6: INC( & RAM[ fetch() ] ); return 5; // INC zpg
|
||||
case 0xE4: CPX( memread_zp( fetch() ) ); return 3; // CPX zpg
|
||||
case 0xE5: SBC( memread_zp( fetch() ) ); return 3; // SBC zpg
|
||||
case 0xE6: INC( & RAM[ fetch() ] ); return 5; // INC zpg
|
||||
// case 0xE7:
|
||||
case 0xE8: INX(); return 2; // INX
|
||||
case 0xE9: SBC( fetch() ); return 2; // SBC imm
|
||||
case 0xEA: NOP(); return 2; // NOP
|
||||
case 0xE8: INX(); return 2; // INX
|
||||
case 0xE9: SBC( fetch() ); return 2; // SBC imm
|
||||
case 0xEA: NOP(); return 2; // NOP
|
||||
// case 0xEB:
|
||||
case 0xEC: CPX( memread( fetch16() ) ); return 4; // CPX abs
|
||||
case 0xED: SBC( fetch16() ); return 4; // SBC abs
|
||||
case 0xEE: INC( & RAM[ fetch16() ] ); return 6; // INC abs
|
||||
case 0xEC: CPX( memread( fetch16() ) ); return 4; // CPX abs
|
||||
case 0xED: SBC( fetch16() ); return 4; // SBC abs
|
||||
case 0xEE: INC( & RAM[ fetch16() ] ); return 6; // INC abs
|
||||
// case 0xEF:
|
||||
case 0xF0: BEQ( (int8_t)fetch() ); return 2; // BEQ rel
|
||||
case 0xF1: SBC( memread( addr_ind_Y() ) ); return 5; // SBC ind,Y
|
||||
case 0xF0: BEQ( (int8_t)fetch() ); return 2; // BEQ rel
|
||||
case 0xF1: SBC( memread( addr_ind_Y() ) ); return 5; // SBC ind,Y
|
||||
// case 0xF2:
|
||||
// case 0xF3:
|
||||
// case 0xF4:
|
||||
case 0xF5: SBC( memread( addr_zpg_X() ) ); return 4; // SBC zpg,X
|
||||
case 0xF6: INC( & RAM[ addr_zpg_X() ] ); return 6; // INC zpg,X
|
||||
case 0xF5: SBC( memread_zp( addr_zp_X() ) ); return 4; // SBC zpg,X
|
||||
case 0xF6: INC( & RAM[ addr_zp_X() ] ); return 6; // INC zpg,X
|
||||
// case 0xF7:
|
||||
case 0xF8: SED(); break; // SED
|
||||
case 0xF9: SBC( memread( addr_abs_Y() ) ); return 4; // SBC abs,Y
|
||||
case 0xF8: SED(); break; // SED
|
||||
case 0xF9: SBC( memread( addr_abs_Y() ) ); return 4; // SBC abs,Y
|
||||
// case 0xFA:
|
||||
// case 0xFB:
|
||||
// case 0xFC:
|
||||
case 0xFD: SBC( memread( addr_abs_X() ) ); return 4; // SBC abs,X
|
||||
case 0xFE: INC( & RAM[ addr_abs_X() ] ); return 6; // INC abs,X
|
||||
case 0xFD: SBC( memread( addr_abs_X() ) ); return 4; // SBC abs,X
|
||||
case 0xFE: INC( & RAM[ addr_abs_X() ] ); return 6; // INC abs,X
|
||||
// case 0xFF:
|
||||
|
||||
default:
|
||||
printf("Unimplemented Instruction 0x%02X\n", memread( m6502.pc -1 ));
|
||||
break;
|
||||
}
|
||||
// } // fetch16
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
|
@ -300,7 +311,7 @@ const unsigned long long int iterations = G;
|
|||
|
||||
unsigned long long TICK_PER_SEC = G;
|
||||
unsigned long long TICK_6502_PER_SEC = 0;
|
||||
unsigned long long MHz_6502 = 1.024 * M;
|
||||
unsigned long long MHz_6502 = 1.023 * M;
|
||||
|
||||
static __inline__ unsigned long long rdtsc(void)
|
||||
{
|
||||
|
|
@ -316,8 +327,8 @@ static inline void m6502_run() {
|
|||
// unsigned long long s = rdtsc();
|
||||
unsigned long long e = (unsigned long long)-1LL;
|
||||
|
||||
// for ( unsigned long long int i = 0; i < iterations ; i++ ) {
|
||||
for ( ; m6502.pc ; ) {
|
||||
for ( unsigned long long int i = 0; i < iterations ; i++ ) {
|
||||
// for ( ; m6502.pc ; ) {
|
||||
dbgPrintf("%04u %04X: ", clktime, m6502.pc);
|
||||
clk = m6502_step();
|
||||
clktime += clk;
|
||||
|
|
@ -333,10 +344,6 @@ static inline void m6502_run() {
|
|||
}
|
||||
|
||||
void init() {
|
||||
// for ( int i = 0; i < 64*1024; i++ ) {
|
||||
// mmio_read[i] = memread;
|
||||
// }
|
||||
|
||||
unsigned long long s = rdtsc();
|
||||
sleep(1);
|
||||
unsigned long long e = rdtsc();
|
||||
|
|
@ -435,7 +442,7 @@ void init() {
|
|||
|
||||
// I have placed NOP to keep addresses
|
||||
|
||||
0xA0, 0x09, // 00 LDY #$09
|
||||
0xA0, 0x06, // 00 LDY #$09
|
||||
0x84, 0x06, // 02 STY #DIGITS
|
||||
|
||||
0xA6, 0x06, // 04 LDY DIGITS
|
||||
|
|
@ -467,9 +474,9 @@ void init() {
|
|||
};
|
||||
|
||||
|
||||
memcpy( RAM + 0x1000, counter_fast, sizeof(counter));
|
||||
// memcpy( RAM + 0x1000, counter_fast, sizeof(counter));
|
||||
|
||||
m6502.pc = 0x1000;
|
||||
// m6502.pc = 0x1000;
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@
|
|||
#define dbgPrintf(format, ...)
|
||||
#endif
|
||||
|
||||
#warning "HHH"
|
||||
|
||||
|
||||
typedef struct m6502_s {
|
||||
uint8_t A; // Accumulator
|
||||
|
|
@ -51,7 +49,7 @@ typedef struct m6502_s {
|
|||
|
||||
|
||||
extern m6502_s m6502;
|
||||
//extern uint8_t RAM[ 64 * 1024 ];
|
||||
extern uint8_t RAM[ 64 * 1024 ];
|
||||
|
||||
extern void tst6502();
|
||||
|
||||
|
|
|
|||
|
|
@ -62,9 +62,17 @@ uint8_t * ram[PAGES] = {
|
|||
|
||||
//uint8_t ( * mmio_read [ 64 * KB ] )( uint16_t addr );
|
||||
|
||||
typedef union address16_u {
|
||||
uint16_t addr;
|
||||
struct {
|
||||
uint8_t offs;
|
||||
uint8_t page;
|
||||
};
|
||||
} address16_t;
|
||||
|
||||
static inline uint8_t mmioRead( uint16_t addr ) {
|
||||
printf("mmio:%04X\n", addr);
|
||||
|
||||
static inline uint8_t ioRead( uint16_t addr ) {
|
||||
// printf("mmio:%04X\n", addr);
|
||||
switch (addr) {
|
||||
case ioSomething:
|
||||
return 123;
|
||||
|
|
@ -75,16 +83,54 @@ static inline uint8_t mmioRead( uint16_t addr ) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline void ioWrite( uint16_t addr ) {
|
||||
// printf("mmio:%04X\n", addr);
|
||||
switch (addr) {
|
||||
case ioSomething:
|
||||
return;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
static inline uint8_t memread( uint16_t addr ) {
|
||||
|
||||
if ( ( addr >= 0xC000 ) && ( addr < 0xD000 ) ) {
|
||||
return mmioRead(addr);
|
||||
static inline uint8_t memread_zp( uint8_t addr ) {
|
||||
return RAM[ addr ];
|
||||
}
|
||||
|
||||
static inline uint8_t memread( uint16_t addr ) {
|
||||
// switch ( ((address16_t)addr).page ) {
|
||||
// case 0xC0:
|
||||
// case 0xC1:
|
||||
// case 0xC2:
|
||||
// case 0xC3:
|
||||
// case 0xC4:
|
||||
// case 0xC5:
|
||||
// case 0xC6:
|
||||
// case 0xC7:
|
||||
// case 0xC8:
|
||||
// case 0xC9:
|
||||
// case 0xCA:
|
||||
// case 0xCB:
|
||||
// case 0xCC:
|
||||
// case 0xCD:
|
||||
// case 0xCE:
|
||||
// case 0xCF:
|
||||
// return ioRead(addr);
|
||||
//
|
||||
// defaut:
|
||||
// break;
|
||||
// }
|
||||
|
||||
if ( (addr >= 0xC000) && (addr < 0xD000) ) {
|
||||
ioRead(addr);
|
||||
}
|
||||
|
||||
dbgPrintf("%02X ", RAM[ addr ]);
|
||||
return RAM[ addr ];
|
||||
}
|
||||
|
||||
|
|
@ -96,7 +142,7 @@ static inline uint16_t memread16( uint16_t addr ) {
|
|||
// return mmioRead(addr);
|
||||
// }
|
||||
|
||||
dbgPrintf("%04X ", * (uint16_t*) (& RAM[ addr ]));
|
||||
// dbgPrintf("%04X ", * (uint16_t*) (& RAM[ addr ]));
|
||||
return * (uint16_t*) (& RAM[ addr ]);
|
||||
}
|
||||
|
||||
|
|
@ -107,22 +153,38 @@ static inline uint16_t memread16( uint16_t addr ) {
|
|||
// return (uint16_t)mmio_read[ addr ](addr);
|
||||
//}
|
||||
|
||||
|
||||
/**
|
||||
Naive implementation of RAM write to address
|
||||
**/
|
||||
static void memwrite_zp( uint8_t addr, uint8_t byte ) {
|
||||
RAM[ addr ] = byte;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Naive implementation of RAM write to address
|
||||
**/
|
||||
static void memwrite( uint16_t addr, uint8_t byte ) {
|
||||
// if ( addr >= 0xD000 ) {
|
||||
// // ROM
|
||||
// return;
|
||||
// }
|
||||
// if ( addr >= 0xC000 ) {
|
||||
// return mmioWrite(addr);
|
||||
// }
|
||||
//
|
||||
|
||||
RAM[ addr ] = byte;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Fetching 1 byte from memory address pc (program counter)
|
||||
increase pc by one
|
||||
**/
|
||||
static inline uint8_t fetch() {
|
||||
// dbgPrintf("%02X ", memread(m6502.pc));
|
||||
// if ( m6502.pc == 0 ) {
|
||||
// printf("******************** finished!!!\n");
|
||||
// }
|
||||
dbgPrintf("%02X ", RAM[m6502.pc]);
|
||||
return memread( m6502.pc++ );
|
||||
}
|
||||
|
||||
|
|
@ -131,7 +193,7 @@ static inline uint8_t fetch() {
|
|||
increase pc by one
|
||||
**/
|
||||
static inline uint16_t fetch16() {
|
||||
// dbgPrintf("%04X ", memread16(m6502.pc));
|
||||
dbgPrintf("%04X ", memread16(m6502.pc));
|
||||
uint16_t word = memread16( m6502.pc );
|
||||
m6502.pc += 2;
|
||||
return word;
|
||||
|
|
@ -140,8 +202,8 @@ static inline uint16_t fetch16() {
|
|||
/**
|
||||
get a 16 bit address from the zp:zp+1
|
||||
**/
|
||||
static inline uint16_t addr_zpg_ind( uint8_t zpg ) {
|
||||
return memread16(zpg);
|
||||
static inline uint16_t addr_zp_ind( uint8_t addr ) {
|
||||
return memread16(addr);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -150,7 +212,7 @@ static inline uint16_t addr_zpg_ind( uint8_t zpg ) {
|
|||
effective address is word in (LL + X, LL + X + 1), inc. without carry: C.w($00LL + X)
|
||||
**/
|
||||
static inline uint16_t addr_X_ind() {
|
||||
return addr_zpg_ind( fetch() + m6502.X );
|
||||
return addr_zp_ind( fetch() + m6502.X );
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -161,7 +223,7 @@ static inline uint16_t addr_X_ind() {
|
|||
static inline uint16_t addr_ind_Y() {
|
||||
uint8_t a = fetch();
|
||||
// dbgPrintf("addr_ind_Y: %04X + %02X = %04X ", addr_zpg_ind( a ), m6502.Y, addr_zpg_ind( a ) + m6502.Y);
|
||||
return addr_zpg_ind( a ) + m6502.Y;
|
||||
return addr_zp_ind( a ) + m6502.Y;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -184,7 +246,7 @@ static inline uint16_t addr_abs_Y() {
|
|||
zpg .... zeropage OPC $LL
|
||||
operand is zeropage address (hi-byte is zero, address = $00LL)
|
||||
**/
|
||||
static inline uint16_t addr_zpg() {
|
||||
static inline uint16_t addr_zp() {
|
||||
return fetch();
|
||||
}
|
||||
|
||||
|
|
@ -193,8 +255,8 @@ static inline uint16_t addr_zpg() {
|
|||
operand is zeropage address;
|
||||
effective address is address incremented by X without carry **
|
||||
**/
|
||||
static inline uint16_t addr_zpg_X() {
|
||||
return addr_zpg() + m6502.X;
|
||||
static inline uint16_t addr_zp_X() {
|
||||
return addr_zp() + m6502.X;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -202,8 +264,8 @@ static inline uint16_t addr_zpg_X() {
|
|||
operand is zeropage address;
|
||||
effective address is address incremented by Y without carry **
|
||||
**/
|
||||
static inline uint16_t addr_zpg_Y() {
|
||||
return addr_zpg() + m6502.Y;
|
||||
static inline uint16_t addr_zp_Y() {
|
||||
return addr_zp() + m6502.Y;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -12,23 +12,61 @@ class ViewController: NSViewController {
|
|||
|
||||
@IBOutlet weak var display: NSTextFieldCell!
|
||||
|
||||
func check() {
|
||||
let ram = UnsafeRawBufferPointer(start: &RAM+0x400, count: 0x400)
|
||||
let string = String(bytes: ram, encoding: .utf8)
|
||||
print(string)
|
||||
}
|
||||
|
||||
|
||||
// func FromBuf(ptr: UnsafeMutablePointer<UInt8>, length len: Int) -> String? {
|
||||
// // convert the bytes using the UTF8 encoding
|
||||
// if let theString = NSString(bytes: ptr, length: len, encoding: NSUTF8StringEncoding) {
|
||||
// return theString as String
|
||||
// } else {
|
||||
// return nil // the bytes aren't valid UTF8
|
||||
// }
|
||||
// }
|
||||
|
||||
override func viewDidLoad() {
|
||||
super.viewDidLoad()
|
||||
display.stringValue = "lll"
|
||||
|
||||
// emulate in he background
|
||||
// DispatchQueue.global(qos: .background).async {
|
||||
DispatchQueue.global(qos: .userInitiated).async {
|
||||
tst6502()
|
||||
}
|
||||
|
||||
// let r = RAM.1
|
||||
|
||||
// let r = UnsafeMutablePointer<UInt8>(RAM)
|
||||
|
||||
// let r = withUnsafeBytes(of: &RAM) { (rawPtr) -> Array<uint8> in
|
||||
// let ptr = rawPtr.baseAddress!.assumingMemoryBound(to: uint8.self)
|
||||
// return Array(ptr)
|
||||
// }
|
||||
|
||||
// let r = UnsafeMutablePointer<UInt8>(RAM)
|
||||
// This seem to work:
|
||||
// var ram: [UInt8] = []
|
||||
// withUnsafeBytes(of: &RAM) {
|
||||
// ram.append(contentsOf: $0)
|
||||
// }
|
||||
// let string = String(bytes: ram, encoding: .utf8)
|
||||
|
||||
// ...but this does not:
|
||||
// let text = ""
|
||||
// while(true) {
|
||||
// for i in 0x400...0x7FF {
|
||||
// // text += r[i]
|
||||
// text += screenBuffer[i]
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
DispatchQueue.main.asyncAfter(deadline: .now() + 5.0, execute: {
|
||||
self.check()
|
||||
})
|
||||
|
||||
}
|
||||
|
||||
override var representedObject: Any? {
|
||||
|
|
|
|||
|
|
@ -92,13 +92,13 @@ char * charConv =
|
|||
static inline void STR( uint8_t * dst, uint8_t imm ) {
|
||||
*dst = imm;
|
||||
|
||||
uint16_t v = dst - RAM;
|
||||
// uint16_t v = dst - RAM;
|
||||
|
||||
if ( ( v >= 0x400 ) && ( v < 0x800 ) ) {
|
||||
char c = charConv[imm];
|
||||
// if ( ( v >= 0x400 ) && ( v < 0x800 ) ) {
|
||||
// char c = charConv[imm];
|
||||
// if (( imm > ' ' ) && ( c < 0x7F ))
|
||||
dbgPrintf("%04X: t:%02X '%c'\n", v, imm, isprint(c) ? c : ' ');
|
||||
}
|
||||
// printf("%04X: t:%02X '%c'\n", v, imm, isprint(c) ? c : ' ');
|
||||
// }
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue